Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	143787751	1			T1	585198		T2	230241		T5	3191
triple_byte_access	2805782	1			T1	1207		T2	4549		T4	1963
halfword_access	4306566	1			T1	1947		T2	6968		T4	3057
byte_access	6021735	1			T1	2397		T2	9286		T4	3948
zero_access	1823733	1			T1	622		T2	2368		T4	989

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79227575

1

T1

298261

T2

126830

T5

1546

auto[1]

79517992

1

T1

293110

T2

126582

T5

1645

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	71610498	1			T1	294833		T2	115333		T5	1546
auto[0]	triple_byte_access	1338979	1			T1	672		T2	2286		T4	980
auto[0]	halfword_access	2104602	1			T1	1100		T2	3465		T4	1523
auto[0]	byte_access	3085731	1			T1	1325		T2	4584		T4	1969
auto[0]	zero_access	1087765	1			T1	331		T2	1162		T4	515
auto[1]	word_access	72177253	1			T1	290365		T2	114908		T5	1645
auto[1]	triple_byte_access	1466803	1			T1	535		T2	2263		T4	983
auto[1]	halfword_access	2201964	1			T1	847		T2	3503		T4	1534
auto[1]	byte_access	2936004	1			T1	1072		T2	4702		T4	1979
auto[1]	zero_access	735968	1			T1	291		T2	1206		T4	474