Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	361897116	1			T1	125290		T3	540374		T4	314484
instr_valid_dis	320707899	1			T1	125290		T3	540374		T4	314484
instr_en	35788111	1			T12	764752		T8	108562		T33	12446

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	14192838	1			T12	189238		T8	58710		T9	15930
sram_ifetch_valid_disable	321788154	1			T1	125290		T3	540374		T4	314484
sram_ifetch_enable	25916124	1			T12	188850		T8	96978		T33	32446

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	361897116	1			T1	125290		T3	540374		T4	314484
hw_debug_en_valid_off	316632624	1			T1	125290		T3	540374		T4	314484
hw_debug_en_on	29543286	1			T12	353566		T8	92268		T33	12446

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	321788154	1			T1	125290		T3	540374		T4	314484
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	303986789	1			T1	125290		T3	540374		T4	314484
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	15418937	1			T12	386664		T8	76154		T9	58132
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5532878	1			T12	34448		T8	37794		T126	14384
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1428630	1			T126	14384		T29	34140		T131	9790
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	3724912	1			T12	34448		T8	18140		T128	16156
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3887842	1			T12	87652		T8	12494		T9	15930
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1791554	1			T8	12494		T9	15930		T126	8730
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1698442	1			T12	87652		T133	15370		T128	43696
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10940036	1			T12	224824		T8	55086		T9	52804
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3902640	1			T8	38104		T133	3860		T29	116442
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	6052688	1			T12	224824		T8	16982		T9	52804

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11607136	1			T12	188850		T8	5846		T33	12446
lc_exec_en	14715408	1			T12	41090		T8	24688		T33	12446
valid_exec_dis	315941432	1			T1	125290		T3	540374		T4	314484
invalid_exec_dis	40108962	1			T12	378088		T8	155688		T33	32446