Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.81 97.15 100.00 100.00 98.61 99.70 98.52


Total tests in report: 1032
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
82.77 82.77 97.66 97.66 74.29 74.29 84.80 84.80 100.00 100.00 90.17 90.17 94.80 94.80 37.66 37.66 /workspace/coverage/default/4.sram_ctrl_lc_escalation.2353589500
89.61 6.84 98.69 1.03 83.03 8.74 90.59 5.79 100.00 0.00 92.13 1.97 96.58 1.78 66.23 28.57 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.96229050
92.93 3.32 99.25 0.56 86.50 3.47 92.37 1.78 100.00 0.00 94.94 2.81 96.73 0.15 80.71 14.47 /workspace/coverage/default/25.sram_ctrl_stress_all.2221685424
95.15 2.22 99.72 0.47 90.87 4.37 98.72 6.36 100.00 0.00 97.75 2.81 97.33 0.59 81.63 0.93 /workspace/coverage/default/1.sram_ctrl_sec_cm.3635511091
96.21 1.06 99.72 0.00 92.67 1.80 98.72 0.00 100.00 0.00 98.60 0.84 97.47 0.15 86.27 4.64 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2960580791
97.04 0.83 99.72 0.00 93.32 0.64 98.72 0.00 100.00 0.00 98.60 0.00 97.47 0.00 91.47 5.19 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3283435764
97.54 0.50 99.72 0.00 93.44 0.13 98.72 0.00 100.00 0.00 98.60 0.00 97.47 0.00 94.81 3.34 /workspace/coverage/default/27.sram_ctrl_stress_all.2182210354
97.79 0.25 99.72 0.00 93.83 0.39 98.72 0.00 100.00 0.00 98.88 0.28 97.47 0.00 95.92 1.11 /workspace/coverage/default/45.sram_ctrl_stress_all.3425689366
97.97 0.18 99.72 0.00 93.83 0.00 98.79 0.07 100.00 0.00 98.88 0.00 98.66 1.19 95.92 0.00 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3150626686
98.14 0.17 99.72 0.00 93.83 0.00 99.22 0.43 100.00 0.00 98.88 0.00 98.66 0.00 96.66 0.74 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2135104495
98.30 0.16 99.72 0.00 94.09 0.26 99.22 0.00 100.00 0.00 98.88 0.00 99.55 0.89 96.66 0.00 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3932589833
98.42 0.11 99.81 0.09 94.09 0.00 99.93 0.71 100.00 0.00 98.88 0.00 99.55 0.00 96.66 0.00 /workspace/coverage/default/12.sram_ctrl_ram_cfg.2679959087
98.52 0.11 99.81 0.00 94.09 0.00 99.93 0.00 100.00 0.00 98.88 0.00 99.55 0.00 97.40 0.74 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2871912576
98.59 0.07 99.81 0.00 94.47 0.39 100.00 0.07 100.00 0.00 98.88 0.00 99.55 0.00 97.40 0.00 /workspace/coverage/default/1.sram_ctrl_alert_test.1956071587
98.64 0.05 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.88 0.00 99.55 0.00 97.77 0.37 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2430241290
98.69 0.05 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.88 0.00 99.55 0.00 98.14 0.37 /workspace/coverage/default/11.sram_ctrl_stress_all.603915211
98.72 0.03 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.88 0.00 99.55 0.00 98.33 0.19 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3611641031
98.75 0.03 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.88 0.00 99.55 0.00 98.52 0.19 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.210619628
98.77 0.02 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.88 0.00 99.70 0.15 98.52 0.00 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.758294595

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1236966838
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.416421389
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2728591023
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1460803147
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.730143021
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2122847921
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2825592418
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.770950173
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1065871941
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3120628427
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1547292698
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.142186953
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3050747917
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4084316521
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2482032618
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2115890984
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.363668039
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3146769915
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.685399644
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1502703539
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3101772580
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3499817463
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3976687764
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2589574609
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3137568497
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1786441336
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1574032700
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2538860176
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.965692173
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2019406851
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.546641364
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1409598116
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.189218792
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2545344216
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3606217690
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4116121850
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1164919650
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1984537450
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2831038844
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1499122651
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.845126173
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3906014044
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3068961945
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.913856799
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2809163532
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.483743167
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3490010716
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2138505811
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1899928653
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1842758401
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.61140369
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3009580278
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1446199852
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3937064269
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3443578041
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1072997071
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1032660657
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.721630483
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.4097419827
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1995887732
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3912962922
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2237949567
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4105947088
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3065956085
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2343026579
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2593456314
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1656398061
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.801624945
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.209305812
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3501900213
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2023652737
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3408695501
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4187641745
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2047788861
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3085303378
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4192096582
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2576713327
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3369310003
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2938396808
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3320725545
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3716884535
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2130417867
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2865016787
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.683357262
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1561874360
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.754518288
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2447700199
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3392467555
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3193937948
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1039211649
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4060347178
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.170038368
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2243964938
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2121668622
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3398299528
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.512101763
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.26513819
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2227061480
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2181118126
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3120841348
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1482344834
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2650300790
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2788229336
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1560948681
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.28044894
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3423210185
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1980278698
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.59158562
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1226387530
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2832343366
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3467791933
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1204729351
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.72349571
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2279536830
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3934522122
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.392547790
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1549344094
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.321175874
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.629631855
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2724993479
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2584207592
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2967035866
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3927165545
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2449837225
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4075295921
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2891816321
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4064132876
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.892645955
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3543090904
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3674248337
/workspace/coverage/default/0.sram_ctrl_alert_test.3128535515
/workspace/coverage/default/0.sram_ctrl_bijection.1361997088
/workspace/coverage/default/0.sram_ctrl_executable.2617623206
/workspace/coverage/default/0.sram_ctrl_lc_escalation.4269226419
/workspace/coverage/default/0.sram_ctrl_max_throughput.3292225909
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2918722060
/workspace/coverage/default/0.sram_ctrl_mem_walk.3185379592
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1416258031
/workspace/coverage/default/0.sram_ctrl_partial_access.679445490
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.238288677
/workspace/coverage/default/0.sram_ctrl_ram_cfg.114816163
/workspace/coverage/default/0.sram_ctrl_regwen.631180721
/workspace/coverage/default/0.sram_ctrl_sec_cm.971878538
/workspace/coverage/default/0.sram_ctrl_smoke.3700374745
/workspace/coverage/default/0.sram_ctrl_stress_all.1511522994
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3392686809
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.52820848
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1399968361
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1988166215
/workspace/coverage/default/1.sram_ctrl_bijection.161309196
/workspace/coverage/default/1.sram_ctrl_executable.743236220
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3559257627
/workspace/coverage/default/1.sram_ctrl_max_throughput.108318023
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3283303019
/workspace/coverage/default/1.sram_ctrl_mem_walk.3672513509
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1291456247
/workspace/coverage/default/1.sram_ctrl_partial_access.1890722611
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3333837051
/workspace/coverage/default/1.sram_ctrl_ram_cfg.584361709
/workspace/coverage/default/1.sram_ctrl_regwen.4237892372
/workspace/coverage/default/1.sram_ctrl_smoke.2637300999
/workspace/coverage/default/1.sram_ctrl_stress_all.982485689
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.4117269644
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2073536294
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2156518800
/workspace/coverage/default/10.sram_ctrl_alert_test.563302410
/workspace/coverage/default/10.sram_ctrl_bijection.2117764822
/workspace/coverage/default/10.sram_ctrl_executable.3257150489
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2942931138
/workspace/coverage/default/10.sram_ctrl_max_throughput.58561199
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1710336491
/workspace/coverage/default/10.sram_ctrl_mem_walk.1154790388
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3327139928
/workspace/coverage/default/10.sram_ctrl_partial_access.2084608901
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2930173987
/workspace/coverage/default/10.sram_ctrl_ram_cfg.736995266
/workspace/coverage/default/10.sram_ctrl_regwen.2373710980
/workspace/coverage/default/10.sram_ctrl_smoke.4149019957
/workspace/coverage/default/10.sram_ctrl_stress_all.2590214853
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1875483704
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2803587593
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1247694516
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1825759081
/workspace/coverage/default/11.sram_ctrl_alert_test.2503794624
/workspace/coverage/default/11.sram_ctrl_bijection.1134465592
/workspace/coverage/default/11.sram_ctrl_executable.3762926554
/workspace/coverage/default/11.sram_ctrl_lc_escalation.673140083
/workspace/coverage/default/11.sram_ctrl_max_throughput.271929787
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1270727915
/workspace/coverage/default/11.sram_ctrl_mem_walk.750954842
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1846448383
/workspace/coverage/default/11.sram_ctrl_partial_access.1110814553
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1162229155
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2187730646
/workspace/coverage/default/11.sram_ctrl_regwen.4021120507
/workspace/coverage/default/11.sram_ctrl_smoke.3693912198
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3171907374
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1207245675
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3469088802
/workspace/coverage/default/12.sram_ctrl_alert_test.3863249601
/workspace/coverage/default/12.sram_ctrl_bijection.764688420
/workspace/coverage/default/12.sram_ctrl_executable.1409942153
/workspace/coverage/default/12.sram_ctrl_lc_escalation.968166391
/workspace/coverage/default/12.sram_ctrl_max_throughput.750685386
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2453599387
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/workspace/coverage/default/43.sram_ctrl_lc_escalation.1826624507
/workspace/coverage/default/43.sram_ctrl_max_throughput.2549371516
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2297520592
/workspace/coverage/default/43.sram_ctrl_mem_walk.4260790626
/workspace/coverage/default/43.sram_ctrl_multiple_keys.995682668
/workspace/coverage/default/43.sram_ctrl_partial_access.1517032027
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3492875159
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2264918849
/workspace/coverage/default/43.sram_ctrl_regwen.2493697319
/workspace/coverage/default/43.sram_ctrl_smoke.3290581009
/workspace/coverage/default/43.sram_ctrl_stress_all.3334857567
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.274858892
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2246173679
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.651812069
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3448197939
/workspace/coverage/default/44.sram_ctrl_alert_test.655852061
/workspace/coverage/default/44.sram_ctrl_bijection.3787786455
/workspace/coverage/default/44.sram_ctrl_executable.2553117825
/workspace/coverage/default/44.sram_ctrl_lc_escalation.267936264
/workspace/coverage/default/44.sram_ctrl_max_throughput.249764304
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.212682822
/workspace/coverage/default/44.sram_ctrl_mem_walk.3399634951
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2141206993
/workspace/coverage/default/44.sram_ctrl_partial_access.1959963400
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.584494648
/workspace/coverage/default/44.sram_ctrl_ram_cfg.511437898
/workspace/coverage/default/44.sram_ctrl_regwen.2719188364
/workspace/coverage/default/44.sram_ctrl_smoke.3496675013
/workspace/coverage/default/44.sram_ctrl_stress_all.2136077945
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1001921206
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2906981897
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2910531859
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1823887225
/workspace/coverage/default/45.sram_ctrl_alert_test.1009525297
/workspace/coverage/default/45.sram_ctrl_bijection.3117487219
/workspace/coverage/default/45.sram_ctrl_executable.430040079
/workspace/coverage/default/45.sram_ctrl_lc_escalation.979183278
/workspace/coverage/default/45.sram_ctrl_max_throughput.3176651320
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.872415980
/workspace/coverage/default/45.sram_ctrl_mem_walk.3311343821
/workspace/coverage/default/45.sram_ctrl_multiple_keys.4056717942
/workspace/coverage/default/45.sram_ctrl_partial_access.3352367820
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1483672858
/workspace/coverage/default/45.sram_ctrl_ram_cfg.639696185
/workspace/coverage/default/45.sram_ctrl_regwen.3278600113
/workspace/coverage/default/45.sram_ctrl_smoke.619076568
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1003731459
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2254966942
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4273728974
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3258097207
/workspace/coverage/default/46.sram_ctrl_alert_test.733747820
/workspace/coverage/default/46.sram_ctrl_bijection.2007828300
/workspace/coverage/default/46.sram_ctrl_executable.4222606495
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1983917900
/workspace/coverage/default/46.sram_ctrl_max_throughput.1843189274
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2312314127
/workspace/coverage/default/46.sram_ctrl_mem_walk.1688931873
/workspace/coverage/default/46.sram_ctrl_multiple_keys.4190941901
/workspace/coverage/default/46.sram_ctrl_partial_access.812391480
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.440066233
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3168727708
/workspace/coverage/default/46.sram_ctrl_regwen.1449042817
/workspace/coverage/default/46.sram_ctrl_smoke.3107043399
/workspace/coverage/default/46.sram_ctrl_stress_all.2692104300
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.4024798635
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.323341535
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.747717097
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3876476008
/workspace/coverage/default/47.sram_ctrl_alert_test.1026111346
/workspace/coverage/default/47.sram_ctrl_bijection.3499435284
/workspace/coverage/default/47.sram_ctrl_executable.3991289927
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3567581692
/workspace/coverage/default/47.sram_ctrl_max_throughput.464315686
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2164838593
/workspace/coverage/default/47.sram_ctrl_mem_walk.1682082037
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1572842998
/workspace/coverage/default/47.sram_ctrl_partial_access.3479546036
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.298284631
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1758773067
/workspace/coverage/default/47.sram_ctrl_regwen.4267200414
/workspace/coverage/default/47.sram_ctrl_smoke.2344465267
/workspace/coverage/default/47.sram_ctrl_stress_all.2735375703
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1973889734
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2094690529
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1697099312
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3850246302
/workspace/coverage/default/48.sram_ctrl_alert_test.1933810475
/workspace/coverage/default/48.sram_ctrl_bijection.2406681892
/workspace/coverage/default/48.sram_ctrl_executable.2084774620
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2542711476
/workspace/coverage/default/48.sram_ctrl_max_throughput.3503215900
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1280373149
/workspace/coverage/default/48.sram_ctrl_mem_walk.639021157
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2515361269
/workspace/coverage/default/48.sram_ctrl_partial_access.2845096582
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1138425482
/workspace/coverage/default/48.sram_ctrl_ram_cfg.4265908958
/workspace/coverage/default/48.sram_ctrl_regwen.1390981468
/workspace/coverage/default/48.sram_ctrl_smoke.1436504951
/workspace/coverage/default/48.sram_ctrl_stress_all.1830839821
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4051538105
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2532639649
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2624267461
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2471697959
/workspace/coverage/default/49.sram_ctrl_alert_test.3900824048
/workspace/coverage/default/49.sram_ctrl_bijection.162687668
/workspace/coverage/default/49.sram_ctrl_executable.1082071122
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1207758238
/workspace/coverage/default/49.sram_ctrl_max_throughput.1215634570
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.185482077
/workspace/coverage/default/49.sram_ctrl_mem_walk.1723411594
/workspace/coverage/default/49.sram_ctrl_multiple_keys.432812062
/workspace/coverage/default/49.sram_ctrl_partial_access.279321143
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3458253763
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3197069353
/workspace/coverage/default/49.sram_ctrl_regwen.3230539268
/workspace/coverage/default/49.sram_ctrl_smoke.2624487393
/workspace/coverage/default/49.sram_ctrl_stress_all.26577163
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.324856990
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2863778208
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4254874590
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1614315210
/workspace/coverage/default/5.sram_ctrl_alert_test.2252180547
/workspace/coverage/default/5.sram_ctrl_bijection.3838713186
/workspace/coverage/default/5.sram_ctrl_executable.554511819
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1491589898
/workspace/coverage/default/5.sram_ctrl_max_throughput.1269535923
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1820534655
/workspace/coverage/default/5.sram_ctrl_mem_walk.4200370689
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1536269816
/workspace/coverage/default/5.sram_ctrl_partial_access.243510709
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1900431474
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1074305443
/workspace/coverage/default/5.sram_ctrl_regwen.4014701388
/workspace/coverage/default/5.sram_ctrl_smoke.3431264245
/workspace/coverage/default/5.sram_ctrl_stress_all.2279627805
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4123156266
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2570523280
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.4127435653
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1576950563
/workspace/coverage/default/6.sram_ctrl_alert_test.3209408007
/workspace/coverage/default/6.sram_ctrl_bijection.1227884115
/workspace/coverage/default/6.sram_ctrl_executable.3903105133
/workspace/coverage/default/6.sram_ctrl_lc_escalation.873570107
/workspace/coverage/default/6.sram_ctrl_max_throughput.2492713888
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1387785518
/workspace/coverage/default/6.sram_ctrl_mem_walk.4212139120
/workspace/coverage/default/6.sram_ctrl_multiple_keys.855686602
/workspace/coverage/default/6.sram_ctrl_partial_access.1840782862
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.726401869
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1548222987
/workspace/coverage/default/6.sram_ctrl_regwen.1671759731
/workspace/coverage/default/6.sram_ctrl_smoke.2130865204
/workspace/coverage/default/6.sram_ctrl_stress_all.2546298391
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.748557473
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.888882210
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1837469701
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1465328926
/workspace/coverage/default/7.sram_ctrl_alert_test.1922308123
/workspace/coverage/default/7.sram_ctrl_bijection.3127003310
/workspace/coverage/default/7.sram_ctrl_executable.1120008458
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3644619852
/workspace/coverage/default/7.sram_ctrl_max_throughput.699923018
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3292633929
/workspace/coverage/default/7.sram_ctrl_mem_walk.176424889
/workspace/coverage/default/7.sram_ctrl_multiple_keys.700837907
/workspace/coverage/default/7.sram_ctrl_partial_access.3437488646
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.293176037
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2007743124
/workspace/coverage/default/7.sram_ctrl_regwen.4247198733
/workspace/coverage/default/7.sram_ctrl_smoke.3159958371
/workspace/coverage/default/7.sram_ctrl_stress_all.393287384
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3152301459
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3420247043
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1632409100
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3449282992
/workspace/coverage/default/8.sram_ctrl_alert_test.1358592169
/workspace/coverage/default/8.sram_ctrl_bijection.1595487521
/workspace/coverage/default/8.sram_ctrl_executable.2965086535
/workspace/coverage/default/8.sram_ctrl_lc_escalation.367363341
/workspace/coverage/default/8.sram_ctrl_max_throughput.4203418878
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1420144775
/workspace/coverage/default/8.sram_ctrl_mem_walk.2144743284
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3130188600
/workspace/coverage/default/8.sram_ctrl_partial_access.45444693
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3534397719
/workspace/coverage/default/8.sram_ctrl_ram_cfg.4150577364
/workspace/coverage/default/8.sram_ctrl_regwen.1632496461
/workspace/coverage/default/8.sram_ctrl_smoke.2622134431
/workspace/coverage/default/8.sram_ctrl_stress_all.3451533624
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1115068693
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3348212492
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1601471412
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1173627290
/workspace/coverage/default/9.sram_ctrl_alert_test.3409814360
/workspace/coverage/default/9.sram_ctrl_bijection.2817976597
/workspace/coverage/default/9.sram_ctrl_executable.2000939756
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1184031298
/workspace/coverage/default/9.sram_ctrl_max_throughput.3763277782
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2633812521
/workspace/coverage/default/9.sram_ctrl_mem_walk.2051251084
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1401889060
/workspace/coverage/default/9.sram_ctrl_partial_access.1544821837
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.309098447
/workspace/coverage/default/9.sram_ctrl_ram_cfg.234940162
/workspace/coverage/default/9.sram_ctrl_regwen.2760247101
/workspace/coverage/default/9.sram_ctrl_smoke.4205058241
/workspace/coverage/default/9.sram_ctrl_stress_all.3327313966
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2990577478
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2059536296
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1755483455



Total test records in report: 1032
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2918722060 Mar 31 03:00:11 PM PDT 24 Mar 31 03:02:10 PM PDT 24 6203566136 ps
T2 /workspace/coverage/default/7.sram_ctrl_ram_cfg.2007743124 Mar 31 03:01:28 PM PDT 24 Mar 31 03:01:31 PM PDT 24 4206059484 ps
T3 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2955559372 Mar 31 03:05:40 PM PDT 24 Mar 31 03:11:11 PM PDT 24 19302715184 ps
T4 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1648418224 Mar 31 03:06:40 PM PDT 24 Mar 31 03:28:35 PM PDT 24 10758030299 ps
T11 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2244777805 Mar 31 03:10:48 PM PDT 24 Mar 31 03:11:06 PM PDT 24 716189593 ps
T5 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1632409100 Mar 31 03:01:28 PM PDT 24 Mar 31 03:02:08 PM PDT 24 1525046911 ps
T12 /workspace/coverage/default/25.sram_ctrl_stress_all.2221685424 Mar 31 03:05:44 PM PDT 24 Mar 31 04:53:08 PM PDT 24 125953902458 ps
T6 /workspace/coverage/default/25.sram_ctrl_mem_walk.3400395535 Mar 31 03:05:43 PM PDT 24 Mar 31 03:08:11 PM PDT 24 27547524658 ps
T7 /workspace/coverage/default/4.sram_ctrl_lc_escalation.2353589500 Mar 31 03:00:52 PM PDT 24 Mar 31 03:01:47 PM PDT 24 17123248161 ps
T13 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.183814117 Mar 31 03:07:23 PM PDT 24 Mar 31 03:09:14 PM PDT 24 3562887215 ps
T19 /workspace/coverage/default/23.sram_ctrl_bijection.3673489962 Mar 31 03:04:53 PM PDT 24 Mar 31 03:27:48 PM PDT 24 50028517166 ps
T61 /workspace/coverage/default/4.sram_ctrl_max_throughput.3956984169 Mar 31 03:00:53 PM PDT 24 Mar 31 03:01:34 PM PDT 24 1527546819 ps
T20 /workspace/coverage/default/45.sram_ctrl_smoke.619076568 Mar 31 03:12:00 PM PDT 24 Mar 31 03:12:10 PM PDT 24 685332434 ps
T34 /workspace/coverage/default/34.sram_ctrl_ram_cfg.3815996145 Mar 31 03:08:34 PM PDT 24 Mar 31 03:08:38 PM PDT 24 3034225634 ps
T23 /workspace/coverage/default/20.sram_ctrl_alert_test.1170142951 Mar 31 03:04:16 PM PDT 24 Mar 31 03:04:17 PM PDT 24 51313910 ps
T8 /workspace/coverage/default/17.sram_ctrl_stress_all.3471479901 Mar 31 03:03:32 PM PDT 24 Mar 31 04:35:18 PM PDT 24 68547687724 ps
T44 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1681760411 Mar 31 03:08:16 PM PDT 24 Mar 31 03:10:40 PM PDT 24 11230860488 ps
T17 /workspace/coverage/default/40.sram_ctrl_smoke.683732949 Mar 31 03:10:18 PM PDT 24 Mar 31 03:10:34 PM PDT 24 4219335094 ps
T35 /workspace/coverage/default/3.sram_ctrl_ram_cfg.38148344 Mar 31 03:00:41 PM PDT 24 Mar 31 03:00:45 PM PDT 24 1462185811 ps
T141 /workspace/coverage/default/41.sram_ctrl_multiple_keys.1213725678 Mar 31 03:10:40 PM PDT 24 Mar 31 03:14:21 PM PDT 24 5300250745 ps
T144 /workspace/coverage/default/33.sram_ctrl_mem_walk.1097795288 Mar 31 03:08:16 PM PDT 24 Mar 31 03:12:21 PM PDT 24 17129409765 ps
T24 /workspace/coverage/default/22.sram_ctrl_alert_test.1315137926 Mar 31 03:04:53 PM PDT 24 Mar 31 03:04:55 PM PDT 24 14566950 ps
T72 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2246173679 Mar 31 03:11:25 PM PDT 24 Mar 31 03:16:20 PM PDT 24 25762126523 ps
T10 /workspace/coverage/default/48.sram_ctrl_lc_escalation.2542711476 Mar 31 03:13:17 PM PDT 24 Mar 31 03:13:24 PM PDT 24 4569217365 ps
T18 /workspace/coverage/default/1.sram_ctrl_bijection.161309196 Mar 31 03:00:18 PM PDT 24 Mar 31 03:13:40 PM PDT 24 52271072362 ps
T145 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3892774632 Mar 31 03:03:12 PM PDT 24 Mar 31 03:03:24 PM PDT 24 9770168486 ps
T14 /workspace/coverage/default/1.sram_ctrl_sec_cm.3635511091 Mar 31 03:00:30 PM PDT 24 Mar 31 03:00:33 PM PDT 24 308461535 ps
T38 /workspace/coverage/default/34.sram_ctrl_smoke.569745054 Mar 31 03:08:24 PM PDT 24 Mar 31 03:08:43 PM PDT 24 4974782190 ps
T22 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3932589833 Mar 31 03:08:45 PM PDT 24 Mar 31 03:11:31 PM PDT 24 5211370812 ps
T15 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.4093140297 Mar 31 03:03:49 PM PDT 24 Mar 31 03:06:07 PM PDT 24 9960624544 ps
T39 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3348212492 Mar 31 03:01:32 PM PDT 24 Mar 31 03:04:24 PM PDT 24 5944045225 ps
T25 /workspace/coverage/default/1.sram_ctrl_alert_test.1956071587 Mar 31 03:00:28 PM PDT 24 Mar 31 03:00:29 PM PDT 24 11863535 ps
T40 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2624267461 Mar 31 03:13:17 PM PDT 24 Mar 31 03:13:37 PM PDT 24 755576180 ps
T41 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1823887225 Mar 31 03:12:10 PM PDT 24 Mar 31 03:30:38 PM PDT 24 26269050444 ps
T21 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.96229050 Mar 31 03:02:25 PM PDT 24 Mar 31 03:02:36 PM PDT 24 413279607 ps
T16 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2960580791 Mar 31 03:07:00 PM PDT 24 Mar 31 03:12:55 PM PDT 24 68794769000 ps
T52 /workspace/coverage/default/42.sram_ctrl_bijection.1274583808 Mar 31 03:11:00 PM PDT 24 Mar 31 03:54:41 PM PDT 24 281212501606 ps
T33 /workspace/coverage/default/47.sram_ctrl_executable.3991289927 Mar 31 03:12:58 PM PDT 24 Mar 31 03:13:24 PM PDT 24 2080697438 ps
T53 /workspace/coverage/default/13.sram_ctrl_partial_access.713275718 Mar 31 03:02:30 PM PDT 24 Mar 31 03:02:51 PM PDT 24 2473919514 ps
T9 /workspace/coverage/default/45.sram_ctrl_stress_all.3425689366 Mar 31 03:12:26 PM PDT 24 Mar 31 03:28:16 PM PDT 24 168697306839 ps
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T78 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2453599387 Mar 31 03:02:32 PM PDT 24 Mar 31 03:05:01 PM PDT 24 9139241320 ps
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T172 /workspace/coverage/default/41.sram_ctrl_mem_walk.3626577157 Mar 31 03:10:53 PM PDT 24 Mar 31 03:16:03 PM PDT 24 21515057077 ps
T29 /workspace/coverage/default/27.sram_ctrl_stress_all.2182210354 Mar 31 03:06:24 PM PDT 24 Mar 31 04:27:07 PM PDT 24 45794734987 ps
T173 /workspace/coverage/default/9.sram_ctrl_max_throughput.3763277782 Mar 31 03:01:52 PM PDT 24 Mar 31 03:03:17 PM PDT 24 833151464 ps
T174 /workspace/coverage/default/14.sram_ctrl_mem_walk.715616146 Mar 31 03:02:50 PM PDT 24 Mar 31 03:06:53 PM PDT 24 3943172283 ps
T128 /workspace/coverage/default/6.sram_ctrl_executable.3903105133 Mar 31 03:01:13 PM PDT 24 Mar 31 03:16:42 PM PDT 24 15958064315 ps
T175 /workspace/coverage/default/32.sram_ctrl_max_throughput.3744489202 Mar 31 03:07:54 PM PDT 24 Mar 31 03:08:56 PM PDT 24 772216975 ps
T176 /workspace/coverage/default/10.sram_ctrl_mem_walk.1154790388 Mar 31 03:02:06 PM PDT 24 Mar 31 03:06:59 PM PDT 24 21529466252 ps
T97 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3522381707 Mar 31 03:06:28 PM PDT 24 Mar 31 03:11:32 PM PDT 24 28738066586 ps
T177 /workspace/coverage/default/47.sram_ctrl_ram_cfg.1758773067 Mar 31 03:12:58 PM PDT 24 Mar 31 03:13:02 PM PDT 24 1409950537 ps
T98 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2863778208 Mar 31 03:13:33 PM PDT 24 Mar 31 03:19:01 PM PDT 24 20412081411 ps
T178 /workspace/coverage/default/33.sram_ctrl_bijection.676535920 Mar 31 03:08:07 PM PDT 24 Mar 31 03:41:52 PM PDT 24 163927345222 ps
T89 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.1109510491 Mar 31 03:05:04 PM PDT 24 Mar 31 03:17:10 PM PDT 24 43834783034 ps
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T179 /workspace/coverage/default/2.sram_ctrl_partial_access.3527227697 Mar 31 03:00:28 PM PDT 24 Mar 31 03:01:14 PM PDT 24 1434453136 ps
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T180 /workspace/coverage/default/36.sram_ctrl_bijection.2006055041 Mar 31 03:08:52 PM PDT 24 Mar 31 03:35:46 PM PDT 24 52063256447 ps
T181 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1755483455 Mar 31 03:01:51 PM PDT 24 Mar 31 03:02:30 PM PDT 24 754809372 ps
T131 /workspace/coverage/default/2.sram_ctrl_regwen.4135094364 Mar 31 03:00:35 PM PDT 24 Mar 31 03:12:08 PM PDT 24 5070815171 ps
T182 /workspace/coverage/default/24.sram_ctrl_executable.4233707078 Mar 31 03:05:24 PM PDT 24 Mar 31 03:17:15 PM PDT 24 45531136853 ps
T183 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.238288677 Mar 31 03:00:10 PM PDT 24 Mar 31 03:05:04 PM PDT 24 5430339979 ps
T184 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.541324118 Mar 31 03:00:53 PM PDT 24 Mar 31 03:07:23 PM PDT 24 19014323733 ps
T185 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.4150684375 Mar 31 03:04:03 PM PDT 24 Mar 31 03:09:31 PM PDT 24 5566675118 ps
T186 /workspace/coverage/default/15.sram_ctrl_lc_escalation.927919038 Mar 31 03:02:53 PM PDT 24 Mar 31 03:03:34 PM PDT 24 6917470023 ps
T90 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1173627290 Mar 31 03:01:49 PM PDT 24 Mar 31 03:19:49 PM PDT 24 17373182987 ps
T187 /workspace/coverage/default/37.sram_ctrl_mem_walk.3485526857 Mar 31 03:09:29 PM PDT 24 Mar 31 03:11:48 PM PDT 24 18131030795 ps
T188 /workspace/coverage/default/46.sram_ctrl_max_throughput.1843189274 Mar 31 03:12:28 PM PDT 24 Mar 31 03:14:01 PM PDT 24 812974031 ps
T47 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3306419069 Mar 31 03:04:29 PM PDT 24 Mar 31 03:04:36 PM PDT 24 627311168 ps
T189 /workspace/coverage/default/42.sram_ctrl_alert_test.2296299235 Mar 31 03:11:21 PM PDT 24 Mar 31 03:11:22 PM PDT 24 53441982 ps
T190 /workspace/coverage/default/6.sram_ctrl_alert_test.3209408007 Mar 31 03:01:23 PM PDT 24 Mar 31 03:01:24 PM PDT 24 45907860 ps
T191 /workspace/coverage/default/18.sram_ctrl_lc_escalation.1439032825 Mar 31 03:03:42 PM PDT 24 Mar 31 03:04:46 PM PDT 24 19949104739 ps
T192 /workspace/coverage/default/15.sram_ctrl_mem_walk.757732582 Mar 31 03:03:02 PM PDT 24 Mar 31 03:08:00 PM PDT 24 86161540988 ps
T193 /workspace/coverage/default/45.sram_ctrl_regwen.3278600113 Mar 31 03:12:15 PM PDT 24 Mar 31 03:22:47 PM PDT 24 2130911906 ps
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T132 /workspace/coverage/default/3.sram_ctrl_executable.744746148 Mar 31 03:00:42 PM PDT 24 Mar 31 03:07:16 PM PDT 24 27449859752 ps
T48 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1768561022 Mar 31 03:08:34 PM PDT 24 Mar 31 03:09:22 PM PDT 24 929763585 ps
T194 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1021180211 Mar 31 03:09:00 PM PDT 24 Mar 31 03:09:16 PM PDT 24 1433800316 ps
T43 /workspace/coverage/default/44.sram_ctrl_stress_all.2136077945 Mar 31 03:12:01 PM PDT 24 Mar 31 03:26:28 PM PDT 24 28314367100 ps
T195 /workspace/coverage/default/5.sram_ctrl_max_throughput.1269535923 Mar 31 03:00:59 PM PDT 24 Mar 31 03:02:19 PM PDT 24 4440349214 ps
T196 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3792668741 Mar 31 03:08:52 PM PDT 24 Mar 31 03:11:16 PM PDT 24 8922947097 ps
T134 /workspace/coverage/default/23.sram_ctrl_regwen.2856622282 Mar 31 03:05:02 PM PDT 24 Mar 31 03:16:05 PM PDT 24 11426259345 ps
T197 /workspace/coverage/default/20.sram_ctrl_lc_escalation.3269706194 Mar 31 03:04:09 PM PDT 24 Mar 31 03:04:42 PM PDT 24 5279298983 ps
T198 /workspace/coverage/default/27.sram_ctrl_max_throughput.1836793989 Mar 31 03:06:15 PM PDT 24 Mar 31 03:06:23 PM PDT 24 11084109146 ps
T199 /workspace/coverage/default/49.sram_ctrl_lc_escalation.1207758238 Mar 31 03:13:46 PM PDT 24 Mar 31 03:15:04 PM PDT 24 49294626727 ps
T200 /workspace/coverage/default/6.sram_ctrl_multiple_keys.855686602 Mar 31 03:01:05 PM PDT 24 Mar 31 03:11:47 PM PDT 24 14967008233 ps
T201 /workspace/coverage/default/11.sram_ctrl_alert_test.2503794624 Mar 31 03:02:23 PM PDT 24 Mar 31 03:02:24 PM PDT 24 43504348 ps
T49 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2135104495 Mar 31 03:06:50 PM PDT 24 Mar 31 03:07:41 PM PDT 24 1999817371 ps
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T202 /workspace/coverage/default/13.sram_ctrl_bijection.2619706884 Mar 31 03:02:32 PM PDT 24 Mar 31 03:18:54 PM PDT 24 49168729689 ps
T203 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3058446531 Mar 31 03:04:54 PM PDT 24 Mar 31 03:11:22 PM PDT 24 22889082267 ps
T204 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.461238863 Mar 31 03:10:52 PM PDT 24 Mar 31 03:11:52 PM PDT 24 1986329168 ps
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T207 /workspace/coverage/default/1.sram_ctrl_max_throughput.108318023 Mar 31 03:00:26 PM PDT 24 Mar 31 03:02:17 PM PDT 24 3053044115 ps
T51 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3690069298 Mar 31 03:00:53 PM PDT 24 Mar 31 03:01:07 PM PDT 24 4392653863 ps
T208 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1391954740 Mar 31 03:09:47 PM PDT 24 Mar 31 03:20:51 PM PDT 24 10994520169 ps
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T210 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.641058366 Mar 31 03:04:22 PM PDT 24 Mar 31 03:10:12 PM PDT 24 10084113497 ps
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T139 /workspace/coverage/default/35.sram_ctrl_regwen.212367686 Mar 31 03:08:47 PM PDT 24 Mar 31 03:20:59 PM PDT 24 54228602330 ps
T213 /workspace/coverage/default/30.sram_ctrl_smoke.2427133110 Mar 31 03:07:10 PM PDT 24 Mar 31 03:07:34 PM PDT 24 625965812 ps
T214 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.3189701767 Mar 31 03:07:11 PM PDT 24 Mar 31 03:10:35 PM PDT 24 15412327181 ps
T215 /workspace/coverage/default/49.sram_ctrl_partial_access.279321143 Mar 31 03:13:32 PM PDT 24 Mar 31 03:15:16 PM PDT 24 20362762586 ps
T216 /workspace/coverage/default/13.sram_ctrl_ram_cfg.4262726912 Mar 31 03:02:39 PM PDT 24 Mar 31 03:02:43 PM PDT 24 676692722 ps
T217 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2111715376 Mar 31 03:03:30 PM PDT 24 Mar 31 03:07:11 PM PDT 24 3590408390 ps
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T220 /workspace/coverage/default/33.sram_ctrl_regwen.2484203673 Mar 31 03:08:15 PM PDT 24 Mar 31 03:19:27 PM PDT 24 12151218464 ps
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T223 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.4273257296 Mar 31 03:04:52 PM PDT 24 Mar 31 03:10:59 PM PDT 24 61313563232 ps
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T225 /workspace/coverage/default/5.sram_ctrl_partial_access.243510709 Mar 31 03:01:00 PM PDT 24 Mar 31 03:01:22 PM PDT 24 4591424105 ps
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T228 /workspace/coverage/default/23.sram_ctrl_partial_access.322203465 Mar 31 03:04:52 PM PDT 24 Mar 31 03:07:30 PM PDT 24 2007227754 ps
T229 /workspace/coverage/default/34.sram_ctrl_partial_access.2361018540 Mar 31 03:08:28 PM PDT 24 Mar 31 03:08:47 PM PDT 24 809300225 ps
T140 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.684804522 Mar 31 03:07:16 PM PDT 24 Mar 31 03:11:36 PM PDT 24 50915264423 ps
T230 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3789924243 Mar 31 03:03:55 PM PDT 24 Mar 31 03:12:26 PM PDT 24 6058042192 ps
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T232 /workspace/coverage/default/7.sram_ctrl_bijection.3127003310 Mar 31 03:01:21 PM PDT 24 Mar 31 03:41:28 PM PDT 24 111724854333 ps
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T234 /workspace/coverage/default/41.sram_ctrl_executable.129645950 Mar 31 03:10:53 PM PDT 24 Mar 31 03:18:17 PM PDT 24 59297133556 ps
T235 /workspace/coverage/default/7.sram_ctrl_alert_test.1922308123 Mar 31 03:01:33 PM PDT 24 Mar 31 03:01:33 PM PDT 24 18378841 ps
T236 /workspace/coverage/default/28.sram_ctrl_max_throughput.2389837614 Mar 31 03:06:32 PM PDT 24 Mar 31 03:08:39 PM PDT 24 3081207948 ps
T237 /workspace/coverage/default/13.sram_ctrl_alert_test.1539380844 Mar 31 03:02:40 PM PDT 24 Mar 31 03:02:41 PM PDT 24 34078391 ps
T238 /workspace/coverage/default/4.sram_ctrl_executable.2994441393 Mar 31 03:00:54 PM PDT 24 Mar 31 03:16:32 PM PDT 24 301487155648 ps
T239 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2228680240 Mar 31 03:10:32 PM PDT 24 Mar 31 03:12:27 PM PDT 24 772908966 ps
T240 /workspace/coverage/default/14.sram_ctrl_ram_cfg.1062486342 Mar 31 03:02:47 PM PDT 24 Mar 31 03:02:50 PM PDT 24 1400699554 ps
T241 /workspace/coverage/default/16.sram_ctrl_ram_cfg.2641695366 Mar 31 03:03:24 PM PDT 24 Mar 31 03:03:27 PM PDT 24 361048098 ps
T242 /workspace/coverage/default/48.sram_ctrl_ram_cfg.4265908958 Mar 31 03:13:28 PM PDT 24 Mar 31 03:13:31 PM PDT 24 347817052 ps
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T244 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1843205354 Mar 31 03:05:16 PM PDT 24 Mar 31 03:09:06 PM PDT 24 21295549123 ps
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T298 /workspace/coverage/default/47.sram_ctrl_alert_test.1026111346 Mar 31 03:13:04 PM PDT 24 Mar 31 03:13:05 PM PDT 24 17320919 ps
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T304 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.1097008881 Mar 31 03:06:22 PM PDT 24 Mar 31 03:08:51 PM PDT 24 4694283526 ps
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