Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	152551172	1			T1	3193		T3	245532		T4	143031
triple_byte_access	2768231	1			T1	7119		T3	5006		T4	2785
halfword_access	4252651	1			T1	13279		T3	7219		T4	4185
byte_access	5964279	1			T1	24660		T3	9874		T4	5778
zero_access	1819803	1			T1	14394		T3	2556		T4	1463

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83369485

1

T1

31088

T3

135466

T4

78920

auto[1]

83986651

1

T1

31557

T3

134721

T4

78322

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	75830051	1			T1	271		T3	123188		T4	71853
auto[0]	triple_byte_access	1315633	1			T1	1299		T3	2435		T4	1350
auto[0]	halfword_access	2073819	1			T1	4661		T3	3657		T4	2081
auto[0]	byte_access	3056156	1			T1	13295		T3	4897		T4	2898
auto[0]	zero_access	1093826	1			T1	11562		T3	1289		T4	738
auto[1]	word_access	76721121	1			T1	2922		T3	122344		T4	71178
auto[1]	triple_byte_access	1452598	1			T1	5820		T3	2571		T4	1435
auto[1]	halfword_access	2178832	1			T1	8618		T3	3562		T4	2104
auto[1]	byte_access	2908123	1			T1	11365		T3	4977		T4	2880
auto[1]	zero_access	725977	1			T1	2832		T3	1267		T4	725