Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	369366828	1			T1	20000		T2	467490		T3	11314
instr_valid_dis	305886174	1			T1	20000		T2	467490		T3	11314
instr_en	46613339	1			T9	416526		T36	48348		T37	194486

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	18964194	1			T20	44186		T9	333288		T37	37620
sram_ifetch_valid_disable	316910320	1			T1	20000		T2	467490		T3	11314
sram_ifetch_enable	33492314	1			T20	34800		T9	405006		T36	110394

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	369366828	1			T1	20000		T2	467490		T3	11314
hw_debug_en_valid_off	315682455	1			T1	20000		T2	467490		T3	11314
hw_debug_en_on	36083227	1			T20	17386		T9	618678		T36	88064

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	316910320	1			T1	20000		T2	467490		T3	11314
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	291566784	1			T1	20000		T2	467490		T3	11314
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	20742195	1			T9	245622		T36	9700		T37	115258
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6973932	1			T20	178		T9	80900		T117	46202
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1297566	1			T20	178		T9	18166		T32	22220
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	4709940	1			T9	42734		T58	3774		T33	5296
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7508720	1			T9	248628		T37	18038		T117	38806
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1514354	1			T9	159574		T117	38806		T32	27252
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2024584	1			T9	51256		T37	18038		T58	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	14510487	1			T20	17386		T9	109202		T37	103554
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3447242	1			T20	17386		T9	103232		T37	72410
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	8926999	1			T9	5970		T37	19056		T117	32012

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	16200658	1			T9	76914		T36	38648		T37	61190
lc_exec_en	14064020	1			T9	260848		T36	88064		T37	165050
valid_exec_dis	304444875	1			T1	20000		T2	467490		T3	11314
invalid_exec_dis	52456508	1			T20	78986		T9	738294		T36	110394