Name |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1746236898 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2924247770 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3123219471 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2576315477 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4178736418 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3990111907 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1886981305 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4157730967 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2115284522 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.876243845 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3135566070 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3854221747 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.975285954 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3414881445 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2284866960 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1817531577 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4080796400 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1348131648 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2464905525 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.92363286 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1888486655 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1868955311 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3148163834 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1824397527 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.252456102 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.912849078 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3775219367 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.707634025 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.317506423 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.689762945 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2277064799 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.367760528 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1305334426 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1578778710 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2828361297 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.172426151 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3369038814 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2393900017 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1827544671 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3712895182 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1794124708 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.430416068 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3405243902 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3811661742 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4193628216 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.681526636 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.812292299 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3855382924 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3983913919 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.673327429 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2205435785 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1219754596 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1852497124 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.6955576 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.501672341 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1701467607 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1493394082 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2068810834 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1510557057 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2449667886 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.57338703 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.536027808 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1462276808 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.285916819 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.811159433 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2492335823 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.609592453 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1389471857 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1056219857 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2523700290 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2306006447 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1624526297 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3350813691 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2660363074 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.236261282 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.373013265 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1619498583 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3552654060 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3033228963 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3399561771 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2365417392 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1098250734 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1389073798 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2842888501 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1644437414 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.242562366 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.311532049 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1653881402 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3943408738 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.536812239 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.721841128 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.788084049 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3595276048 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3967529352 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.697355428 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2120853622 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.423973006 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.366476327 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.95669565 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.448325930 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1282673561 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.570430310 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.18959860 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3684676747 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3908296853 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2653349892 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1952077137 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3055092886 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1843480825 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.120303238 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1483433558 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3269936330 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3651087056 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.77664401 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3263822438 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3111591685 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2175653742 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4081599823 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1273306008 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2459488733 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3333341838 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2653426721 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3629634503 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1791910763 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4086606093 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.949428122 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1309180998 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2875524061 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.589344878 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2944913083 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1937324592 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2270643675 |
/workspace/coverage/default/0.sram_ctrl_bijection.18346258 |
/workspace/coverage/default/0.sram_ctrl_executable.727574322 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2942045664 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.1728158532 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.156260016 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.1149325919 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3157847603 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3863358219 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2327847502 |
/workspace/coverage/default/0.sram_ctrl_regwen.820011022 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.4215575747 |
/workspace/coverage/default/0.sram_ctrl_smoke.1824479031 |
/workspace/coverage/default/0.sram_ctrl_stress_all.1119911819 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1671473618 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.734210893 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3983598838 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3385629355 |
/workspace/coverage/default/1.sram_ctrl_alert_test.4116422202 |
/workspace/coverage/default/1.sram_ctrl_bijection.126868958 |
/workspace/coverage/default/1.sram_ctrl_executable.2559416416 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3721959512 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.570947174 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3292297618 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.2324792984 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.907113757 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1105672503 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1417280378 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3704719560 |
/workspace/coverage/default/1.sram_ctrl_regwen.3617626406 |
/workspace/coverage/default/1.sram_ctrl_smoke.2988049565 |
/workspace/coverage/default/1.sram_ctrl_stress_all.2089191220 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.31675675 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3168851259 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.406576848 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2214937065 |
/workspace/coverage/default/10.sram_ctrl_alert_test.226105747 |
/workspace/coverage/default/10.sram_ctrl_bijection.1119030273 |
/workspace/coverage/default/10.sram_ctrl_executable.190369364 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2758869052 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.2956865588 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.581628379 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.1326818494 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3129081401 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2025477597 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3419233814 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2300396405 |
/workspace/coverage/default/10.sram_ctrl_regwen.4228907106 |
/workspace/coverage/default/10.sram_ctrl_smoke.1147124053 |
/workspace/coverage/default/10.sram_ctrl_stress_all.2710152583 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.214023488 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.576103909 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1783258479 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2403010620 |
/workspace/coverage/default/11.sram_ctrl_alert_test.490068696 |
/workspace/coverage/default/11.sram_ctrl_bijection.252732028 |
/workspace/coverage/default/11.sram_ctrl_executable.4220865322 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.4984952 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.3070219764 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1044252847 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.1189348664 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.822947117 |
/workspace/coverage/default/11.sram_ctrl_partial_access.1531961233 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2747374850 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2095713534 |
/workspace/coverage/default/11.sram_ctrl_regwen.207854745 |
/workspace/coverage/default/11.sram_ctrl_smoke.1383366700 |
/workspace/coverage/default/11.sram_ctrl_stress_all.1750568032 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.55664064 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2848498309 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3136982514 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3251797760 |
/workspace/coverage/default/12.sram_ctrl_alert_test.3888762789 |
/workspace/coverage/default/12.sram_ctrl_bijection.3432041086 |
/workspace/coverage/default/12.sram_ctrl_executable.1967949730 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2657533786 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.3718717193 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3930898691 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.4003369699 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2714494727 |
/workspace/coverage/default/12.sram_ctrl_partial_access.1119264782 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.589266130 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.421350400 |
/workspace/coverage/default/12.sram_ctrl_smoke.386819201 |
/workspace/coverage/default/12.sram_ctrl_stress_all.3628033969 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2495079326 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.479266182 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2758775671 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3207974202 |
/workspace/coverage/default/13.sram_ctrl_alert_test.224194379 |
/workspace/coverage/default/13.sram_ctrl_bijection.3050520006 |
/workspace/coverage/default/13.sram_ctrl_executable.735293518 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2735265630 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.3933142397 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.605377620 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.3401200183 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.3269089501 |
/workspace/coverage/default/13.sram_ctrl_partial_access.3622932496 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3651834972 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.2777637802 |
/workspace/coverage/default/13.sram_ctrl_regwen.1226321855 |
/workspace/coverage/default/13.sram_ctrl_smoke.3089004095 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1214586959 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2410340984 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.1868021259 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2951282982 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3908180653 |
/workspace/coverage/default/14.sram_ctrl_alert_test.3961696625 |
/workspace/coverage/default/14.sram_ctrl_bijection.4053418517 |
/workspace/coverage/default/14.sram_ctrl_executable.1701555950 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.3635941487 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.2375264346 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.2801976518 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1233914132 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.2742984324 |
/workspace/coverage/default/14.sram_ctrl_partial_access.3246581883 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.501207335 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.906897672 |
/workspace/coverage/default/14.sram_ctrl_regwen.1793151041 |
/workspace/coverage/default/14.sram_ctrl_smoke.3387569016 |
/workspace/coverage/default/14.sram_ctrl_stress_all.1962435371 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2595922070 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.3408259140 |
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/workspace/coverage/default/44.sram_ctrl_alert_test.467065830 |
/workspace/coverage/default/44.sram_ctrl_bijection.3441278378 |
/workspace/coverage/default/44.sram_ctrl_executable.745014665 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2754095626 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.2752504139 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.837684909 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1109985137 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3744115677 |
/workspace/coverage/default/44.sram_ctrl_partial_access.1817487901 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.474699843 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.84091269 |
/workspace/coverage/default/44.sram_ctrl_regwen.839323875 |
/workspace/coverage/default/44.sram_ctrl_smoke.3723454211 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3594729249 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1269097831 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2550177664 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2052532030 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.637109441 |
/workspace/coverage/default/45.sram_ctrl_alert_test.1764870569 |
/workspace/coverage/default/45.sram_ctrl_bijection.913190895 |
/workspace/coverage/default/45.sram_ctrl_executable.3628567074 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2314583918 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2043599058 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1154092247 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.51943807 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1013155489 |
/workspace/coverage/default/45.sram_ctrl_partial_access.4138134294 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3454437102 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2443779339 |
/workspace/coverage/default/45.sram_ctrl_regwen.731977885 |
/workspace/coverage/default/45.sram_ctrl_smoke.3551669396 |
/workspace/coverage/default/45.sram_ctrl_stress_all.2956470245 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1128376633 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2594676480 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3475204597 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.888386645 |
/workspace/coverage/default/46.sram_ctrl_alert_test.3474815420 |
/workspace/coverage/default/46.sram_ctrl_bijection.740502168 |
/workspace/coverage/default/46.sram_ctrl_executable.657453367 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.943683665 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.4246654561 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1606915317 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.66673239 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.471486528 |
/workspace/coverage/default/46.sram_ctrl_partial_access.522299659 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2358616664 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2147519154 |
/workspace/coverage/default/46.sram_ctrl_regwen.747326865 |
/workspace/coverage/default/46.sram_ctrl_smoke.4034980193 |
/workspace/coverage/default/46.sram_ctrl_stress_all.246338761 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2102877782 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.362773106 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1600218900 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.4010428530 |
/workspace/coverage/default/47.sram_ctrl_alert_test.957201679 |
/workspace/coverage/default/47.sram_ctrl_bijection.865201622 |
/workspace/coverage/default/47.sram_ctrl_executable.2219571206 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2996545003 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.418380808 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1642514404 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.211880174 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.326434835 |
/workspace/coverage/default/47.sram_ctrl_partial_access.3009546520 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3901045706 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.4049983673 |
/workspace/coverage/default/47.sram_ctrl_regwen.386322375 |
/workspace/coverage/default/47.sram_ctrl_smoke.2152245602 |
/workspace/coverage/default/47.sram_ctrl_stress_all.1457351729 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.90278001 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.16502383 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.878335015 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3117715058 |
/workspace/coverage/default/48.sram_ctrl_alert_test.3950638477 |
/workspace/coverage/default/48.sram_ctrl_bijection.632604028 |
/workspace/coverage/default/48.sram_ctrl_executable.3338051423 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1587576104 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3307917505 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.4099650772 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.3625729087 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.854074720 |
/workspace/coverage/default/48.sram_ctrl_partial_access.3699111438 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.258466332 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.941239466 |
/workspace/coverage/default/48.sram_ctrl_regwen.3838768148 |
/workspace/coverage/default/48.sram_ctrl_smoke.2511806396 |
/workspace/coverage/default/48.sram_ctrl_stress_all.2847252573 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.847383675 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2349907288 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3897118890 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1847657445 |
/workspace/coverage/default/49.sram_ctrl_alert_test.4210221847 |
/workspace/coverage/default/49.sram_ctrl_bijection.1789777090 |
/workspace/coverage/default/49.sram_ctrl_executable.829106859 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3415846835 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2891009780 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1282943227 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.2679521956 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1407912423 |
/workspace/coverage/default/49.sram_ctrl_partial_access.3461083209 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2607556792 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3469323948 |
/workspace/coverage/default/49.sram_ctrl_regwen.3001925875 |
/workspace/coverage/default/49.sram_ctrl_smoke.1683098875 |
/workspace/coverage/default/49.sram_ctrl_stress_all.1828562562 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.488012579 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4042536106 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.655933194 |
/workspace/coverage/default/5.sram_ctrl_alert_test.3907834234 |
/workspace/coverage/default/5.sram_ctrl_bijection.3073756408 |
/workspace/coverage/default/5.sram_ctrl_executable.2927163769 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2395577851 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.3885994664 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2861281120 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.100593275 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.949232732 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1053346506 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1622887467 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3406050204 |
/workspace/coverage/default/5.sram_ctrl_regwen.3692543166 |
/workspace/coverage/default/5.sram_ctrl_smoke.1433292318 |
/workspace/coverage/default/5.sram_ctrl_stress_all.748735399 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.729044291 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2555431347 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1042993805 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1430301473 |
/workspace/coverage/default/6.sram_ctrl_alert_test.771985831 |
/workspace/coverage/default/6.sram_ctrl_bijection.2370581893 |
/workspace/coverage/default/6.sram_ctrl_executable.1076627275 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.937069414 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.1156717208 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3642080934 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.3650074073 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1245221969 |
/workspace/coverage/default/6.sram_ctrl_partial_access.426760376 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1002824970 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.961995627 |
/workspace/coverage/default/6.sram_ctrl_regwen.2336839422 |
/workspace/coverage/default/6.sram_ctrl_smoke.3972566748 |
/workspace/coverage/default/6.sram_ctrl_stress_all.167709769 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2049530884 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2535510000 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3854608588 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.289356331 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2642114334 |
/workspace/coverage/default/7.sram_ctrl_bijection.979945706 |
/workspace/coverage/default/7.sram_ctrl_executable.1759517337 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3889577532 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.2415600886 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.4020835220 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.438207627 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2721657728 |
/workspace/coverage/default/7.sram_ctrl_partial_access.603905593 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1645701533 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1648454599 |
/workspace/coverage/default/7.sram_ctrl_regwen.2640526013 |
/workspace/coverage/default/7.sram_ctrl_smoke.2121176514 |
/workspace/coverage/default/7.sram_ctrl_stress_all.3373898285 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3823421984 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.4238975581 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2956129839 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1636268676 |
/workspace/coverage/default/8.sram_ctrl_alert_test.916302808 |
/workspace/coverage/default/8.sram_ctrl_bijection.1759017042 |
/workspace/coverage/default/8.sram_ctrl_executable.3216718194 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.304534994 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.2189505714 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3003114366 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.2459081934 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.4227632848 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3142358373 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.132624611 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2549471614 |
/workspace/coverage/default/8.sram_ctrl_regwen.2169208759 |
/workspace/coverage/default/8.sram_ctrl_smoke.901866945 |
/workspace/coverage/default/8.sram_ctrl_stress_all.749137239 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3224398334 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.704951129 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.223519484 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.586657479 |
/workspace/coverage/default/9.sram_ctrl_alert_test.1876588541 |
/workspace/coverage/default/9.sram_ctrl_bijection.98555654 |
/workspace/coverage/default/9.sram_ctrl_executable.1390717970 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2952903952 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3244984948 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2378448135 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.2015079034 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.95920363 |
/workspace/coverage/default/9.sram_ctrl_partial_access.3850954476 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3018774814 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.4078423491 |
/workspace/coverage/default/9.sram_ctrl_regwen.467813554 |
/workspace/coverage/default/9.sram_ctrl_smoke.3081305167 |
/workspace/coverage/default/9.sram_ctrl_stress_all.2457997161 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.833609106 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.851434848 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2454403995 |
TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
T1 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.1544812154 |
|
|
Apr 02 02:31:29 PM PDT 24 |
Apr 02 02:34:07 PM PDT 24 |
771623933 ps |
T2 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3643417662 |
|
|
Apr 02 02:35:56 PM PDT 24 |
Apr 02 02:41:31 PM PDT 24 |
11515367055 ps |
T3 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.2415600886 |
|
|
Apr 02 02:28:10 PM PDT 24 |
Apr 02 02:28:41 PM PDT 24 |
1473107942 ps |
T4 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3908180653 |
|
|
Apr 02 02:30:08 PM PDT 24 |
Apr 02 02:35:27 PM PDT 24 |
92047466377 ps |
T12 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2167235523 |
|
|
Apr 02 02:39:54 PM PDT 24 |
Apr 02 02:40:40 PM PDT 24 |
753241905 ps |
T5 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.3392217526 |
|
|
Apr 02 02:36:24 PM PDT 24 |
Apr 02 02:41:27 PM PDT 24 |
5705995572 ps |
T6 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.252511935 |
|
|
Apr 02 02:32:26 PM PDT 24 |
Apr 02 02:41:28 PM PDT 24 |
26298707169 ps |
T13 |
/workspace/coverage/default/26.sram_ctrl_smoke.1642986689 |
|
|
Apr 02 02:34:33 PM PDT 24 |
Apr 02 02:34:38 PM PDT 24 |
702327655 ps |
T7 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.1688459560 |
|
|
Apr 02 02:33:12 PM PDT 24 |
Apr 02 02:35:44 PM PDT 24 |
25256510892 ps |
T14 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3292297618 |
|
|
Apr 02 02:27:03 PM PDT 24 |
Apr 02 02:29:01 PM PDT 24 |
1583231319 ps |
T16 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3233499635 |
|
|
Apr 02 02:39:55 PM PDT 24 |
Apr 02 02:40:16 PM PDT 24 |
5459664932 ps |
T17 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2520583697 |
|
|
Apr 02 02:37:27 PM PDT 24 |
Apr 02 02:37:41 PM PDT 24 |
5839408042 ps |
T18 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.3703242894 |
|
|
Apr 02 02:30:42 PM PDT 24 |
Apr 02 02:39:10 PM PDT 24 |
7418551345 ps |
T28 |
/workspace/coverage/default/48.sram_ctrl_bijection.632604028 |
|
|
Apr 02 02:41:12 PM PDT 24 |
Apr 02 03:25:08 PM PDT 24 |
171805424583 ps |
T89 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.2317003546 |
|
|
Apr 02 02:31:06 PM PDT 24 |
Apr 02 02:35:13 PM PDT 24 |
17140878843 ps |
T94 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3504005748 |
|
|
Apr 02 02:33:23 PM PDT 24 |
Apr 02 02:33:37 PM PDT 24 |
708610366 ps |
T22 |
/workspace/coverage/default/28.sram_ctrl_alert_test.2669247770 |
|
|
Apr 02 02:35:47 PM PDT 24 |
Apr 02 02:35:48 PM PDT 24 |
33702937 ps |
T29 |
/workspace/coverage/default/45.sram_ctrl_bijection.913190895 |
|
|
Apr 02 02:40:41 PM PDT 24 |
Apr 02 02:48:03 PM PDT 24 |
7190906679 ps |
T21 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.781536259 |
|
|
Apr 02 02:39:49 PM PDT 24 |
Apr 02 02:48:20 PM PDT 24 |
10746406166 ps |
T19 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1370702127 |
|
|
Apr 02 02:41:34 PM PDT 24 |
Apr 02 02:42:00 PM PDT 24 |
1792724163 ps |
T30 |
/workspace/coverage/default/32.sram_ctrl_bijection.22537531 |
|
|
Apr 02 02:36:53 PM PDT 24 |
Apr 02 03:20:51 PM PDT 24 |
229999377049 ps |
T57 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.3700650306 |
|
|
Apr 02 02:39:45 PM PDT 24 |
Apr 02 02:40:24 PM PDT 24 |
729960313 ps |
T38 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.2070025124 |
|
|
Apr 02 02:39:10 PM PDT 24 |
Apr 02 02:39:14 PM PDT 24 |
700551399 ps |
T11 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.761648672 |
|
|
Apr 02 02:27:08 PM PDT 24 |
Apr 02 02:27:12 PM PDT 24 |
1056258937 ps |
T20 |
/workspace/coverage/default/48.sram_ctrl_regwen.3838768148 |
|
|
Apr 02 02:41:17 PM PDT 24 |
Apr 02 02:45:53 PM PDT 24 |
4571747253 ps |
T43 |
/workspace/coverage/default/17.sram_ctrl_bijection.42357590 |
|
|
Apr 02 02:31:02 PM PDT 24 |
Apr 02 02:47:41 PM PDT 24 |
30751862762 ps |
T44 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2454403995 |
|
|
Apr 02 02:28:46 PM PDT 24 |
Apr 02 02:29:27 PM PDT 24 |
777766835 ps |
T45 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.2216984443 |
|
|
Apr 02 02:33:08 PM PDT 24 |
Apr 02 02:35:44 PM PDT 24 |
18745384021 ps |
T46 |
/workspace/coverage/default/18.sram_ctrl_smoke.4158353727 |
|
|
Apr 02 02:31:22 PM PDT 24 |
Apr 02 02:31:37 PM PDT 24 |
639426032 ps |
T15 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2874177316 |
|
|
Apr 02 02:40:19 PM PDT 24 |
Apr 02 02:48:06 PM PDT 24 |
31918013854 ps |
T8 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.3635941487 |
|
|
Apr 02 02:30:09 PM PDT 24 |
Apr 02 02:31:17 PM PDT 24 |
41735177731 ps |
T47 |
/workspace/coverage/default/47.sram_ctrl_smoke.2152245602 |
|
|
Apr 02 02:41:01 PM PDT 24 |
Apr 02 02:41:20 PM PDT 24 |
1732166784 ps |
T48 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2594676480 |
|
|
Apr 02 02:40:39 PM PDT 24 |
Apr 02 02:46:40 PM PDT 24 |
5293011055 ps |
T9 |
/workspace/coverage/default/27.sram_ctrl_stress_all.2777900089 |
|
|
Apr 02 02:35:21 PM PDT 24 |
Apr 02 03:32:35 PM PDT 24 |
140958727395 ps |
T36 |
/workspace/coverage/default/19.sram_ctrl_executable.2695902134 |
|
|
Apr 02 02:32:00 PM PDT 24 |
Apr 02 02:35:54 PM PDT 24 |
3234328564 ps |
T39 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.1107528005 |
|
|
Apr 02 02:34:56 PM PDT 24 |
Apr 02 02:35:00 PM PDT 24 |
1405869401 ps |
T120 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1407912423 |
|
|
Apr 02 02:41:34 PM PDT 24 |
Apr 02 02:56:52 PM PDT 24 |
16550632223 ps |
T23 |
/workspace/coverage/default/10.sram_ctrl_alert_test.226105747 |
|
|
Apr 02 02:29:04 PM PDT 24 |
Apr 02 02:29:05 PM PDT 24 |
31973603 ps |
T124 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.588205446 |
|
|
Apr 02 02:31:07 PM PDT 24 |
Apr 02 02:32:01 PM PDT 24 |
3041418978 ps |
T70 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1053346506 |
|
|
Apr 02 02:27:46 PM PDT 24 |
Apr 02 02:29:33 PM PDT 24 |
7200980272 ps |
T25 |
/workspace/coverage/default/35.sram_ctrl_alert_test.3738175892 |
|
|
Apr 02 02:38:23 PM PDT 24 |
Apr 02 02:38:24 PM PDT 24 |
47545859 ps |
T75 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.3750499281 |
|
|
Apr 02 02:35:18 PM PDT 24 |
Apr 02 02:36:31 PM PDT 24 |
9835583023 ps |
T40 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.4132221501 |
|
|
Apr 02 02:36:25 PM PDT 24 |
Apr 02 02:36:28 PM PDT 24 |
1348814309 ps |
T125 |
/workspace/coverage/default/46.sram_ctrl_partial_access.522299659 |
|
|
Apr 02 02:40:50 PM PDT 24 |
Apr 02 02:41:04 PM PDT 24 |
733105998 ps |
T90 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2550177664 |
|
|
Apr 02 02:40:26 PM PDT 24 |
Apr 02 02:44:34 PM PDT 24 |
4733415950 ps |
T37 |
/workspace/coverage/default/28.sram_ctrl_executable.1784002832 |
|
|
Apr 02 02:35:36 PM PDT 24 |
Apr 02 02:54:34 PM PDT 24 |
35474908148 ps |
T91 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.501207335 |
|
|
Apr 02 02:30:03 PM PDT 24 |
Apr 02 02:34:42 PM PDT 24 |
12249501193 ps |
T121 |
/workspace/coverage/default/43.sram_ctrl_bijection.276402811 |
|
|
Apr 02 02:40:15 PM PDT 24 |
Apr 02 03:03:30 PM PDT 24 |
304186368488 ps |
T126 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.80737937 |
|
|
Apr 02 02:27:24 PM PDT 24 |
Apr 02 02:27:57 PM PDT 24 |
3024346530 ps |
T123 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.1230093908 |
|
|
Apr 02 02:30:34 PM PDT 24 |
Apr 02 02:30:38 PM PDT 24 |
1413549906 ps |
T76 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2964321640 |
|
|
Apr 02 02:39:37 PM PDT 24 |
Apr 02 02:40:53 PM PDT 24 |
9066837743 ps |
T117 |
/workspace/coverage/default/22.sram_ctrl_executable.2249848600 |
|
|
Apr 02 02:33:05 PM PDT 24 |
Apr 02 02:47:33 PM PDT 24 |
9304982232 ps |
T31 |
/workspace/coverage/default/3.sram_ctrl_regwen.731868934 |
|
|
Apr 02 02:27:25 PM PDT 24 |
Apr 02 02:29:02 PM PDT 24 |
10857432700 ps |
T127 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.570947174 |
|
|
Apr 02 02:26:58 PM PDT 24 |
Apr 02 02:28:59 PM PDT 24 |
842395954 ps |
T122 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.2248226061 |
|
|
Apr 02 02:39:32 PM PDT 24 |
Apr 02 03:03:07 PM PDT 24 |
10064531657 ps |
T34 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3767817418 |
|
|
Apr 02 02:39:35 PM PDT 24 |
Apr 02 02:40:56 PM PDT 24 |
1679477798 ps |
T128 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2391246050 |
|
|
Apr 02 02:34:12 PM PDT 24 |
Apr 02 02:35:56 PM PDT 24 |
828071448 ps |
T58 |
/workspace/coverage/default/26.sram_ctrl_stress_all.2247638931 |
|
|
Apr 02 02:34:59 PM PDT 24 |
Apr 02 03:46:29 PM PDT 24 |
240947239045 ps |
T35 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3760750732 |
|
|
Apr 02 02:37:16 PM PDT 24 |
Apr 02 02:37:43 PM PDT 24 |
2636189439 ps |
T49 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2705781431 |
|
|
Apr 02 02:38:53 PM PDT 24 |
Apr 02 02:39:34 PM PDT 24 |
1647232267 ps |
T129 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.418380808 |
|
|
Apr 02 02:41:08 PM PDT 24 |
Apr 02 02:41:24 PM PDT 24 |
1401975188 ps |
T32 |
/workspace/coverage/default/12.sram_ctrl_regwen.3118756963 |
|
|
Apr 02 02:29:36 PM PDT 24 |
Apr 02 02:41:53 PM PDT 24 |
46181341180 ps |
T77 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1636268676 |
|
|
Apr 02 02:28:27 PM PDT 24 |
Apr 02 02:42:40 PM PDT 24 |
15268090657 ps |
T92 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3018774814 |
|
|
Apr 02 02:29:09 PM PDT 24 |
Apr 02 02:33:55 PM PDT 24 |
28892280180 ps |
T130 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.3953966718 |
|
|
Apr 02 02:33:19 PM PDT 24 |
Apr 02 02:42:38 PM PDT 24 |
12101906202 ps |
T78 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3308741802 |
|
|
Apr 02 02:38:25 PM PDT 24 |
Apr 02 02:39:26 PM PDT 24 |
989620042 ps |
T79 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.4047593907 |
|
|
Apr 02 02:38:49 PM PDT 24 |
Apr 02 02:39:48 PM PDT 24 |
995329274 ps |
T131 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1630549302 |
|
|
Apr 02 02:38:14 PM PDT 24 |
Apr 02 02:43:40 PM PDT 24 |
13749667942 ps |
T80 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.156260016 |
|
|
Apr 02 02:26:50 PM PDT 24 |
Apr 02 02:28:08 PM PDT 24 |
2479266092 ps |
T59 |
/workspace/coverage/default/7.sram_ctrl_regwen.2640526013 |
|
|
Apr 02 02:28:13 PM PDT 24 |
Apr 02 02:38:18 PM PDT 24 |
2301611566 ps |
T132 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.2951458738 |
|
|
Apr 02 02:33:24 PM PDT 24 |
Apr 02 02:34:22 PM PDT 24 |
838859733 ps |
T50 |
/workspace/coverage/default/2.sram_ctrl_executable.2874606700 |
|
|
Apr 02 02:27:14 PM PDT 24 |
Apr 02 02:33:49 PM PDT 24 |
19880306780 ps |
T133 |
/workspace/coverage/default/37.sram_ctrl_partial_access.4227482393 |
|
|
Apr 02 02:38:59 PM PDT 24 |
Apr 02 02:39:10 PM PDT 24 |
798926536 ps |
T134 |
/workspace/coverage/default/15.sram_ctrl_executable.3090882001 |
|
|
Apr 02 02:30:35 PM PDT 24 |
Apr 02 02:34:28 PM PDT 24 |
4237400865 ps |
T10 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.2302840312 |
|
|
Apr 02 02:35:33 PM PDT 24 |
Apr 02 02:36:51 PM PDT 24 |
24742909803 ps |
T33 |
/workspace/coverage/default/22.sram_ctrl_regwen.2549522830 |
|
|
Apr 02 02:33:08 PM PDT 24 |
Apr 02 02:35:51 PM PDT 24 |
11266914902 ps |
T118 |
/workspace/coverage/default/48.sram_ctrl_executable.3338051423 |
|
|
Apr 02 02:41:15 PM PDT 24 |
Apr 02 02:55:25 PM PDT 24 |
15865868849 ps |
T135 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3594729249 |
|
|
Apr 02 02:40:37 PM PDT 24 |
Apr 02 03:54:42 PM PDT 24 |
188746118883 ps |
T136 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.1566431224 |
|
|
Apr 02 02:37:50 PM PDT 24 |
Apr 02 02:38:44 PM PDT 24 |
1517396087 ps |
T137 |
/workspace/coverage/default/30.sram_ctrl_smoke.1007620088 |
|
|
Apr 02 02:36:12 PM PDT 24 |
Apr 02 02:36:21 PM PDT 24 |
1891003520 ps |
T138 |
/workspace/coverage/default/19.sram_ctrl_smoke.2278063439 |
|
|
Apr 02 02:31:43 PM PDT 24 |
Apr 02 02:31:51 PM PDT 24 |
5066394455 ps |
T139 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.438207627 |
|
|
Apr 02 02:28:18 PM PDT 24 |
Apr 02 02:30:42 PM PDT 24 |
43090307236 ps |
T119 |
/workspace/coverage/default/35.sram_ctrl_regwen.1606795799 |
|
|
Apr 02 02:38:17 PM PDT 24 |
Apr 02 02:56:46 PM PDT 24 |
21603573086 ps |
T140 |
/workspace/coverage/default/12.sram_ctrl_bijection.3432041086 |
|
|
Apr 02 02:29:26 PM PDT 24 |
Apr 02 03:01:15 PM PDT 24 |
106253190901 ps |
T141 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.1716895947 |
|
|
Apr 02 02:39:42 PM PDT 24 |
Apr 02 02:43:45 PM PDT 24 |
49222993311 ps |
T24 |
/workspace/coverage/default/22.sram_ctrl_alert_test.1075509526 |
|
|
Apr 02 02:33:17 PM PDT 24 |
Apr 02 02:33:18 PM PDT 24 |
22057647 ps |
T142 |
/workspace/coverage/default/15.sram_ctrl_smoke.1894829979 |
|
|
Apr 02 02:30:23 PM PDT 24 |
Apr 02 02:30:33 PM PDT 24 |
643678339 ps |
T143 |
/workspace/coverage/default/5.sram_ctrl_regwen.3692543166 |
|
|
Apr 02 02:27:51 PM PDT 24 |
Apr 02 02:40:22 PM PDT 24 |
12397482527 ps |
T144 |
/workspace/coverage/default/43.sram_ctrl_smoke.2234896696 |
|
|
Apr 02 02:40:15 PM PDT 24 |
Apr 02 02:41:08 PM PDT 24 |
3113400161 ps |
T145 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.961995627 |
|
|
Apr 02 02:27:57 PM PDT 24 |
Apr 02 02:28:00 PM PDT 24 |
690186207 ps |
T146 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1245221969 |
|
|
Apr 02 02:27:53 PM PDT 24 |
Apr 02 02:39:41 PM PDT 24 |
42588909815 ps |
T147 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.1604052622 |
|
|
Apr 02 02:36:04 PM PDT 24 |
Apr 02 02:38:06 PM PDT 24 |
2017118525 ps |
T148 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.1237029409 |
|
|
Apr 02 02:32:42 PM PDT 24 |
Apr 02 02:33:10 PM PDT 24 |
10589183956 ps |
T149 |
/workspace/coverage/default/16.sram_ctrl_regwen.3127900374 |
|
|
Apr 02 02:30:52 PM PDT 24 |
Apr 02 02:39:09 PM PDT 24 |
26312735655 ps |
T150 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.949232732 |
|
|
Apr 02 02:27:42 PM PDT 24 |
Apr 02 02:44:53 PM PDT 24 |
70089208375 ps |
T151 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.150950723 |
|
|
Apr 02 02:36:30 PM PDT 24 |
Apr 02 02:41:45 PM PDT 24 |
13526445505 ps |
T152 |
/workspace/coverage/default/21.sram_ctrl_regwen.1556201876 |
|
|
Apr 02 02:32:46 PM PDT 24 |
Apr 02 02:52:26 PM PDT 24 |
13002959016 ps |
T153 |
/workspace/coverage/default/36.sram_ctrl_alert_test.40639395 |
|
|
Apr 02 02:38:53 PM PDT 24 |
Apr 02 02:38:54 PM PDT 24 |
20095498 ps |
T154 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3251797760 |
|
|
Apr 02 02:29:34 PM PDT 24 |
Apr 02 02:41:48 PM PDT 24 |
10364253694 ps |
T155 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.3011730270 |
|
|
Apr 02 02:32:22 PM PDT 24 |
Apr 02 02:32:35 PM PDT 24 |
7418877074 ps |
T156 |
/workspace/coverage/default/20.sram_ctrl_regwen.190967656 |
|
|
Apr 02 02:32:28 PM PDT 24 |
Apr 02 02:42:28 PM PDT 24 |
12019937726 ps |
T157 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.304534994 |
|
|
Apr 02 02:28:27 PM PDT 24 |
Apr 02 02:29:31 PM PDT 24 |
13799075025 ps |
T158 |
/workspace/coverage/default/39.sram_ctrl_executable.3884237809 |
|
|
Apr 02 02:39:39 PM PDT 24 |
Apr 02 02:49:37 PM PDT 24 |
6214469715 ps |
T159 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.430472274 |
|
|
Apr 02 02:37:32 PM PDT 24 |
Apr 02 02:37:36 PM PDT 24 |
5565014362 ps |
T160 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.779962825 |
|
|
Apr 02 02:26:52 PM PDT 24 |
Apr 02 02:26:55 PM PDT 24 |
404357210 ps |
T161 |
/workspace/coverage/default/19.sram_ctrl_bijection.2900198324 |
|
|
Apr 02 02:31:50 PM PDT 24 |
Apr 02 02:55:06 PM PDT 24 |
65206949965 ps |
T162 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.406576848 |
|
|
Apr 02 02:26:55 PM PDT 24 |
Apr 02 02:27:15 PM PDT 24 |
714495264 ps |
T163 |
/workspace/coverage/default/8.sram_ctrl_bijection.1759017042 |
|
|
Apr 02 02:28:27 PM PDT 24 |
Apr 02 03:05:37 PM PDT 24 |
386716842749 ps |
T164 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2052532030 |
|
|
Apr 02 02:40:30 PM PDT 24 |
Apr 02 02:40:41 PM PDT 24 |
1327097520 ps |
T165 |
/workspace/coverage/default/49.sram_ctrl_bijection.1789777090 |
|
|
Apr 02 02:42:10 PM PDT 24 |
Apr 02 02:51:13 PM PDT 24 |
34205462754 ps |
T166 |
/workspace/coverage/default/26.sram_ctrl_regwen.4026762340 |
|
|
Apr 02 02:34:54 PM PDT 24 |
Apr 02 02:48:36 PM PDT 24 |
119696732044 ps |
T167 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2956129839 |
|
|
Apr 02 02:28:08 PM PDT 24 |
Apr 02 02:28:31 PM PDT 24 |
1525634571 ps |
T168 |
/workspace/coverage/default/15.sram_ctrl_partial_access.2691146741 |
|
|
Apr 02 02:30:29 PM PDT 24 |
Apr 02 02:33:01 PM PDT 24 |
5272949642 ps |
T169 |
/workspace/coverage/default/38.sram_ctrl_smoke.736461807 |
|
|
Apr 02 02:39:17 PM PDT 24 |
Apr 02 02:39:30 PM PDT 24 |
2118676940 ps |
T170 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.1572101331 |
|
|
Apr 02 02:27:19 PM PDT 24 |
Apr 02 02:31:49 PM PDT 24 |
13754961181 ps |
T51 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.4051998775 |
|
|
Apr 02 02:35:20 PM PDT 24 |
Apr 02 02:35:47 PM PDT 24 |
4429033565 ps |
T171 |
/workspace/coverage/default/8.sram_ctrl_stress_all.749137239 |
|
|
Apr 02 02:28:33 PM PDT 24 |
Apr 02 04:40:01 PM PDT 24 |
481636539474 ps |
T172 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3027279528 |
|
|
Apr 02 02:33:23 PM PDT 24 |
Apr 02 02:38:28 PM PDT 24 |
26601777817 ps |
T173 |
/workspace/coverage/default/36.sram_ctrl_executable.3518816471 |
|
|
Apr 02 02:38:39 PM PDT 24 |
Apr 02 02:50:30 PM PDT 24 |
12586600603 ps |
T174 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.442930289 |
|
|
Apr 02 02:33:24 PM PDT 24 |
Apr 02 02:53:58 PM PDT 24 |
113771899771 ps |
T175 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3568750642 |
|
|
Apr 02 02:37:07 PM PDT 24 |
Apr 02 02:39:23 PM PDT 24 |
18160100338 ps |
T176 |
/workspace/coverage/default/29.sram_ctrl_smoke.1244884109 |
|
|
Apr 02 02:35:52 PM PDT 24 |
Apr 02 02:36:01 PM PDT 24 |
2199895655 ps |
T105 |
/workspace/coverage/default/17.sram_ctrl_stress_all.3308897517 |
|
|
Apr 02 02:31:15 PM PDT 24 |
Apr 02 04:16:54 PM PDT 24 |
606587978094 ps |
T177 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1403616073 |
|
|
Apr 02 02:33:07 PM PDT 24 |
Apr 02 02:34:14 PM PDT 24 |
15029623119 ps |
T178 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3469323948 |
|
|
Apr 02 02:41:31 PM PDT 24 |
Apr 02 02:41:34 PM PDT 24 |
696603212 ps |
T179 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3251978936 |
|
|
Apr 02 02:35:30 PM PDT 24 |
Apr 02 02:39:40 PM PDT 24 |
17223746241 ps |
T180 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.3885994664 |
|
|
Apr 02 02:27:47 PM PDT 24 |
Apr 02 02:27:59 PM PDT 24 |
711741678 ps |
T181 |
/workspace/coverage/default/1.sram_ctrl_executable.2559416416 |
|
|
Apr 02 02:27:00 PM PDT 24 |
Apr 02 02:42:08 PM PDT 24 |
113449943355 ps |
T182 |
/workspace/coverage/default/38.sram_ctrl_bijection.2957934753 |
|
|
Apr 02 02:39:16 PM PDT 24 |
Apr 02 03:03:49 PM PDT 24 |
124992914341 ps |
T183 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2060548437 |
|
|
Apr 02 02:40:16 PM PDT 24 |
Apr 02 02:42:17 PM PDT 24 |
4432029625 ps |
T184 |
/workspace/coverage/default/33.sram_ctrl_bijection.2810040305 |
|
|
Apr 02 02:37:19 PM PDT 24 |
Apr 02 02:58:26 PM PDT 24 |
659882952559 ps |
T185 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.619675508 |
|
|
Apr 02 02:38:37 PM PDT 24 |
Apr 02 02:39:08 PM PDT 24 |
3485631282 ps |
T186 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.3933142397 |
|
|
Apr 02 02:29:55 PM PDT 24 |
Apr 02 02:31:29 PM PDT 24 |
1596964941 ps |
T187 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3930898691 |
|
|
Apr 02 02:29:37 PM PDT 24 |
Apr 02 02:31:40 PM PDT 24 |
3161307511 ps |
T52 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2495079326 |
|
|
Apr 02 02:29:41 PM PDT 24 |
Apr 02 02:29:54 PM PDT 24 |
2116885073 ps |
T188 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1895583062 |
|
|
Apr 02 02:30:26 PM PDT 24 |
Apr 02 02:36:44 PM PDT 24 |
70614010513 ps |
T189 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.631312885 |
|
|
Apr 02 02:40:23 PM PDT 24 |
Apr 02 02:40:27 PM PDT 24 |
349332860 ps |
T190 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.2818391296 |
|
|
Apr 02 02:30:22 PM PDT 24 |
Apr 02 02:36:09 PM PDT 24 |
6889138185 ps |
T191 |
/workspace/coverage/default/6.sram_ctrl_executable.1076627275 |
|
|
Apr 02 02:27:57 PM PDT 24 |
Apr 02 02:49:36 PM PDT 24 |
58575086903 ps |
T192 |
/workspace/coverage/default/4.sram_ctrl_smoke.2861187017 |
|
|
Apr 02 02:27:30 PM PDT 24 |
Apr 02 02:28:48 PM PDT 24 |
1197958588 ps |
T193 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.888386645 |
|
|
Apr 02 02:40:54 PM PDT 24 |
Apr 02 02:47:23 PM PDT 24 |
59034841648 ps |
T194 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.2189505714 |
|
|
Apr 02 02:28:25 PM PDT 24 |
Apr 02 02:28:44 PM PDT 24 |
710987266 ps |
T195 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.3140647922 |
|
|
Apr 02 02:30:52 PM PDT 24 |
Apr 02 02:30:57 PM PDT 24 |
4207836475 ps |
T196 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.2900393979 |
|
|
Apr 02 02:38:16 PM PDT 24 |
Apr 02 02:59:43 PM PDT 24 |
15902497360 ps |
T197 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.4040971263 |
|
|
Apr 02 02:40:23 PM PDT 24 |
Apr 02 02:42:59 PM PDT 24 |
10315640744 ps |
T198 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.2119925508 |
|
|
Apr 02 02:31:27 PM PDT 24 |
Apr 02 02:35:50 PM PDT 24 |
25628531690 ps |
T199 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.3115670426 |
|
|
Apr 02 02:32:28 PM PDT 24 |
Apr 02 02:36:23 PM PDT 24 |
8210277769 ps |
T200 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3547636950 |
|
|
Apr 02 02:31:11 PM PDT 24 |
Apr 02 02:32:31 PM PDT 24 |
14407861340 ps |
T201 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.3646167836 |
|
|
Apr 02 02:35:17 PM PDT 24 |
Apr 02 02:37:45 PM PDT 24 |
13782834323 ps |
T202 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3073253501 |
|
|
Apr 02 02:40:17 PM PDT 24 |
Apr 02 02:41:43 PM PDT 24 |
5045844386 ps |
T53 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.31675675 |
|
|
Apr 02 02:27:04 PM PDT 24 |
Apr 02 02:27:13 PM PDT 24 |
286543083 ps |
T203 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.2708911194 |
|
|
Apr 02 02:27:21 PM PDT 24 |
Apr 02 02:54:03 PM PDT 24 |
116118074474 ps |
T204 |
/workspace/coverage/default/38.sram_ctrl_alert_test.787890999 |
|
|
Apr 02 02:39:32 PM PDT 24 |
Apr 02 02:39:33 PM PDT 24 |
27308923 ps |
T205 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.662576700 |
|
|
Apr 02 02:37:18 PM PDT 24 |
Apr 02 02:44:07 PM PDT 24 |
96133266928 ps |
T206 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3454437102 |
|
|
Apr 02 02:40:38 PM PDT 24 |
Apr 02 02:43:40 PM PDT 24 |
50713125752 ps |
T207 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.449040956 |
|
|
Apr 02 02:31:32 PM PDT 24 |
Apr 02 02:38:20 PM PDT 24 |
13213114411 ps |
T208 |
/workspace/coverage/default/18.sram_ctrl_executable.2024409108 |
|
|
Apr 02 02:31:31 PM PDT 24 |
Apr 02 02:39:14 PM PDT 24 |
9987959246 ps |
T209 |
/workspace/coverage/default/20.sram_ctrl_partial_access.2320237130 |
|
|
Apr 02 02:32:26 PM PDT 24 |
Apr 02 02:32:37 PM PDT 24 |
1904836210 ps |
T210 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1196710125 |
|
|
Apr 02 02:27:33 PM PDT 24 |
Apr 02 02:41:48 PM PDT 24 |
16825548785 ps |
T211 |
/workspace/coverage/default/31.sram_ctrl_stress_all.3871536267 |
|
|
Apr 02 02:36:44 PM PDT 24 |
Apr 02 03:11:07 PM PDT 24 |
46653104226 ps |
T212 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3456752023 |
|
|
Apr 02 02:40:11 PM PDT 24 |
Apr 02 02:40:14 PM PDT 24 |
710733322 ps |
T213 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1214586959 |
|
|
Apr 02 02:30:01 PM PDT 24 |
Apr 02 04:32:39 PM PDT 24 |
273840082263 ps |
T214 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3767892871 |
|
|
Apr 02 02:37:25 PM PDT 24 |
Apr 02 02:41:37 PM PDT 24 |
6614299178 ps |
T215 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.4177375192 |
|
|
Apr 02 02:34:44 PM PDT 24 |
Apr 02 02:35:25 PM PDT 24 |
2597215446 ps |
T54 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2049530884 |
|
|
Apr 02 02:28:00 PM PDT 24 |
Apr 02 02:28:07 PM PDT 24 |
195208740 ps |
T216 |
/workspace/coverage/default/42.sram_ctrl_smoke.755714030 |
|
|
Apr 02 02:40:07 PM PDT 24 |
Apr 02 02:40:17 PM PDT 24 |
2733978037 ps |
T217 |
/workspace/coverage/default/42.sram_ctrl_bijection.4223475589 |
|
|
Apr 02 02:40:05 PM PDT 24 |
Apr 02 02:53:47 PM PDT 24 |
15009064691 ps |
T218 |
/workspace/coverage/default/38.sram_ctrl_regwen.1537375808 |
|
|
Apr 02 02:39:27 PM PDT 24 |
Apr 02 02:50:40 PM PDT 24 |
46422638819 ps |
T219 |
/workspace/coverage/default/35.sram_ctrl_executable.981168246 |
|
|
Apr 02 02:38:18 PM PDT 24 |
Apr 02 02:53:55 PM PDT 24 |
11494996244 ps |
T220 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3003114366 |
|
|
Apr 02 02:28:31 PM PDT 24 |
Apr 02 02:29:33 PM PDT 24 |
6803285871 ps |
T221 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3555050507 |
|
|
Apr 02 02:31:32 PM PDT 24 |
Apr 02 02:32:50 PM PDT 24 |
8506331818 ps |
T222 |
/workspace/coverage/default/5.sram_ctrl_smoke.1433292318 |
|
|
Apr 02 02:27:42 PM PDT 24 |
Apr 02 02:28:36 PM PDT 24 |
4873624912 ps |
T223 |
/workspace/coverage/default/0.sram_ctrl_alert_test.2231376865 |
|
|
Apr 02 02:26:50 PM PDT 24 |
Apr 02 02:26:51 PM PDT 24 |
24658762 ps |
T224 |
/workspace/coverage/default/29.sram_ctrl_regwen.2356259062 |
|
|
Apr 02 02:36:01 PM PDT 24 |
Apr 02 02:50:34 PM PDT 24 |
15703303859 ps |
T225 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2730643814 |
|
|
Apr 02 02:30:25 PM PDT 24 |
Apr 02 02:34:48 PM PDT 24 |
13357731610 ps |
T226 |
/workspace/coverage/default/24.sram_ctrl_executable.821991058 |
|
|
Apr 02 02:33:49 PM PDT 24 |
Apr 02 02:40:02 PM PDT 24 |
28587807054 ps |
T227 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.162022630 |
|
|
Apr 02 02:34:44 PM PDT 24 |
Apr 02 02:42:58 PM PDT 24 |
21984605171 ps |
T228 |
/workspace/coverage/default/16.sram_ctrl_executable.870040693 |
|
|
Apr 02 02:30:49 PM PDT 24 |
Apr 02 02:57:40 PM PDT 24 |
99703600800 ps |
T229 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.789275524 |
|
|
Apr 02 02:40:17 PM PDT 24 |
Apr 02 03:00:31 PM PDT 24 |
69677365515 ps |
T230 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.1138367031 |
|
|
Apr 02 02:36:35 PM PDT 24 |
Apr 02 02:36:50 PM PDT 24 |
2047017895 ps |
T231 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1645701533 |
|
|
Apr 02 02:28:06 PM PDT 24 |
Apr 02 02:31:34 PM PDT 24 |
15708035670 ps |
T232 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3776601633 |
|
|
Apr 02 02:27:14 PM PDT 24 |
Apr 02 02:28:34 PM PDT 24 |
10911197344 ps |
T233 |
/workspace/coverage/default/39.sram_ctrl_stress_all.1744170979 |
|
|
Apr 02 02:39:42 PM PDT 24 |
Apr 02 04:17:22 PM PDT 24 |
1235052035482 ps |
T234 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1600218900 |
|
|
Apr 02 02:40:55 PM PDT 24 |
Apr 02 02:43:03 PM PDT 24 |
3134230002 ps |
T235 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.3625729087 |
|
|
Apr 02 02:41:21 PM PDT 24 |
Apr 02 02:44:08 PM PDT 24 |
68897685537 ps |
T236 |
/workspace/coverage/default/29.sram_ctrl_partial_access.2231109360 |
|
|
Apr 02 02:35:56 PM PDT 24 |
Apr 02 02:36:04 PM PDT 24 |
2885832145 ps |
T237 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.2652611708 |
|
|
Apr 02 02:39:33 PM PDT 24 |
Apr 02 02:42:01 PM PDT 24 |
226322066638 ps |
T238 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2134281680 |
|
|
Apr 02 02:40:16 PM PDT 24 |
Apr 02 02:46:52 PM PDT 24 |
11098126429 ps |
T239 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.361344916 |
|
|
Apr 02 02:31:50 PM PDT 24 |
Apr 02 02:36:58 PM PDT 24 |
16716255446 ps |
T240 |
/workspace/coverage/default/49.sram_ctrl_regwen.3001925875 |
|
|
Apr 02 02:41:27 PM PDT 24 |
Apr 02 02:55:27 PM PDT 24 |
37248110322 ps |
T241 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.3201292145 |
|
|
Apr 02 02:39:59 PM PDT 24 |
Apr 02 02:40:03 PM PDT 24 |
831584651 ps |
T242 |
/workspace/coverage/default/14.sram_ctrl_regwen.1793151041 |
|
|
Apr 02 02:30:07 PM PDT 24 |
Apr 02 02:42:26 PM PDT 24 |
29724254536 ps |
T243 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.3116261370 |
|
|
Apr 02 02:32:28 PM PDT 24 |
Apr 02 02:32:32 PM PDT 24 |
695001254 ps |
T244 |
/workspace/coverage/default/16.sram_ctrl_smoke.1594644119 |
|
|
Apr 02 02:30:38 PM PDT 24 |
Apr 02 02:30:57 PM PDT 24 |
3545160579 ps |
T245 |
/workspace/coverage/default/6.sram_ctrl_regwen.2336839422 |
|
|
Apr 02 02:27:57 PM PDT 24 |
Apr 02 02:43:15 PM PDT 24 |
13555423650 ps |
T246 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2395577851 |
|
|
Apr 02 02:27:48 PM PDT 24 |
Apr 02 02:29:21 PM PDT 24 |
51275065217 ps |
T247 |
/workspace/coverage/default/33.sram_ctrl_partial_access.3292494560 |
|
|
Apr 02 02:37:25 PM PDT 24 |
Apr 02 02:38:24 PM PDT 24 |
2380538449 ps |
T248 |
/workspace/coverage/default/11.sram_ctrl_executable.4220865322 |
|
|
Apr 02 02:29:21 PM PDT 24 |
Apr 02 02:37:48 PM PDT 24 |
8788877253 ps |
T249 |
/workspace/coverage/default/36.sram_ctrl_bijection.1899302243 |
|
|
Apr 02 02:38:27 PM PDT 24 |
Apr 02 03:16:28 PM PDT 24 |
138299663870 ps |
T250 |
/workspace/coverage/default/28.sram_ctrl_partial_access.1578589651 |
|
|
Apr 02 02:35:29 PM PDT 24 |
Apr 02 02:35:49 PM PDT 24 |
2863635201 ps |
T251 |
/workspace/coverage/default/0.sram_ctrl_bijection.18346258 |
|
|
Apr 02 02:26:39 PM PDT 24 |
Apr 02 02:46:06 PM PDT 24 |
17741901864 ps |
T252 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.345185488 |
|
|
Apr 02 02:36:33 PM PDT 24 |
Apr 02 02:47:38 PM PDT 24 |
10511847920 ps |
T253 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1667063442 |
|
|
Apr 02 02:27:13 PM PDT 24 |
Apr 02 02:30:56 PM PDT 24 |
3644455455 ps |
T26 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.4115682625 |
|
|
Apr 02 02:27:43 PM PDT 24 |
Apr 02 02:27:47 PM PDT 24 |
855137073 ps |
T254 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2861281120 |
|
|
Apr 02 02:27:50 PM PDT 24 |
Apr 02 02:28:51 PM PDT 24 |
3811087558 ps |
T255 |
/workspace/coverage/default/42.sram_ctrl_alert_test.1930658082 |
|
|
Apr 02 02:40:11 PM PDT 24 |
Apr 02 02:40:11 PM PDT 24 |
38235113 ps |
T256 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.438948295 |
|
|
Apr 02 02:40:34 PM PDT 24 |
Apr 02 02:57:14 PM PDT 24 |
16561869340 ps |
T257 |
/workspace/coverage/default/2.sram_ctrl_stress_all.1301812243 |
|
|
Apr 02 02:27:17 PM PDT 24 |
Apr 02 03:33:12 PM PDT 24 |
272283862557 ps |
T258 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.4238998608 |
|
|
Apr 02 02:35:10 PM PDT 24 |
Apr 02 02:35:20 PM PDT 24 |
2947991984 ps |
T259 |
/workspace/coverage/default/4.sram_ctrl_executable.643661668 |
|
|
Apr 02 02:27:40 PM PDT 24 |
Apr 02 02:35:33 PM PDT 24 |
11025780686 ps |
T260 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1783258479 |
|
|
Apr 02 02:29:02 PM PDT 24 |
Apr 02 02:29:30 PM PDT 24 |
3064296637 ps |
T261 |
/workspace/coverage/default/23.sram_ctrl_executable.2977306397 |
|
|
Apr 02 02:33:26 PM PDT 24 |
Apr 02 02:48:28 PM PDT 24 |
16786601952 ps |
T262 |
/workspace/coverage/default/4.sram_ctrl_alert_test.2280263677 |
|
|
Apr 02 02:27:43 PM PDT 24 |
Apr 02 02:27:45 PM PDT 24 |
39638046 ps |
T263 |
/workspace/coverage/default/3.sram_ctrl_alert_test.1677451480 |
|
|
Apr 02 02:27:34 PM PDT 24 |
Apr 02 02:27:35 PM PDT 24 |
31896908 ps |
T264 |
/workspace/coverage/default/25.sram_ctrl_regwen.3127191472 |
|
|
Apr 02 02:34:18 PM PDT 24 |
Apr 02 02:36:07 PM PDT 24 |
9834156852 ps |
T265 |
/workspace/coverage/default/24.sram_ctrl_bijection.3317129861 |
|
|
Apr 02 02:33:39 PM PDT 24 |
Apr 02 02:48:36 PM PDT 24 |
57714428310 ps |
T266 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2147519154 |
|
|
Apr 02 02:41:06 PM PDT 24 |
Apr 02 02:41:09 PM PDT 24 |
376202311 ps |
T267 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.539129172 |
|
|
Apr 02 02:31:10 PM PDT 24 |
Apr 02 02:41:09 PM PDT 24 |
22133410228 ps |
T268 |
/workspace/coverage/default/29.sram_ctrl_stress_all.3483931449 |
|
|
Apr 02 02:36:12 PM PDT 24 |
Apr 02 04:23:12 PM PDT 24 |
1173409583599 ps |
T269 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.764643472 |
|
|
Apr 02 02:33:19 PM PDT 24 |
Apr 02 02:37:46 PM PDT 24 |
9425514928 ps |
T270 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.51943807 |
|
|
Apr 02 02:40:48 PM PDT 24 |
Apr 02 02:42:43 PM PDT 24 |
2063725967 ps |
T271 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.2550173637 |
|
|
Apr 02 02:32:46 PM PDT 24 |
Apr 02 02:32:49 PM PDT 24 |
1351849688 ps |
T272 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.1523186125 |
|
|
Apr 02 02:35:54 PM PDT 24 |
Apr 02 02:36:45 PM PDT 24 |
14878242613 ps |
T273 |
/workspace/coverage/default/42.sram_ctrl_partial_access.889903958 |
|
|
Apr 02 02:40:10 PM PDT 24 |
Apr 02 02:40:32 PM PDT 24 |
1562113352 ps |
T274 |
/workspace/coverage/default/36.sram_ctrl_stress_all.1307315710 |
|
|
Apr 02 02:38:53 PM PDT 24 |
Apr 02 04:08:20 PM PDT 24 |
899377928335 ps |
T275 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.3716422450 |
|
|
Apr 02 02:34:41 PM PDT 24 |
Apr 02 03:02:14 PM PDT 24 |
36915944733 ps |
T276 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.1161109245 |
|
|
Apr 02 02:39:48 PM PDT 24 |
Apr 02 02:42:14 PM PDT 24 |
5178906153 ps |
T277 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.3803791421 |
|
|
Apr 02 02:38:39 PM PDT 24 |
Apr 02 02:39:51 PM PDT 24 |
24355945515 ps |
T278 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3704719560 |
|
|
Apr 02 02:27:02 PM PDT 24 |
Apr 02 02:27:05 PM PDT 24 |
1404296682 ps |
T279 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2006394937 |
|
|
Apr 02 02:32:54 PM PDT 24 |
Apr 02 02:35:20 PM PDT 24 |
62074801670 ps |
T280 |
/workspace/coverage/default/45.sram_ctrl_smoke.3551669396 |
|
|
Apr 02 02:40:35 PM PDT 24 |
Apr 02 02:40:48 PM PDT 24 |
1460067986 ps |
T281 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1233914132 |
|
|
Apr 02 02:30:16 PM PDT 24 |
Apr 02 02:33:16 PM PDT 24 |
79559119637 ps |
T282 |
/workspace/coverage/default/7.sram_ctrl_stress_all.3373898285 |
|
|
Apr 02 02:28:18 PM PDT 24 |
Apr 02 03:39:48 PM PDT 24 |
566698362002 ps |
T283 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.1382345571 |
|
|
Apr 02 02:36:01 PM PDT 24 |
Apr 02 02:36:04 PM PDT 24 |
1348812498 ps |
T284 |
/workspace/coverage/default/18.sram_ctrl_regwen.3271734053 |
|
|
Apr 02 02:31:40 PM PDT 24 |
Apr 02 02:43:10 PM PDT 24 |
24617868018 ps |
T285 |
/workspace/coverage/default/34.sram_ctrl_bijection.1387053924 |
|
|
Apr 02 02:37:49 PM PDT 24 |
Apr 02 03:14:17 PM PDT 24 |
386776930479 ps |
T286 |
/workspace/coverage/default/34.sram_ctrl_stress_all.2742289217 |
|
|
Apr 02 02:37:56 PM PDT 24 |
Apr 02 03:30:36 PM PDT 24 |
34450732866 ps |
T287 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2735265630 |
|
|
Apr 02 02:29:57 PM PDT 24 |
Apr 02 02:31:30 PM PDT 24 |
61914706046 ps |
T55 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2732067236 |
|
|
Apr 02 02:30:35 PM PDT 24 |
Apr 02 02:30:46 PM PDT 24 |
657605058 ps |
T288 |
/workspace/coverage/default/48.sram_ctrl_smoke.2511806396 |
|
|
Apr 02 02:41:15 PM PDT 24 |
Apr 02 02:41:21 PM PDT 24 |
4320059257 ps |
T289 |
/workspace/coverage/default/38.sram_ctrl_stress_all.114823296 |
|
|
Apr 02 02:39:31 PM PDT 24 |
Apr 02 02:57:24 PM PDT 24 |
73083788820 ps |
T290 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.3952475236 |
|
|
Apr 02 02:27:28 PM PDT 24 |
Apr 02 02:31:54 PM PDT 24 |
20302407333 ps |
T291 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.289356331 |
|
|
Apr 02 02:28:09 PM PDT 24 |
Apr 02 02:36:00 PM PDT 24 |
5675048701 ps |
T292 |
/workspace/coverage/default/5.sram_ctrl_bijection.3073756408 |
|
|
Apr 02 02:27:42 PM PDT 24 |
Apr 02 02:52:44 PM PDT 24 |
39060024223 ps |
T293 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3168851259 |
|
|
Apr 02 02:26:57 PM PDT 24 |
Apr 02 02:30:02 PM PDT 24 |
3699532286 ps |
T294 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3142358373 |
|
|
Apr 02 02:28:26 PM PDT 24 |
Apr 02 02:30:10 PM PDT 24 |
958805028 ps |
T295 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.389669159 |
|
|
Apr 02 02:37:53 PM PDT 24 |
Apr 02 02:40:09 PM PDT 24 |
6370466800 ps |
T296 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.1809594278 |
|
|
Apr 02 02:37:01 PM PDT 24 |
Apr 02 02:37:17 PM PDT 24 |
2787725747 ps |
T297 |
/workspace/coverage/default/7.sram_ctrl_smoke.2121176514 |
|
|
Apr 02 02:28:04 PM PDT 24 |
Apr 02 02:28:13 PM PDT 24 |
3117371642 ps |
T298 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1122319275 |
|
|
Apr 02 02:35:54 PM PDT 24 |
Apr 02 02:36:37 PM PDT 24 |
765962773 ps |