Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	154356445	1			T1	10000		T2	42343		T3	5657
triple_byte_access	2805148	1			T2	38547		T4	1172		T5	1564
halfword_access	4299526	1			T2	57353		T4	1715		T5	2240
byte_access	6006401	1			T2	76238		T4	2274		T5	3020
zero_access	1813474	1			T2	19264		T4	604		T5	759

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84489851

1

T1

4987

T2

116805

T3

2843

auto[1]

84791143

1

T1

5013

T2

116940

T3

2814

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	76887581	1			T1	4987		T2	21054		T3	2843
auto[0]	triple_byte_access	1340149	1			T2	19284		T4	581		T5	824
auto[0]	halfword_access	2102249	1			T2	28528		T4	849		T5	1118
auto[0]	byte_access	3077273	1			T2	38283		T4	1166		T5	1539
auto[0]	zero_access	1082599	1			T2	9656		T4	301		T5	383
auto[1]	word_access	77468864	1			T1	5013		T2	21289		T3	2814
auto[1]	triple_byte_access	1464999	1			T2	19263		T4	591		T5	740
auto[1]	halfword_access	2197277	1			T2	28825		T4	866		T5	1122
auto[1]	byte_access	2929128	1			T2	37955		T4	1108		T5	1481
auto[1]	zero_access	730875	1			T2	9608		T4	303		T5	376