Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	368976612	1			T1	254328		T2	164098		T4	282576
instr_valid_dis	330547109	1			T1	254328		T2	164098		T4	282576
instr_en	25665685	1			T18	70		T19	159008		T20	116884

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	20831024	1			T18	30630		T19	43410		T20	45398
sram_ifetch_valid_disable	317028647	1			T1	254328		T2	164098		T4	282576
sram_ifetch_enable	31116941	1			T18	54336		T19	124806		T20	110500

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	368976612	1			T1	254328		T2	164098		T4	282576
hw_debug_en_valid_off	328001072	1			T1	254328		T2	164098		T4	282576
hw_debug_en_on	26392396	1			T18	55300		T19	89264		T20	128680

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	317028647	1			T1	254328		T2	164098		T4	282576
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	302922638	1			T1	254328		T2	164098		T4	282576
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9761293	1			T19	30354		T20	98648		T100	15998
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	13049794	1			T19	43410		T20	20992		T100	10614
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	8920038	1			T19	12046		T20	992		T100	10614
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	3515258	1			T19	31364		T49	18284		T152	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5195822	1			T18	30630		T20	20650		T29	45772
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2070284	1			T18	30630		T20	20650		T49	24306
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2094682	1			T29	45772		T49	86420		T61	51786
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11004366	1			T18	20000		T19	76370		T20	55836
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4307250	1			T18	20000		T19	18564		T20	18442
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4969354	1			T19	22334		T20	37394		T29	59808

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9717168	1			T18	70		T19	97290		T20	18236
lc_exec_en	10192208	1			T18	4670		T19	12894		T20	52194
valid_exec_dis	317216962	1			T1	254328		T2	164098		T4	282576
invalid_exec_dis	51947965	1			T18	84966		T19	168216		T20	155898