Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.81 97.15 100.00 100.00 98.61 99.70 98.52


Total tests in report: 1037
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
79.10 79.10 96.44 96.44 73.65 73.65 90.16 90.16 71.43 71.43 86.80 86.80 95.54 95.54 39.70 39.70 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.3713294997
86.75 7.64 97.47 1.03 80.98 7.33 94.39 4.23 71.43 0.00 89.61 2.81 97.47 1.93 75.88 36.18 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.98755481
93.07 6.32 98.88 1.40 85.60 4.63 94.89 0.50 100.00 28.57 93.54 3.93 97.47 0.00 81.08 5.19 /workspace/coverage/default/1.sram_ctrl_stress_all.3131757878
94.96 1.90 98.97 0.09 89.20 3.60 95.81 0.92 100.00 0.00 96.07 2.53 97.47 0.00 87.20 6.12 /workspace/coverage/default/48.sram_ctrl_executable.1415185878
96.14 1.18 99.44 0.47 92.29 3.08 96.73 0.92 100.00 0.00 98.31 2.25 98.07 0.59 88.13 0.93 /workspace/coverage/default/3.sram_ctrl_sec_cm.76154710
96.92 0.78 99.44 0.00 92.93 0.64 96.73 0.00 100.00 0.00 98.31 0.00 98.07 0.00 92.95 4.82 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4162848956
97.42 0.50 99.44 0.00 93.83 0.90 99.08 2.34 100.00 0.00 98.60 0.28 98.07 0.00 92.95 0.00 /workspace/coverage/default/16.sram_ctrl_multiple_keys.923728519
97.87 0.45 99.44 0.00 93.83 0.00 99.08 0.00 100.00 0.00 98.60 0.00 98.22 0.15 95.92 2.97 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3306750236
98.06 0.19 99.72 0.28 94.09 0.26 99.08 0.00 100.00 0.00 98.88 0.28 98.37 0.15 96.29 0.37 /workspace/coverage/default/39.sram_ctrl_regwen.10149624
98.24 0.18 99.72 0.00 94.09 0.00 99.15 0.07 100.00 0.00 98.88 0.00 99.55 1.19 96.29 0.00 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.732131584
98.36 0.12 99.81 0.09 94.09 0.00 99.93 0.78 100.00 0.00 98.88 0.00 99.55 0.00 96.29 0.00 /workspace/coverage/default/5.sram_ctrl_ram_cfg.452188125
98.47 0.11 99.81 0.00 94.09 0.00 99.93 0.00 100.00 0.00 98.88 0.00 99.55 0.00 97.03 0.74 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.417560446
98.55 0.08 99.81 0.00 94.09 0.00 99.93 0.00 100.00 0.00 98.88 0.00 99.55 0.00 97.59 0.56 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1804354889
98.61 0.07 99.81 0.00 94.47 0.39 100.00 0.07 100.00 0.00 98.88 0.00 99.55 0.00 97.59 0.00 /workspace/coverage/default/12.sram_ctrl_alert_test.2217769961
98.67 0.05 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.88 0.00 99.55 0.00 97.96 0.37 /workspace/coverage/default/45.sram_ctrl_stress_all.1091709753
98.69 0.03 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.88 0.00 99.55 0.00 98.14 0.19 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3760077924
98.72 0.03 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.88 0.00 99.55 0.00 98.33 0.19 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2443135333
98.75 0.03 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.88 0.00 99.55 0.00 98.52 0.19 /workspace/coverage/default/25.sram_ctrl_executable.3179733073
98.77 0.02 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.88 0.00 99.70 0.15 98.52 0.00 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2503292770

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4248018085
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2755880216
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2331628715
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.65794266
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2865452846
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3986625272
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2661532618
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3608310900
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4005190756
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2271422881
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1951093997
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2349201424
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1486521980
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2008895819
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1720075328
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3709098654
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4006347840
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3325214123
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2051358112
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2414743445
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.524813051
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1306111428
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1627297548
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.798913514
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1883082346
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1734525536
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4275028519
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.842380631
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1934105925
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1398046689
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3950037748
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3573959819
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3812812097
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3584813446
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1455469758
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.599258261
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.47875419
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1645448676
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1282463156
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.939331541
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4102463331
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3322547046
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2543945734
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.38685427
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.324815255
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3116076504
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1852044428
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1169385812
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1717425803
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1171185357
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.376972409
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3315637605
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4142068198
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2648826132
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3984438899
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.530510749
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3835855762
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2139712796
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3633112018
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1253471437
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2890471554
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.789936687
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1839685981
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.43180794
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3629510087
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.994204896
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.712625973
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.53292217
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2531230563
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.295087403
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2798022580
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2521623816
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2545996861
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3538053226
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1623248974
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4094409705
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3462794138
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3032759048
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2519818536
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1620084737
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3490775877
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3985656160
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3372210870
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3032222670
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2926442563
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1907412579
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3472720231
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1913514121
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2783582893
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2036783559
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1189808765
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2937986657
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2994663447
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2111110118
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1393822485
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2540911503
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2565112914
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1480820707
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1862948544
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2106421530
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1003755692
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1792492312
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1178087047
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1189902209
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2802349442
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2153761881
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3367087801
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2205421152
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.325135247
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3313164951
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1336895928
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.180868676
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4106545314
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1907668376
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1070900573
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3393139146
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4012063623
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3595179004
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3302736665
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1708966089
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3326520762
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.922537842
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.7381964
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.842549642
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.673733868
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1654259590
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.998633992
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3181832626
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3570583883
/workspace/coverage/default/0.sram_ctrl_alert_test.450168197
/workspace/coverage/default/0.sram_ctrl_bijection.1657395493
/workspace/coverage/default/0.sram_ctrl_executable.1165185334
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1668717048
/workspace/coverage/default/0.sram_ctrl_max_throughput.42054328
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3919234498
/workspace/coverage/default/0.sram_ctrl_mem_walk.3407094827
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1552141324
/workspace/coverage/default/0.sram_ctrl_partial_access.358939630
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1672025566
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2546459778
/workspace/coverage/default/0.sram_ctrl_regwen.255045729
/workspace/coverage/default/0.sram_ctrl_sec_cm.685098373
/workspace/coverage/default/0.sram_ctrl_smoke.1743656219
/workspace/coverage/default/0.sram_ctrl_stress_all.2053128122
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2991451848
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3084529442
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2093753928
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2238609509
/workspace/coverage/default/1.sram_ctrl_alert_test.46671955
/workspace/coverage/default/1.sram_ctrl_bijection.2658810352
/workspace/coverage/default/1.sram_ctrl_executable.2769220167
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1733512240
/workspace/coverage/default/1.sram_ctrl_max_throughput.3191421522
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3572093989
/workspace/coverage/default/1.sram_ctrl_mem_walk.4088259764
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3171030364
/workspace/coverage/default/1.sram_ctrl_partial_access.757919584
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4280199592
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2536248986
/workspace/coverage/default/1.sram_ctrl_regwen.2480024764
/workspace/coverage/default/1.sram_ctrl_sec_cm.4110234408
/workspace/coverage/default/1.sram_ctrl_smoke.1850928924
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2705200644
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.429475084
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1514415411
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1919482906
/workspace/coverage/default/10.sram_ctrl_alert_test.1469539607
/workspace/coverage/default/10.sram_ctrl_bijection.1376762325
/workspace/coverage/default/10.sram_ctrl_executable.2911486885
/workspace/coverage/default/10.sram_ctrl_lc_escalation.215504966
/workspace/coverage/default/10.sram_ctrl_max_throughput.1326381698
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1777020778
/workspace/coverage/default/10.sram_ctrl_mem_walk.4122185110
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3872680814
/workspace/coverage/default/10.sram_ctrl_partial_access.3809978005
/workspace/coverage/default/10.sram_ctrl_ram_cfg.418826000
/workspace/coverage/default/10.sram_ctrl_regwen.2819169311
/workspace/coverage/default/10.sram_ctrl_smoke.397890357
/workspace/coverage/default/10.sram_ctrl_stress_all.1287454554
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1537322760
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.802666625
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.366338302
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1470673332
/workspace/coverage/default/11.sram_ctrl_alert_test.3254354072
/workspace/coverage/default/11.sram_ctrl_bijection.2330876666
/workspace/coverage/default/11.sram_ctrl_executable.3250030113
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3816539900
/workspace/coverage/default/11.sram_ctrl_max_throughput.942972769
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3753089611
/workspace/coverage/default/11.sram_ctrl_mem_walk.995702356
/workspace/coverage/default/11.sram_ctrl_multiple_keys.278155666
/workspace/coverage/default/11.sram_ctrl_partial_access.1809286991
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3253807681
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2211982125
/workspace/coverage/default/11.sram_ctrl_regwen.1494059773
/workspace/coverage/default/11.sram_ctrl_smoke.4172513808
/workspace/coverage/default/11.sram_ctrl_stress_all.554474842
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.522043671
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.652183890
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3952262657
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3617300445
/workspace/coverage/default/12.sram_ctrl_bijection.479667495
/workspace/coverage/default/12.sram_ctrl_executable.3868861612
/workspace/coverage/default/12.sram_ctrl_lc_escalation.687256561
/workspace/coverage/default/12.sram_ctrl_max_throughput.1783343166
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3450083626
/workspace/coverage/default/12.sram_ctrl_mem_walk.602014464
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/workspace/coverage/default/42.sram_ctrl_smoke.2432029983
/workspace/coverage/default/42.sram_ctrl_stress_all.3131080550
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4066431835
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2940390410
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2614895965
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2725869055
/workspace/coverage/default/43.sram_ctrl_alert_test.2908884178
/workspace/coverage/default/43.sram_ctrl_executable.2515824212
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2027954099
/workspace/coverage/default/43.sram_ctrl_max_throughput.223286814
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.905642887
/workspace/coverage/default/43.sram_ctrl_mem_walk.3998743329
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3729331783
/workspace/coverage/default/43.sram_ctrl_partial_access.865999214
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3428411346
/workspace/coverage/default/43.sram_ctrl_ram_cfg.911139254
/workspace/coverage/default/43.sram_ctrl_regwen.694419445
/workspace/coverage/default/43.sram_ctrl_smoke.3923759788
/workspace/coverage/default/43.sram_ctrl_stress_all.2440664164
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.678521742
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3488337656
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.536327928
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2362280643
/workspace/coverage/default/44.sram_ctrl_alert_test.2475601710
/workspace/coverage/default/44.sram_ctrl_bijection.456102512
/workspace/coverage/default/44.sram_ctrl_executable.2443553278
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1089501578
/workspace/coverage/default/44.sram_ctrl_max_throughput.4203535248
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.156616381
/workspace/coverage/default/44.sram_ctrl_mem_walk.1436537422
/workspace/coverage/default/44.sram_ctrl_multiple_keys.120591807
/workspace/coverage/default/44.sram_ctrl_partial_access.501129822
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1237571467
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3674284354
/workspace/coverage/default/44.sram_ctrl_regwen.223937338
/workspace/coverage/default/44.sram_ctrl_smoke.567786561
/workspace/coverage/default/44.sram_ctrl_stress_all.1769518515
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.895613352
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1047753630
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1962095398
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3337482801
/workspace/coverage/default/45.sram_ctrl_alert_test.3198016453
/workspace/coverage/default/45.sram_ctrl_bijection.1090154432
/workspace/coverage/default/45.sram_ctrl_executable.2113235930
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3555667311
/workspace/coverage/default/45.sram_ctrl_max_throughput.1758071455
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.12814901
/workspace/coverage/default/45.sram_ctrl_mem_walk.4090184205
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3585988935
/workspace/coverage/default/45.sram_ctrl_partial_access.1796785104
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.274286474
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3747098966
/workspace/coverage/default/45.sram_ctrl_regwen.2324979702
/workspace/coverage/default/45.sram_ctrl_smoke.942834600
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2145839523
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3297801654
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.590822104
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2060310549
/workspace/coverage/default/46.sram_ctrl_alert_test.3174880189
/workspace/coverage/default/46.sram_ctrl_bijection.1143460997
/workspace/coverage/default/46.sram_ctrl_executable.2019885645
/workspace/coverage/default/46.sram_ctrl_lc_escalation.694298160
/workspace/coverage/default/46.sram_ctrl_max_throughput.1498502080
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1538882747
/workspace/coverage/default/46.sram_ctrl_mem_walk.2567974043
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3070676231
/workspace/coverage/default/46.sram_ctrl_partial_access.2301664848
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2963691619
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2913163217
/workspace/coverage/default/46.sram_ctrl_regwen.685696537
/workspace/coverage/default/46.sram_ctrl_smoke.3930546871
/workspace/coverage/default/46.sram_ctrl_stress_all.726251567
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.153247155
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.83960541
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2500491090
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2460887358
/workspace/coverage/default/47.sram_ctrl_alert_test.2875485682
/workspace/coverage/default/47.sram_ctrl_bijection.1018652407
/workspace/coverage/default/47.sram_ctrl_executable.805096222
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2490681636
/workspace/coverage/default/47.sram_ctrl_max_throughput.3238020662
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2128224592
/workspace/coverage/default/47.sram_ctrl_mem_walk.3193529206
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2363190832
/workspace/coverage/default/47.sram_ctrl_partial_access.3404974971
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3200486755
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1191309062
/workspace/coverage/default/47.sram_ctrl_regwen.128741197
/workspace/coverage/default/47.sram_ctrl_smoke.4277546768
/workspace/coverage/default/47.sram_ctrl_stress_all.3241859000
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1932277995
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2941624402
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.871284505
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1893998575
/workspace/coverage/default/48.sram_ctrl_alert_test.18793753
/workspace/coverage/default/48.sram_ctrl_bijection.4127670021
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1271678171
/workspace/coverage/default/48.sram_ctrl_max_throughput.1884397763
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2386832348
/workspace/coverage/default/48.sram_ctrl_mem_walk.1612536438
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2115855898
/workspace/coverage/default/48.sram_ctrl_partial_access.1923362202
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1192627987
/workspace/coverage/default/48.sram_ctrl_ram_cfg.359121543
/workspace/coverage/default/48.sram_ctrl_regwen.2722594111
/workspace/coverage/default/48.sram_ctrl_smoke.1776297558
/workspace/coverage/default/48.sram_ctrl_stress_all.1750087373
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1234151747
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.123488301
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2124926997
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1801892296
/workspace/coverage/default/49.sram_ctrl_alert_test.2034860494
/workspace/coverage/default/49.sram_ctrl_bijection.712041131
/workspace/coverage/default/49.sram_ctrl_executable.3127140483
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1644336407
/workspace/coverage/default/49.sram_ctrl_max_throughput.3317914944
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2078898793
/workspace/coverage/default/49.sram_ctrl_mem_walk.4118824902
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2037296166
/workspace/coverage/default/49.sram_ctrl_partial_access.3397493681
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.411432138
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1208088085
/workspace/coverage/default/49.sram_ctrl_regwen.3908521336
/workspace/coverage/default/49.sram_ctrl_smoke.1217038399
/workspace/coverage/default/49.sram_ctrl_stress_all.1851686309
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1278447546
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2769003028
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.726286664
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.906918897
/workspace/coverage/default/5.sram_ctrl_alert_test.2220492696
/workspace/coverage/default/5.sram_ctrl_bijection.2833655261
/workspace/coverage/default/5.sram_ctrl_executable.1280107719
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3434862583
/workspace/coverage/default/5.sram_ctrl_max_throughput.4052193058
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.608152326
/workspace/coverage/default/5.sram_ctrl_mem_walk.1499174714
/workspace/coverage/default/5.sram_ctrl_multiple_keys.4272325886
/workspace/coverage/default/5.sram_ctrl_partial_access.2558979687
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2628167040
/workspace/coverage/default/5.sram_ctrl_regwen.401141560
/workspace/coverage/default/5.sram_ctrl_smoke.2877090342
/workspace/coverage/default/5.sram_ctrl_stress_all.1667998228
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2034797670
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.95889118
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.820712556
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3316176299
/workspace/coverage/default/6.sram_ctrl_alert_test.1637591149
/workspace/coverage/default/6.sram_ctrl_executable.3048742721
/workspace/coverage/default/6.sram_ctrl_lc_escalation.96874068
/workspace/coverage/default/6.sram_ctrl_max_throughput.3649681037
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3778181825
/workspace/coverage/default/6.sram_ctrl_mem_walk.1731964678
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2679565772
/workspace/coverage/default/6.sram_ctrl_partial_access.2466782524
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3424461271
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2429523710
/workspace/coverage/default/6.sram_ctrl_regwen.83570257
/workspace/coverage/default/6.sram_ctrl_smoke.267855066
/workspace/coverage/default/6.sram_ctrl_stress_all.3476995039
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3723282808
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1374346592
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.921162183
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1502952983
/workspace/coverage/default/7.sram_ctrl_alert_test.2896399902
/workspace/coverage/default/7.sram_ctrl_bijection.3038965095
/workspace/coverage/default/7.sram_ctrl_executable.3048089570
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3847717058
/workspace/coverage/default/7.sram_ctrl_max_throughput.403824266
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.180192594
/workspace/coverage/default/7.sram_ctrl_mem_walk.1889660393
/workspace/coverage/default/7.sram_ctrl_multiple_keys.4136023061
/workspace/coverage/default/7.sram_ctrl_partial_access.7847210
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.418864056
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3768514080
/workspace/coverage/default/7.sram_ctrl_regwen.1795674427
/workspace/coverage/default/7.sram_ctrl_smoke.2216249097
/workspace/coverage/default/7.sram_ctrl_stress_all.599024035
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.730736197
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2789281460
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.492893260
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1177902305
/workspace/coverage/default/8.sram_ctrl_alert_test.3053551467
/workspace/coverage/default/8.sram_ctrl_bijection.2648673915
/workspace/coverage/default/8.sram_ctrl_executable.3820482121
/workspace/coverage/default/8.sram_ctrl_lc_escalation.410333465
/workspace/coverage/default/8.sram_ctrl_max_throughput.1427649805
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.657163639
/workspace/coverage/default/8.sram_ctrl_mem_walk.1721423185
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1912648064
/workspace/coverage/default/8.sram_ctrl_partial_access.2896667581
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.607523100
/workspace/coverage/default/8.sram_ctrl_ram_cfg.36179017
/workspace/coverage/default/8.sram_ctrl_regwen.4027673813
/workspace/coverage/default/8.sram_ctrl_smoke.989550025
/workspace/coverage/default/8.sram_ctrl_stress_all.1779578740
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.409578216
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.347143901
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.4050154357
/workspace/coverage/default/9.sram_ctrl_alert_test.2698557537
/workspace/coverage/default/9.sram_ctrl_bijection.1523913124
/workspace/coverage/default/9.sram_ctrl_executable.2068560588
/workspace/coverage/default/9.sram_ctrl_lc_escalation.531574678
/workspace/coverage/default/9.sram_ctrl_max_throughput.3928179630
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2348595311
/workspace/coverage/default/9.sram_ctrl_mem_walk.594887884
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2999253631
/workspace/coverage/default/9.sram_ctrl_partial_access.2378729977
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.980220718
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2997644630
/workspace/coverage/default/9.sram_ctrl_regwen.2491488351
/workspace/coverage/default/9.sram_ctrl_smoke.2476487495
/workspace/coverage/default/9.sram_ctrl_stress_all.4250689874
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.578164400
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.790309181
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3475555386



Total test records in report: 1037
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/40.sram_ctrl_multiple_keys.1025251373 Apr 04 01:57:44 PM PDT 24 Apr 04 02:07:48 PM PDT 24 28518742422 ps
T2 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.3713294997 Apr 04 01:47:19 PM PDT 24 Apr 04 01:55:36 PM PDT 24 28321412900 ps
T3 /workspace/coverage/default/7.sram_ctrl_alert_test.2896399902 Apr 04 01:36:44 PM PDT 24 Apr 04 01:36:45 PM PDT 24 25783942 ps
T4 /workspace/coverage/default/28.sram_ctrl_multiple_keys.2916879922 Apr 04 01:50:00 PM PDT 24 Apr 04 02:01:08 PM PDT 24 87360874221 ps
T5 /workspace/coverage/default/40.sram_ctrl_mem_walk.3647543604 Apr 04 01:57:52 PM PDT 24 Apr 04 02:00:24 PM PDT 24 13960370292 ps
T9 /workspace/coverage/default/47.sram_ctrl_alert_test.2875485682 Apr 04 02:00:20 PM PDT 24 Apr 04 02:00:21 PM PDT 24 18931007 ps
T10 /workspace/coverage/default/5.sram_ctrl_ram_cfg.452188125 Apr 04 01:36:14 PM PDT 24 Apr 04 01:36:18 PM PDT 24 354612477 ps
T11 /workspace/coverage/default/16.sram_ctrl_alert_test.3925785813 Apr 04 01:41:24 PM PDT 24 Apr 04 01:41:25 PM PDT 24 29157817 ps
T12 /workspace/coverage/default/43.sram_ctrl_max_throughput.223286814 Apr 04 01:58:44 PM PDT 24 Apr 04 01:59:56 PM PDT 24 754728606 ps
T13 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.938594995 Apr 04 01:53:02 PM PDT 24 Apr 04 01:54:21 PM PDT 24 1666907760 ps
T6 /workspace/coverage/default/7.sram_ctrl_lc_escalation.3847717058 Apr 04 01:36:34 PM PDT 24 Apr 04 01:37:36 PM PDT 24 10203422323 ps
T14 /workspace/coverage/default/27.sram_ctrl_multiple_keys.3372808042 Apr 04 01:48:45 PM PDT 24 Apr 04 02:04:31 PM PDT 24 19647101328 ps
T17 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2614895965 Apr 04 01:58:24 PM PDT 24 Apr 04 01:58:32 PM PDT 24 704330309 ps
T18 /workspace/coverage/default/38.sram_ctrl_regwen.2296675648 Apr 04 01:56:50 PM PDT 24 Apr 04 02:00:17 PM PDT 24 4943963721 ps
T19 /workspace/coverage/default/26.sram_ctrl_executable.1214755624 Apr 04 01:48:19 PM PDT 24 Apr 04 01:58:22 PM PDT 24 34899286132 ps
T20 /workspace/coverage/default/2.sram_ctrl_executable.283689445 Apr 04 01:35:26 PM PDT 24 Apr 04 01:49:35 PM PDT 24 7167628525 ps
T21 /workspace/coverage/default/22.sram_ctrl_smoke.2854406556 Apr 04 01:44:52 PM PDT 24 Apr 04 01:44:59 PM PDT 24 713203519 ps
T65 /workspace/coverage/default/12.sram_ctrl_smoke.4050754736 Apr 04 01:38:24 PM PDT 24 Apr 04 01:38:31 PM PDT 24 726836081 ps
T48 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1185272196 Apr 04 01:54:24 PM PDT 24 Apr 04 01:59:18 PM PDT 24 11371433081 ps
T66 /workspace/coverage/default/21.sram_ctrl_mem_walk.128997220 Apr 04 01:44:34 PM PDT 24 Apr 04 01:49:32 PM PDT 24 55119564144 ps
T100 /workspace/coverage/default/41.sram_ctrl_executable.2730292419 Apr 04 01:58:06 PM PDT 24 Apr 04 02:02:44 PM PDT 24 43303856514 ps
T28 /workspace/coverage/default/12.sram_ctrl_bijection.479667495 Apr 04 01:38:36 PM PDT 24 Apr 04 02:08:05 PM PDT 24 132762563329 ps
T15 /workspace/coverage/default/16.sram_ctrl_multiple_keys.923728519 Apr 04 01:40:55 PM PDT 24 Apr 04 01:57:44 PM PDT 24 43694995250 ps
T16 /workspace/coverage/default/49.sram_ctrl_partial_access.3397493681 Apr 04 02:00:43 PM PDT 24 Apr 04 02:01:20 PM PDT 24 1106707358 ps
T101 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2829995778 Apr 04 01:54:46 PM PDT 24 Apr 04 01:56:00 PM PDT 24 782440818 ps
T102 /workspace/coverage/default/29.sram_ctrl_smoke.585711836 Apr 04 01:50:47 PM PDT 24 Apr 04 01:52:35 PM PDT 24 1596800497 ps
T103 /workspace/coverage/default/49.sram_ctrl_mem_walk.4118824902 Apr 04 02:00:43 PM PDT 24 Apr 04 02:05:33 PM PDT 24 18652445499 ps
T32 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.98755481 Apr 04 01:36:59 PM PDT 24 Apr 04 01:37:16 PM PDT 24 540347750 ps
T22 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1274144769 Apr 04 01:58:06 PM PDT 24 Apr 04 02:07:49 PM PDT 24 13223989317 ps
T33 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1278447546 Apr 04 02:00:58 PM PDT 24 Apr 04 02:02:27 PM PDT 24 1575412546 ps
T57 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1121836389 Apr 04 01:39:12 PM PDT 24 Apr 04 01:39:30 PM PDT 24 1470788134 ps
T58 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.204143137 Apr 04 01:39:50 PM PDT 24 Apr 04 01:40:25 PM PDT 24 3106051696 ps
T7 /workspace/coverage/default/0.sram_ctrl_lc_escalation.1668717048 Apr 04 01:35:09 PM PDT 24 Apr 04 01:36:00 PM PDT 24 31640971522 ps
T34 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3432971803 Apr 04 01:45:34 PM PDT 24 Apr 04 01:46:40 PM PDT 24 4820828214 ps
T8 /workspace/coverage/default/17.sram_ctrl_lc_escalation.3653471024 Apr 04 01:41:41 PM PDT 24 Apr 04 01:42:56 PM PDT 24 23463457537 ps
T59 /workspace/coverage/default/42.sram_ctrl_partial_access.3578778154 Apr 04 01:58:23 PM PDT 24 Apr 04 01:58:39 PM PDT 24 1238486150 ps
T60 /workspace/coverage/default/42.sram_ctrl_bijection.653616643 Apr 04 01:58:22 PM PDT 24 Apr 04 02:27:34 PM PDT 24 431563033966 ps
T137 /workspace/coverage/default/9.sram_ctrl_executable.2068560588 Apr 04 01:37:25 PM PDT 24 Apr 04 01:44:11 PM PDT 24 20135218529 ps
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T29 /workspace/coverage/default/39.sram_ctrl_regwen.10149624 Apr 04 01:57:18 PM PDT 24 Apr 04 02:14:22 PM PDT 24 4083915767 ps
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T23 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2362280643 Apr 04 01:59:09 PM PDT 24 Apr 04 02:22:54 PM PDT 24 19142239403 ps
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T50 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.98274570 Apr 04 01:43:41 PM PDT 24 Apr 04 01:45:10 PM PDT 24 6774003317 ps
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T163 /workspace/coverage/default/24.sram_ctrl_bijection.1787169531 Apr 04 01:46:05 PM PDT 24 Apr 04 01:56:00 PM PDT 24 68051751667 ps
T51 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3744697515 Apr 04 01:48:29 PM PDT 24 Apr 04 01:51:44 PM PDT 24 2601012315 ps
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T30 /workspace/coverage/default/3.sram_ctrl_regwen.534189013 Apr 04 01:35:36 PM PDT 24 Apr 04 01:51:19 PM PDT 24 17574219297 ps
T63 /workspace/coverage/default/7.sram_ctrl_regwen.1795674427 Apr 04 01:36:34 PM PDT 24 Apr 04 01:40:08 PM PDT 24 7897278875 ps
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T88 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.1350897003 Apr 04 01:54:55 PM PDT 24 Apr 04 02:07:15 PM PDT 24 26729324597 ps
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T36 /workspace/coverage/default/38.sram_ctrl_ram_cfg.3045576709 Apr 04 01:56:52 PM PDT 24 Apr 04 01:56:55 PM PDT 24 1318641771 ps
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T111 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2889686582 Apr 04 01:57:02 PM PDT 24 Apr 04 02:02:01 PM PDT 24 186303479244 ps
T169 /workspace/coverage/default/19.sram_ctrl_lc_escalation.688639461 Apr 04 01:42:45 PM PDT 24 Apr 04 01:44:29 PM PDT 24 48101220743 ps
T140 /workspace/coverage/default/49.sram_ctrl_executable.3127140483 Apr 04 02:00:46 PM PDT 24 Apr 04 02:19:45 PM PDT 24 60898173815 ps
T53 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4066431835 Apr 04 01:58:35 PM PDT 24 Apr 04 01:58:56 PM PDT 24 477702548 ps
T170 /workspace/coverage/default/37.sram_ctrl_regwen.2295459828 Apr 04 01:56:41 PM PDT 24 Apr 04 02:06:45 PM PDT 24 13915186367 ps
T139 /workspace/coverage/default/44.sram_ctrl_regwen.223937338 Apr 04 01:59:08 PM PDT 24 Apr 04 02:11:15 PM PDT 24 7590911154 ps
T171 /workspace/coverage/default/46.sram_ctrl_mem_walk.2567974043 Apr 04 01:59:50 PM PDT 24 Apr 04 02:03:47 PM PDT 24 3983942752 ps
T172 /workspace/coverage/default/24.sram_ctrl_smoke.241587636 Apr 04 01:46:03 PM PDT 24 Apr 04 01:46:13 PM PDT 24 3630211630 ps
T90 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3094848394 Apr 04 01:44:31 PM PDT 24 Apr 04 01:46:34 PM PDT 24 8235467542 ps
T173 /workspace/coverage/default/4.sram_ctrl_partial_access.2118102243 Apr 04 01:35:44 PM PDT 24 Apr 04 01:35:59 PM PDT 24 1361241871 ps
T174 /workspace/coverage/default/8.sram_ctrl_ram_cfg.36179017 Apr 04 01:36:44 PM PDT 24 Apr 04 01:36:48 PM PDT 24 707103037 ps
T175 /workspace/coverage/default/30.sram_ctrl_multiple_keys.3436609847 Apr 04 01:51:18 PM PDT 24 Apr 04 02:01:09 PM PDT 24 28891323459 ps
T176 /workspace/coverage/default/49.sram_ctrl_lc_escalation.1644336407 Apr 04 02:00:43 PM PDT 24 Apr 04 02:01:39 PM PDT 24 41053667250 ps
T177 /workspace/coverage/default/29.sram_ctrl_ram_cfg.212028707 Apr 04 01:51:08 PM PDT 24 Apr 04 01:51:12 PM PDT 24 2090994516 ps
T178 /workspace/coverage/default/25.sram_ctrl_partial_access.3704728137 Apr 04 01:47:00 PM PDT 24 Apr 04 01:47:09 PM PDT 24 2556775499 ps
T54 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.522043671 Apr 04 01:38:23 PM PDT 24 Apr 04 01:38:31 PM PDT 24 158057337 ps
T179 /workspace/coverage/default/43.sram_ctrl_partial_access.865999214 Apr 04 01:58:44 PM PDT 24 Apr 04 01:58:55 PM PDT 24 731642759 ps
T142 /workspace/coverage/default/1.sram_ctrl_stress_all.3131757878 Apr 04 01:35:26 PM PDT 24 Apr 04 03:09:33 PM PDT 24 105699747434 ps
T180 /workspace/coverage/default/40.sram_ctrl_ram_cfg.2452043401 Apr 04 01:57:46 PM PDT 24 Apr 04 01:57:49 PM PDT 24 355664059 ps
T181 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.762148365 Apr 04 01:48:07 PM PDT 24 Apr 04 01:49:19 PM PDT 24 1475918531 ps
T55 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3389505637 Apr 04 01:54:38 PM PDT 24 Apr 04 01:55:54 PM PDT 24 6516636287 ps
T91 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.157923361 Apr 04 01:49:24 PM PDT 24 Apr 04 01:51:17 PM PDT 24 1571770477 ps
T112 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3306750236 Apr 04 01:37:36 PM PDT 24 Apr 04 01:45:26 PM PDT 24 40302547362 ps
T138 /workspace/coverage/default/47.sram_ctrl_executable.805096222 Apr 04 01:59:59 PM PDT 24 Apr 04 02:22:45 PM PDT 24 18138089904 ps
T182 /workspace/coverage/default/3.sram_ctrl_max_throughput.2597224514 Apr 04 01:35:38 PM PDT 24 Apr 04 01:36:20 PM PDT 24 3494590175 ps
T92 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1598666151 Apr 04 01:48:20 PM PDT 24 Apr 04 01:50:18 PM PDT 24 8222588556 ps
T183 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.963772171 Apr 04 01:56:51 PM PDT 24 Apr 04 01:58:49 PM PDT 24 6464477688 ps
T184 /workspace/coverage/default/4.sram_ctrl_multiple_keys.2580513943 Apr 04 01:35:44 PM PDT 24 Apr 04 01:52:18 PM PDT 24 18350325948 ps
T185 /workspace/coverage/default/36.sram_ctrl_partial_access.2111519974 Apr 04 01:55:25 PM PDT 24 Apr 04 01:55:29 PM PDT 24 378102410 ps
T186 /workspace/coverage/default/30.sram_ctrl_lc_escalation.2446672550 Apr 04 01:51:47 PM PDT 24 Apr 04 01:52:21 PM PDT 24 11586988092 ps
T56 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1676172724 Apr 04 01:50:35 PM PDT 24 Apr 04 01:51:13 PM PDT 24 5355227982 ps
T187 /workspace/coverage/default/12.sram_ctrl_ram_cfg.395569312 Apr 04 01:38:42 PM PDT 24 Apr 04 01:38:46 PM PDT 24 357504518 ps
T188 /workspace/coverage/default/23.sram_ctrl_multiple_keys.2162616729 Apr 04 01:45:33 PM PDT 24 Apr 04 01:51:13 PM PDT 24 12216285411 ps
T189 /workspace/coverage/default/48.sram_ctrl_smoke.1776297558 Apr 04 02:00:22 PM PDT 24 Apr 04 02:00:44 PM PDT 24 1415910733 ps
T190 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1704658336 Apr 04 01:52:41 PM PDT 24 Apr 04 01:53:13 PM PDT 24 13296181923 ps
T191 /workspace/coverage/default/20.sram_ctrl_regwen.3641798725 Apr 04 01:43:28 PM PDT 24 Apr 04 01:57:57 PM PDT 24 24755633706 ps
T192 /workspace/coverage/default/6.sram_ctrl_partial_access.2466782524 Apr 04 01:36:14 PM PDT 24 Apr 04 01:36:37 PM PDT 24 452476042 ps
T193 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3948672427 Apr 04 01:56:41 PM PDT 24 Apr 04 01:57:36 PM PDT 24 6235355707 ps
T194 /workspace/coverage/default/14.sram_ctrl_bijection.4014341220 Apr 04 01:39:30 PM PDT 24 Apr 04 02:19:21 PM PDT 24 216582476409 ps
T195 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.820712556 Apr 04 01:35:54 PM PDT 24 Apr 04 01:36:01 PM PDT 24 2663222525 ps
T196 /workspace/coverage/default/19.sram_ctrl_max_throughput.2080294825 Apr 04 01:42:43 PM PDT 24 Apr 04 01:43:09 PM PDT 24 1463900516 ps
T197 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.872471929 Apr 04 01:53:11 PM PDT 24 Apr 04 01:54:10 PM PDT 24 1005659044 ps
T198 /workspace/coverage/default/45.sram_ctrl_ram_cfg.3747098966 Apr 04 01:59:28 PM PDT 24 Apr 04 01:59:32 PM PDT 24 1400413058 ps
T199 /workspace/coverage/default/22.sram_ctrl_multiple_keys.2353787460 Apr 04 01:44:52 PM PDT 24 Apr 04 01:52:29 PM PDT 24 14618340611 ps
T200 /workspace/coverage/default/7.sram_ctrl_partial_access.7847210 Apr 04 01:36:24 PM PDT 24 Apr 04 01:36:38 PM PDT 24 458903695 ps
T201 /workspace/coverage/default/29.sram_ctrl_bijection.1687107605 Apr 04 01:50:47 PM PDT 24 Apr 04 02:09:08 PM PDT 24 99655503826 ps
T202 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1514140352 Apr 04 01:35:32 PM PDT 24 Apr 04 01:41:51 PM PDT 24 57477360430 ps
T203 /workspace/coverage/default/37.sram_ctrl_ram_cfg.280268113 Apr 04 01:56:40 PM PDT 24 Apr 04 01:56:43 PM PDT 24 676167287 ps
T144 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.291893279 Apr 04 01:39:21 PM PDT 24 Apr 04 01:41:48 PM PDT 24 54106926980 ps
T204 /workspace/coverage/default/25.sram_ctrl_max_throughput.3423156607 Apr 04 01:47:10 PM PDT 24 Apr 04 01:48:35 PM PDT 24 12496756604 ps
T205 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.442535132 Apr 04 01:45:32 PM PDT 24 Apr 04 01:48:26 PM PDT 24 11013819104 ps
T206 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.686707252 Apr 04 01:42:15 PM PDT 24 Apr 04 02:01:40 PM PDT 24 19099497163 ps
T207 /workspace/coverage/default/12.sram_ctrl_alert_test.2217769961 Apr 04 01:38:52 PM PDT 24 Apr 04 01:38:53 PM PDT 24 47191591 ps
T208 /workspace/coverage/default/2.sram_ctrl_regwen.2540879276 Apr 04 01:35:36 PM PDT 24 Apr 04 01:44:13 PM PDT 24 10356901681 ps
T209 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2598237563 Apr 04 01:43:41 PM PDT 24 Apr 04 01:45:57 PM PDT 24 4541714274 ps
T124 /workspace/coverage/default/14.sram_ctrl_stress_all.1062610018 Apr 04 01:40:13 PM PDT 24 Apr 04 02:10:02 PM PDT 24 102954528022 ps
T210 /workspace/coverage/default/43.sram_ctrl_executable.2515824212 Apr 04 01:58:48 PM PDT 24 Apr 04 02:15:46 PM PDT 24 13513359535 ps
T145 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3778181825 Apr 04 01:36:15 PM PDT 24 Apr 04 01:38:38 PM PDT 24 19078100127 ps
T211 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2714461251 Apr 04 01:47:57 PM PDT 24 Apr 04 01:53:17 PM PDT 24 21871112581 ps
T143 /workspace/coverage/default/16.sram_ctrl_regwen.980606161 Apr 04 01:41:03 PM PDT 24 Apr 04 01:52:24 PM PDT 24 8652487682 ps
T212 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1200834492 Apr 04 01:39:51 PM PDT 24 Apr 04 01:45:37 PM PDT 24 15393139601 ps
T213 /workspace/coverage/default/16.sram_ctrl_max_throughput.2621349299 Apr 04 01:41:03 PM PDT 24 Apr 04 01:41:10 PM PDT 24 1286478893 ps
T214 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2429171868 Apr 04 01:57:59 PM PDT 24 Apr 04 01:58:44 PM PDT 24 736663084 ps
T215 /workspace/coverage/default/19.sram_ctrl_alert_test.621245340 Apr 04 01:43:04 PM PDT 24 Apr 04 01:43:05 PM PDT 24 15153963 ps
T151 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3572093989 Apr 04 01:35:20 PM PDT 24 Apr 04 01:37:48 PM PDT 24 82790431381 ps
T216 /workspace/coverage/default/26.sram_ctrl_bijection.3958962816 Apr 04 01:47:44 PM PDT 24 Apr 04 02:08:34 PM PDT 24 19475532534 ps
T217 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1392919749 Apr 04 01:40:15 PM PDT 24 Apr 04 01:43:57 PM PDT 24 13010361451 ps
T218 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.336170881 Apr 04 01:35:35 PM PDT 24 Apr 04 01:35:49 PM PDT 24 550303384 ps
T219 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.700336249 Apr 04 01:53:45 PM PDT 24 Apr 04 01:54:58 PM PDT 24 2409817659 ps
T220 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1418549597 Apr 04 01:45:46 PM PDT 24 Apr 04 01:47:24 PM PDT 24 3263030742 ps
T221 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.578164400 Apr 04 01:37:23 PM PDT 24 Apr 04 01:37:42 PM PDT 24 591884578 ps
T222 /workspace/coverage/default/15.sram_ctrl_bijection.3047512517 Apr 04 01:40:19 PM PDT 24 Apr 04 02:02:36 PM PDT 24 345480809595 ps
T223 /workspace/coverage/default/38.sram_ctrl_smoke.2184292974 Apr 04 01:56:41 PM PDT 24 Apr 04 01:56:59 PM PDT 24 887934384 ps
T224 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.505926290 Apr 04 01:56:41 PM PDT 24 Apr 04 02:02:16 PM PDT 24 11073413708 ps
T225 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2128224592 Apr 04 02:00:09 PM PDT 24 Apr 04 02:01:25 PM PDT 24 9335697546 ps
T226 /workspace/coverage/default/32.sram_ctrl_smoke.743213022 Apr 04 01:52:50 PM PDT 24 Apr 04 01:53:06 PM PDT 24 852328568 ps
T227 /workspace/coverage/default/3.sram_ctrl_partial_access.3827245635 Apr 04 01:35:41 PM PDT 24 Apr 04 01:35:55 PM PDT 24 1967939413 ps
T228 /workspace/coverage/default/34.sram_ctrl_stress_all.3728204119 Apr 04 01:54:37 PM PDT 24 Apr 04 02:54:19 PM PDT 24 53434785042 ps
T229 /workspace/coverage/default/3.sram_ctrl_ram_cfg.1366104290 Apr 04 01:35:45 PM PDT 24 Apr 04 01:35:48 PM PDT 24 734699353 ps
T25 /workspace/coverage/default/3.sram_ctrl_sec_cm.76154710 Apr 04 01:35:44 PM PDT 24 Apr 04 01:35:47 PM PDT 24 1096563606 ps
T39 /workspace/coverage/default/13.sram_ctrl_max_throughput.725863579 Apr 04 01:39:13 PM PDT 24 Apr 04 01:41:01 PM PDT 24 2818966956 ps
T40 /workspace/coverage/default/21.sram_ctrl_regwen.3354447447 Apr 04 01:44:31 PM PDT 24 Apr 04 01:54:59 PM PDT 24 7403152944 ps
T41 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1138928464 Apr 04 01:35:51 PM PDT 24 Apr 04 01:37:02 PM PDT 24 917081641 ps
T42 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2348595311 Apr 04 01:37:24 PM PDT 24 Apr 04 01:39:41 PM PDT 24 4975186111 ps
T43 /workspace/coverage/default/39.sram_ctrl_partial_access.2995852747 Apr 04 01:56:58 PM PDT 24 Apr 04 01:57:13 PM PDT 24 15730761556 ps
T44 /workspace/coverage/default/7.sram_ctrl_mem_walk.1889660393 Apr 04 01:36:36 PM PDT 24 Apr 04 01:41:08 PM PDT 24 18126097356 ps
T45 /workspace/coverage/default/20.sram_ctrl_max_throughput.1633172684 Apr 04 01:43:23 PM PDT 24 Apr 04 01:43:31 PM PDT 24 1135848115 ps
T46 /workspace/coverage/default/2.sram_ctrl_lc_escalation.2425609343 Apr 04 01:35:27 PM PDT 24 Apr 04 01:36:21 PM PDT 24 37696966949 ps
T47 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3650855528 Apr 04 01:42:34 PM PDT 24 Apr 04 01:45:44 PM PDT 24 2987052085 ps
T230 /workspace/coverage/default/39.sram_ctrl_max_throughput.1579755802 Apr 04 01:57:10 PM PDT 24 Apr 04 01:58:03 PM PDT 24 2120548383 ps
T231 /workspace/coverage/default/18.sram_ctrl_max_throughput.3529813452 Apr 04 01:42:00 PM PDT 24 Apr 04 01:42:27 PM PDT 24 2993656628 ps
T232 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3249429867 Apr 04 01:55:05 PM PDT 24 Apr 04 01:57:28 PM PDT 24 4518827530 ps
T233 /workspace/coverage/default/9.sram_ctrl_multiple_keys.2999253631 Apr 04 01:37:13 PM PDT 24 Apr 04 01:56:06 PM PDT 24 20010423522 ps
T234 /workspace/coverage/default/32.sram_ctrl_ram_cfg.2149523041 Apr 04 01:53:10 PM PDT 24 Apr 04 01:53:13 PM PDT 24 355187813 ps
T235 /workspace/coverage/default/38.sram_ctrl_mem_walk.995598359 Apr 04 01:56:54 PM PDT 24 Apr 04 02:01:20 PM PDT 24 28099275361 ps
T236 /workspace/coverage/default/31.sram_ctrl_smoke.3007875070 Apr 04 01:51:58 PM PDT 24 Apr 04 01:52:47 PM PDT 24 777280438 ps
T237 /workspace/coverage/default/28.sram_ctrl_stress_all.789849499 Apr 04 01:50:47 PM PDT 24 Apr 04 03:56:03 PM PDT 24 1245031362352 ps
T238 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.2271539610 Apr 04 01:50:58 PM PDT 24 Apr 04 01:52:59 PM PDT 24 4869381399 ps
T239 /workspace/coverage/default/0.sram_ctrl_max_throughput.42054328 Apr 04 01:35:08 PM PDT 24 Apr 04 01:36:48 PM PDT 24 2827038843 ps
T240 /workspace/coverage/default/6.sram_ctrl_mem_walk.1731964678 Apr 04 01:36:15 PM PDT 24 Apr 04 01:38:28 PM PDT 24 7186788325 ps
T241 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1123157012 Apr 04 01:45:51 PM PDT 24 Apr 04 01:47:49 PM PDT 24 38755228171 ps
T242 /workspace/coverage/default/27.sram_ctrl_max_throughput.3184746998 Apr 04 01:49:03 PM PDT 24 Apr 04 01:49:11 PM PDT 24 2693952267 ps
T243 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.180192594 Apr 04 01:36:34 PM PDT 24 Apr 04 01:38:47 PM PDT 24 18281044191 ps
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T294 /workspace/coverage/default/24.sram_ctrl_stress_all.2406393513 Apr 04 01:46:37 PM PDT 24 Apr 04 02:48:10 PM PDT 24 153289888160 ps
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T298 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.726286664 Apr 04 02:00:43 PM PDT 24 Apr 04 02:01:51 PM PDT 24 1514165651 ps
T118 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2991451848 Apr 04 01:35:18 PM PDT 24 Apr 04 01:35:29 PM PDT 24 316393755 ps
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T300 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1777020778 Apr 04 01:37:52 PM PDT 24 Apr 04 01:40:11 PM PDT 24 15652730765 ps
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T303 /workspace/coverage/default/0.sram_ctrl_partial_access.358939630 Apr 04 01:35:08 PM PDT 24 Apr 04 01:35:12 PM PDT 24 364578631 ps
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