Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	153761100	1			T1	115472		T2	74597		T4	128421
triple_byte_access	2895789	1			T1	2394		T2	1518		T4	2555
halfword_access	4439199	1			T1	3488		T2	2268		T4	3863
byte_access	6210846	1			T1	4664		T2	2915		T4	5129
zero_access	1882490	1			T1	1146		T2	751		T4	1320

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84458543

1

T1

63816

T2

40984

T4

70583

auto[1]

84730881

1

T1

63348

T2

41065

T4

70705

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	76598078	1			T1	57927		T2	37251		T4	64184
auto[0]	triple_byte_access	1380768	1			T1	1147		T2	792		T4	1252
auto[0]	halfword_access	2170774	1			T1	1796		T2	1125		T4	1961
auto[0]	byte_access	3182504	1			T1	2382		T2	1449		T4	2526
auto[0]	zero_access	1126419	1			T1	564		T2	367		T4	660
auto[1]	word_access	77163022	1			T1	57545		T2	37346		T4	64237
auto[1]	triple_byte_access	1515021	1			T1	1247		T2	726		T4	1303
auto[1]	halfword_access	2268425	1			T1	1692		T2	1143		T4	1902
auto[1]	byte_access	3028342	1			T1	2282		T2	1466		T4	2603
auto[1]	zero_access	756071	1			T1	582		T2	384		T4	660