Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	348399464	1			T1	14128		T2	196606		T3	125482
instr_valid_dis	305684995	1			T1	14128		T2	196606		T3	125482
instr_en	32430974	1			T9	109804		T10	47648		T11	315716

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12377301	1			T9	135692		T10	83010		T11	62450
sram_ifetch_valid_disable	311288945	1			T1	14128		T2	196606		T3	125482
sram_ifetch_enable	24733218	1			T4	1764		T9	104512		T10	147872

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	348399464	1			T1	14128		T2	196606		T3	125482
hw_debug_en_valid_off	307397743	1			T1	14128		T2	196606		T3	125482
hw_debug_en_on	28134321	1			T9	125868		T10	83362		T11	95116

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	311288945	1			T1	14128		T2	196606		T3	125482
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	292257635	1			T1	14128		T2	196606		T3	125482
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	14392469	1			T9	20000		T10	12364		T11	72528
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4473218	1			T9	43204		T8	68790		T43	47644
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1693604	1			T8	68790		T53	58902		T54	10732
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1752688	1			T9	43204		T43	47644		T53	25782
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4565581	1			T9	61840		T10	70954		T11	24310
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2077086	1			T10	70954		T44	11492		T135	104614
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1904453	1			T11	24310		T134	17534		T8	16484
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	12527148	1			T9	43072		T10	12364		T11	36534
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3346276	1			T134	31352		T133	33602		T8	28582
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	7979672	1			T10	12364		T11	36534		T133	32920

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12247796	1			T9	46600		T10	35284		T11	180738
lc_exec_en	11041592	1			T9	20956		T10	44		T11	34272
valid_exec_dis	302660613	1			T1	14128		T2	196606		T3	125482
invalid_exec_dis	37110519	1			T4	1764		T9	240204		T10	230882