Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.81	97.15	100.00	100.00	98.61	99.70	98.52

Total tests in report: 1036

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
87.36	87.36	97.75	97.75	83.93	83.93	95.56	95.56	71.43	71.43	91.29	91.29	95.10	95.10	76.44	76.44	/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2751685738
94.60	7.24	99.06	1.31	90.62	6.68	95.92	0.36	100.00	28.57	96.91	5.62	95.25	0.15	84.42	7.98	/workspace/coverage/default/23.sram_ctrl_stress_all.2397167957
95.64	1.05	99.25	0.19	91.52	0.90	96.13	0.21	100.00	0.00	97.75	0.84	95.25	0.00	89.61	5.19	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1712357758
96.48	0.84	99.53	0.28	92.03	0.51	98.44	2.31	100.00	0.00	98.03	0.28	97.18	1.93	90.17	0.56	/workspace/coverage/default/40.sram_ctrl_access_during_key_req.3588383382
97.22	0.74	99.72	0.19	93.96	1.93	99.15	0.71	100.00	0.00	98.88	0.84	97.77	0.59	91.09	0.93	/workspace/coverage/default/1.sram_ctrl_sec_cm.3340983698
97.53	0.31	99.72	0.00	94.09	0.13	99.15	0.00	100.00	0.00	98.88	0.00	97.77	0.00	93.14	2.04	/workspace/coverage/default/43.sram_ctrl_stress_all.2462835756
97.83	0.29	99.72	0.00	94.09	0.00	99.15	0.00	100.00	0.00	98.88	0.00	97.77	0.00	95.18	2.04	/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1287092637
98.03	0.20	99.72	0.00	94.09	0.00	99.22	0.07	100.00	0.00	98.88	0.00	99.11	1.34	95.18	0.00	/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1151276082
98.21	0.18	99.72	0.00	94.09	0.00	99.22	0.00	100.00	0.00	98.88	0.00	99.26	0.15	96.29	1.11	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.549242256
98.32	0.11	99.81	0.09	94.09	0.00	99.93	0.71	100.00	0.00	98.88	0.00	99.26	0.00	96.29	0.00	/workspace/coverage/default/12.sram_ctrl_ram_cfg.3171171188
98.43	0.11	99.81	0.00	94.09	0.00	99.93	0.00	100.00	0.00	98.88	0.00	99.26	0.00	97.03	0.74	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3051775164
98.53	0.11	99.81	0.00	94.09	0.00	99.93	0.00	100.00	0.00	98.88	0.00	99.26	0.00	97.77	0.74	/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1018422454
98.61	0.08	99.81	0.00	94.09	0.00	99.93	0.00	100.00	0.00	98.88	0.00	99.26	0.00	98.33	0.56	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3079936997
98.68	0.07	99.81	0.00	94.47	0.39	100.00	0.07	100.00	0.00	98.88	0.00	99.26	0.00	98.33	0.00	/workspace/coverage/default/22.sram_ctrl_alert_test.722139306
98.74	0.06	99.81	0.00	94.47	0.00	100.00	0.00	100.00	0.00	98.88	0.00	99.70	0.45	98.33	0.00	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2073843867
98.77	0.03	99.81	0.00	94.47	0.00	100.00	0.00	100.00	0.00	98.88	0.00	99.70	0.00	98.52	0.19	/workspace/coverage/default/17.sram_ctrl_executable.1449622881

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3484989481
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.506028523
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3312837640
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.410667430
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1965234042
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2842243502
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2980087653
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1970158559
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.435879141
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4040520709
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.908233843
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.678863850
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4168431063
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3758523326
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3914407853
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2458662603
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.155560249
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.54639215
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.882502379
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2107101933
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.700615858
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.787382596
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.886644662
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2950890414
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2336831794
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.734362262
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2469203568
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3643641881
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3448741564
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2798898577
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3361571629
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2009827130
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1864399666
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.175161072
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.306579347
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1859570694
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.391676737
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.278486117
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.778878106
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1474153424
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3819734521
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.409570162
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1072700172
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1432638779
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2993035606
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3369301979
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1662767921
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3407922487
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3227498265
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2680872156
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2141388643
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2612512938
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3793952513
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.633845852
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.558842831
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1994080613
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1384803724
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1143235793
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2110200462
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2315025015
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3310696722
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3562889037
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2324210894
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3883965624
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2362173656
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1723447898
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.12729563
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3874695079
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2674909510
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2659601372
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4264034521
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3352103873
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1109482777
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.118549942
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1247361838
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.505924266
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.755448634
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.246735083
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.914797823
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4181602247
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1021370525
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1404171445
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1594989249
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1698865456
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.657752965
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2169573739
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2248682533
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.679482688
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.897314684
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3482685415
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2523068411
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4006057632
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.701744058
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.237727724
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.515347446
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.253136635
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1511612168
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.209839774
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2376918614
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.396047818
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1128079489
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1293755337
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1106286197
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.72172335
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3242259059
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.355313665
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3482158868
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3130952356
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1448594290
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2967270163
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1074483840
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.550185474
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4096924736
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.124866475
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1965279631
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2719877202
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.791411573
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2173333900
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1598463869
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2055717474
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1399105937
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.735835575
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3098183035
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1223198762
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.805205247
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.78587893
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.655808395
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1142896245
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4114104447
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1864496674
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2945022039
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.276263842
/workspace/coverage/default/0.sram_ctrl_alert_test.2105468536
/workspace/coverage/default/0.sram_ctrl_bijection.631658389
/workspace/coverage/default/0.sram_ctrl_executable.1926617475
/workspace/coverage/default/0.sram_ctrl_lc_escalation.751016127
/workspace/coverage/default/0.sram_ctrl_max_throughput.4001215864
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3823690189
/workspace/coverage/default/0.sram_ctrl_mem_walk.2455471865
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2482999787
/workspace/coverage/default/0.sram_ctrl_partial_access.2139968928
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.34841583
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1906278583
/workspace/coverage/default/0.sram_ctrl_regwen.2998956675
/workspace/coverage/default/0.sram_ctrl_sec_cm.309505469
/workspace/coverage/default/0.sram_ctrl_smoke.1908583703
/workspace/coverage/default/0.sram_ctrl_stress_all.2939133883
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4122091793
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.4023114523
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1155402815
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.630591268
/workspace/coverage/default/1.sram_ctrl_alert_test.3047801445
/workspace/coverage/default/1.sram_ctrl_bijection.3172980261
/workspace/coverage/default/1.sram_ctrl_executable.238725053
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2362620392
/workspace/coverage/default/1.sram_ctrl_max_throughput.2810590604
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3731166982
/workspace/coverage/default/1.sram_ctrl_mem_walk.203733199
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3684226663
/workspace/coverage/default/1.sram_ctrl_partial_access.2254453287
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2990528097
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3383101460
/workspace/coverage/default/1.sram_ctrl_regwen.3272038016
/workspace/coverage/default/1.sram_ctrl_smoke.1138031107
/workspace/coverage/default/1.sram_ctrl_stress_all.2166870612
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2439498825
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.153367464
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1406356213
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3740677953
/workspace/coverage/default/10.sram_ctrl_alert_test.1699486199
/workspace/coverage/default/10.sram_ctrl_bijection.467775371
/workspace/coverage/default/10.sram_ctrl_executable.4028684600
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3814359703
/workspace/coverage/default/10.sram_ctrl_max_throughput.3687196668
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2417457061
/workspace/coverage/default/10.sram_ctrl_mem_walk.4156371256
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1531588661
/workspace/coverage/default/10.sram_ctrl_partial_access.372545058
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.156907359
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2739210949
/workspace/coverage/default/10.sram_ctrl_regwen.4283095222
/workspace/coverage/default/10.sram_ctrl_smoke.2070985959
/workspace/coverage/default/10.sram_ctrl_stress_all.3843196321
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1934145494
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3240732869
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3233215279
/workspace/coverage/default/11.sram_ctrl_alert_test.4086929753
/workspace/coverage/default/11.sram_ctrl_bijection.1509031956
/workspace/coverage/default/11.sram_ctrl_executable.1025037286
/workspace/coverage/default/11.sram_ctrl_lc_escalation.902486630
/workspace/coverage/default/11.sram_ctrl_max_throughput.1166440568
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.504723145
/workspace/coverage/default/11.sram_ctrl_mem_walk.2030234519
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1102241036
/workspace/coverage/default/11.sram_ctrl_partial_access.951140658
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.580492819
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2209819472
/workspace/coverage/default/11.sram_ctrl_regwen.746963404
/workspace/coverage/default/11.sram_ctrl_smoke.3078696895
/workspace/coverage/default/11.sram_ctrl_stress_all.686246042
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3993931562
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2849202098
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.934685229
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/workspace/coverage/default/42.sram_ctrl_ram_cfg.1344419235
/workspace/coverage/default/42.sram_ctrl_regwen.678924692
/workspace/coverage/default/42.sram_ctrl_smoke.1034299031
/workspace/coverage/default/42.sram_ctrl_stress_all.2073833652
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4272107969
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2285243426
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.215679035
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2031714616
/workspace/coverage/default/43.sram_ctrl_alert_test.3563588340
/workspace/coverage/default/43.sram_ctrl_bijection.517255228
/workspace/coverage/default/43.sram_ctrl_executable.436265845
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3812204454
/workspace/coverage/default/43.sram_ctrl_max_throughput.728111238
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1302682437
/workspace/coverage/default/43.sram_ctrl_mem_walk.1727726194
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2219892814
/workspace/coverage/default/43.sram_ctrl_partial_access.536863412
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2910684226
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1973254599
/workspace/coverage/default/43.sram_ctrl_regwen.1934277301
/workspace/coverage/default/43.sram_ctrl_smoke.2893307518
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.4168802836
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2250803915
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3737751281
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.627472815
/workspace/coverage/default/44.sram_ctrl_alert_test.3827796468
/workspace/coverage/default/44.sram_ctrl_bijection.483540557
/workspace/coverage/default/44.sram_ctrl_executable.923013799
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2125135052
/workspace/coverage/default/44.sram_ctrl_max_throughput.3722553851
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3210341955
/workspace/coverage/default/44.sram_ctrl_mem_walk.457310374
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2968552982
/workspace/coverage/default/44.sram_ctrl_partial_access.4214555847
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2942424354
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1083063490
/workspace/coverage/default/44.sram_ctrl_regwen.2960001878
/workspace/coverage/default/44.sram_ctrl_smoke.453501525
/workspace/coverage/default/44.sram_ctrl_stress_all.3174601356
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.626524406
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2537313203
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1811724680
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3019724424
/workspace/coverage/default/45.sram_ctrl_alert_test.2446481532
/workspace/coverage/default/45.sram_ctrl_bijection.3705005148
/workspace/coverage/default/45.sram_ctrl_executable.2167315608
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3999007359
/workspace/coverage/default/45.sram_ctrl_max_throughput.3725465853
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.503176523
/workspace/coverage/default/45.sram_ctrl_mem_walk.3801718197
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1034830153
/workspace/coverage/default/45.sram_ctrl_partial_access.2582751102
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.412699138
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3414778472
/workspace/coverage/default/45.sram_ctrl_regwen.2157290225
/workspace/coverage/default/45.sram_ctrl_smoke.2090559416
/workspace/coverage/default/45.sram_ctrl_stress_all.573494140
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1861535001
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.473498999
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.773059487
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.236103084
/workspace/coverage/default/46.sram_ctrl_alert_test.334763962
/workspace/coverage/default/46.sram_ctrl_bijection.1709875610
/workspace/coverage/default/46.sram_ctrl_executable.565428741
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3418151518
/workspace/coverage/default/46.sram_ctrl_max_throughput.81694445
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1888346287
/workspace/coverage/default/46.sram_ctrl_mem_walk.3667477407
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3452735630
/workspace/coverage/default/46.sram_ctrl_partial_access.2965016515
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1945453299
/workspace/coverage/default/46.sram_ctrl_ram_cfg.4010858276
/workspace/coverage/default/46.sram_ctrl_regwen.1289384694
/workspace/coverage/default/46.sram_ctrl_smoke.3996510365
/workspace/coverage/default/46.sram_ctrl_stress_all.397042376
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3351139968
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1290366218
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.393711344
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3670442424
/workspace/coverage/default/47.sram_ctrl_alert_test.603970618
/workspace/coverage/default/47.sram_ctrl_bijection.2562641123
/workspace/coverage/default/47.sram_ctrl_executable.2717479904
/workspace/coverage/default/47.sram_ctrl_lc_escalation.4058700361
/workspace/coverage/default/47.sram_ctrl_max_throughput.3299271838
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.4243626435
/workspace/coverage/default/47.sram_ctrl_mem_walk.3807297822
/workspace/coverage/default/47.sram_ctrl_multiple_keys.871047061
/workspace/coverage/default/47.sram_ctrl_partial_access.2002708682
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3994218196
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2960072753
/workspace/coverage/default/47.sram_ctrl_regwen.1064146262
/workspace/coverage/default/47.sram_ctrl_smoke.3312135827
/workspace/coverage/default/47.sram_ctrl_stress_all.3734084249
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.490615866
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2905772597
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.936561827
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.555853918
/workspace/coverage/default/48.sram_ctrl_alert_test.186358872
/workspace/coverage/default/48.sram_ctrl_bijection.1522750768
/workspace/coverage/default/48.sram_ctrl_executable.2334871259
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3237263139
/workspace/coverage/default/48.sram_ctrl_max_throughput.2152096434
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3730441436
/workspace/coverage/default/48.sram_ctrl_mem_walk.1951885668
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1927095432
/workspace/coverage/default/48.sram_ctrl_partial_access.2131732859
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.167875432
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1847723940
/workspace/coverage/default/48.sram_ctrl_regwen.3814950811
/workspace/coverage/default/48.sram_ctrl_smoke.646194077
/workspace/coverage/default/48.sram_ctrl_stress_all.2592807610
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1070331454
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1891642256
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3692923574
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2844379400
/workspace/coverage/default/49.sram_ctrl_alert_test.3307177373
/workspace/coverage/default/49.sram_ctrl_bijection.3652217040
/workspace/coverage/default/49.sram_ctrl_executable.1328149286
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3317659408
/workspace/coverage/default/49.sram_ctrl_max_throughput.3793530781
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1810938953
/workspace/coverage/default/49.sram_ctrl_mem_walk.2112669944
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1667045125
/workspace/coverage/default/49.sram_ctrl_partial_access.1434652446
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3348840111
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3466771383
/workspace/coverage/default/49.sram_ctrl_regwen.3946351141
/workspace/coverage/default/49.sram_ctrl_smoke.1162314991
/workspace/coverage/default/49.sram_ctrl_stress_all.2706372729
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3615726281
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2216961918
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3378738949
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2630649707
/workspace/coverage/default/5.sram_ctrl_alert_test.1106448105
/workspace/coverage/default/5.sram_ctrl_bijection.3457865823
/workspace/coverage/default/5.sram_ctrl_executable.225296642
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1684725005
/workspace/coverage/default/5.sram_ctrl_max_throughput.4286313692
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.433255822
/workspace/coverage/default/5.sram_ctrl_mem_walk.2218802571
/workspace/coverage/default/5.sram_ctrl_partial_access.1406280435
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2281785451
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2435919115
/workspace/coverage/default/5.sram_ctrl_regwen.2001682940
/workspace/coverage/default/5.sram_ctrl_smoke.3400299479
/workspace/coverage/default/5.sram_ctrl_stress_all.2916473946
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2606422165
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2181673344
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.409652287
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1003318208
/workspace/coverage/default/6.sram_ctrl_alert_test.3301013997
/workspace/coverage/default/6.sram_ctrl_bijection.1619344138
/workspace/coverage/default/6.sram_ctrl_executable.3582167903
/workspace/coverage/default/6.sram_ctrl_lc_escalation.880730715
/workspace/coverage/default/6.sram_ctrl_max_throughput.580082368
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.192507285
/workspace/coverage/default/6.sram_ctrl_mem_walk.2104402955
/workspace/coverage/default/6.sram_ctrl_multiple_keys.4180465781
/workspace/coverage/default/6.sram_ctrl_partial_access.464691818
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.105112370
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2275978714
/workspace/coverage/default/6.sram_ctrl_regwen.2314023464
/workspace/coverage/default/6.sram_ctrl_smoke.3061976661
/workspace/coverage/default/6.sram_ctrl_stress_all.2363821872
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2276602246
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3048117358
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2633066514
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1963567274
/workspace/coverage/default/7.sram_ctrl_alert_test.3713069105
/workspace/coverage/default/7.sram_ctrl_bijection.2226327250
/workspace/coverage/default/7.sram_ctrl_executable.2653646879
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2850864079
/workspace/coverage/default/7.sram_ctrl_max_throughput.3534212118
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.717917743
/workspace/coverage/default/7.sram_ctrl_mem_walk.4098787264
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2073368264
/workspace/coverage/default/7.sram_ctrl_partial_access.1310212902
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1233392341
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3270936661
/workspace/coverage/default/7.sram_ctrl_regwen.4091722343
/workspace/coverage/default/7.sram_ctrl_smoke.2101555163
/workspace/coverage/default/7.sram_ctrl_stress_all.833458561
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2385672597
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1571809084
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.417474040
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2099555593
/workspace/coverage/default/8.sram_ctrl_alert_test.2602011613
/workspace/coverage/default/8.sram_ctrl_bijection.3706770393
/workspace/coverage/default/8.sram_ctrl_executable.3314150208
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1578874149
/workspace/coverage/default/8.sram_ctrl_max_throughput.3231546052
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3731703105
/workspace/coverage/default/8.sram_ctrl_mem_walk.1397752682
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2148936668
/workspace/coverage/default/8.sram_ctrl_partial_access.1305959392
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1573403689
/workspace/coverage/default/8.sram_ctrl_ram_cfg.398077251
/workspace/coverage/default/8.sram_ctrl_regwen.3159954498
/workspace/coverage/default/8.sram_ctrl_smoke.721125607
/workspace/coverage/default/8.sram_ctrl_stress_all.1749025679
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1260647747
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3775217741
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2420205781
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3167961736
/workspace/coverage/default/9.sram_ctrl_alert_test.1341893720
/workspace/coverage/default/9.sram_ctrl_bijection.1357876525
/workspace/coverage/default/9.sram_ctrl_executable.2211431810
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1324822427
/workspace/coverage/default/9.sram_ctrl_max_throughput.2059851415
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1489696077
/workspace/coverage/default/9.sram_ctrl_mem_walk.3621530129
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1959155021
/workspace/coverage/default/9.sram_ctrl_partial_access.3878149390
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1715454227
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1765135941
/workspace/coverage/default/9.sram_ctrl_regwen.3288034613
/workspace/coverage/default/9.sram_ctrl_smoke.2970136231
/workspace/coverage/default/9.sram_ctrl_stress_all.3774960951
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3544329941
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3172157972
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.813900615

Total test records in report: 1036

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.490615866	Apr 15 12:45:44 PM PDT 24	Apr 15 12:46:05 PM PDT 24	2150726989 ps
T2	/workspace/coverage/default/2.sram_ctrl_mem_walk.4056780953	Apr 15 12:41:38 PM PDT 24	Apr 15 12:43:34 PM PDT 24	32867838899 ps
T3	/workspace/coverage/default/41.sram_ctrl_mem_partial_access.454999401	Apr 15 12:44:53 PM PDT 24	Apr 15 12:46:58 PM PDT 24	1563916835 ps
T4	/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2751685738	Apr 15 12:44:17 PM PDT 24	Apr 15 12:46:43 PM PDT 24	2592708794 ps
T5	/workspace/coverage/default/40.sram_ctrl_access_during_key_req.3588383382	Apr 15 12:44:36 PM PDT 24	Apr 15 01:03:44 PM PDT 24	48056314973 ps
T9	/workspace/coverage/default/2.sram_ctrl_stress_all.561621225	Apr 15 12:41:45 PM PDT 24	Apr 15 01:51:05 PM PDT 24	62762660474 ps
T10	/workspace/coverage/default/17.sram_ctrl_executable.1449622881	Apr 15 12:42:30 PM PDT 24	Apr 15 12:53:28 PM PDT 24	11261987622 ps
T6	/workspace/coverage/default/43.sram_ctrl_lc_escalation.3812204454	Apr 15 12:45:03 PM PDT 24	Apr 15 12:45:45 PM PDT 24	5868581449 ps
T11	/workspace/coverage/default/26.sram_ctrl_regwen.1183469672	Apr 15 12:42:56 PM PDT 24	Apr 15 12:56:12 PM PDT 24	2815831900 ps
T12	/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3898809191	Apr 15 12:44:46 PM PDT 24	Apr 15 12:44:53 PM PDT 24	2981926644 ps
T7	/workspace/coverage/default/9.sram_ctrl_lc_escalation.1324822427	Apr 15 12:42:10 PM PDT 24	Apr 15 12:42:33 PM PDT 24	11229856535 ps
T13	/workspace/coverage/default/20.sram_ctrl_smoke.2961397904	Apr 15 12:42:38 PM PDT 24	Apr 15 12:42:50 PM PDT 24	1560260148 ps
T21	/workspace/coverage/default/35.sram_ctrl_alert_test.4144841524	Apr 15 12:44:06 PM PDT 24	Apr 15 12:44:07 PM PDT 24	32794247 ps
T15	/workspace/coverage/default/16.sram_ctrl_multiple_keys.1087173262	Apr 15 12:42:31 PM PDT 24	Apr 15 01:05:23 PM PDT 24	19461144084 ps
T55	/workspace/coverage/default/18.sram_ctrl_max_throughput.4068780771	Apr 15 12:42:35 PM PDT 24	Apr 15 12:44:51 PM PDT 24	782053790 ps
T98	/workspace/coverage/default/22.sram_ctrl_bijection.1653271607	Apr 15 12:42:39 PM PDT 24	Apr 15 12:58:34 PM PDT 24	53784540957 ps
T134	/workspace/coverage/default/33.sram_ctrl_executable.2745841585	Apr 15 12:43:42 PM PDT 24	Apr 15 12:48:04 PM PDT 24	7756525167 ps
T142	/workspace/coverage/default/0.sram_ctrl_max_throughput.4001215864	Apr 15 12:41:10 PM PDT 24	Apr 15 12:41:49 PM PDT 24	14433125836 ps
T66	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.597302417	Apr 15 12:42:28 PM PDT 24	Apr 15 12:43:29 PM PDT 24	964664341 ps
T67	/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2022079887	Apr 15 12:43:07 PM PDT 24	Apr 15 12:44:30 PM PDT 24	21450988604 ps
T143	/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.934685229	Apr 15 12:42:12 PM PDT 24	Apr 15 12:42:22 PM PDT 24	3376791487 ps
T133	/workspace/coverage/default/34.sram_ctrl_executable.89492727	Apr 15 12:43:53 PM PDT 24	Apr 15 12:51:24 PM PDT 24	50066870781 ps
T68	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.549242256	Apr 15 12:42:36 PM PDT 24	Apr 15 12:47:07 PM PDT 24	13997261234 ps
T25	/workspace/coverage/default/46.sram_ctrl_regwen.1289384694	Apr 15 12:45:29 PM PDT 24	Apr 15 12:51:46 PM PDT 24	1356477809 ps
T14	/workspace/coverage/default/39.sram_ctrl_smoke.3523272704	Apr 15 12:44:27 PM PDT 24	Apr 15 12:44:41 PM PDT 24	3172176480 ps
T141	/workspace/coverage/default/16.sram_ctrl_max_throughput.878091521	Apr 15 12:42:31 PM PDT 24	Apr 15 12:42:41 PM PDT 24	3085856586 ps
T29	/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3544329941	Apr 15 12:42:17 PM PDT 24	Apr 15 12:42:29 PM PDT 24	4028155816 ps
T89	/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.989561506	Apr 15 12:43:25 PM PDT 24	Apr 15 12:47:52 PM PDT 24	5322739360 ps
T90	/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2250803915	Apr 15 12:45:04 PM PDT 24	Apr 15 12:50:20 PM PDT 24	19666066968 ps
T16	/workspace/coverage/default/46.sram_ctrl_access_during_key_req.236103084	Apr 15 12:45:29 PM PDT 24	Apr 15 12:50:27 PM PDT 24	18367211789 ps
T8	/workspace/coverage/default/23.sram_ctrl_stress_all.2397167957	Apr 15 12:42:47 PM PDT 24	Apr 15 01:09:48 PM PDT 24	227683338555 ps
T43	/workspace/coverage/default/38.sram_ctrl_executable.373596092	Apr 15 12:44:22 PM PDT 24	Apr 15 01:02:17 PM PDT 24	50179806653 ps
T144	/workspace/coverage/default/42.sram_ctrl_mem_walk.3257414420	Apr 15 12:44:59 PM PDT 24	Apr 15 12:50:04 PM PDT 24	129185393660 ps
T145	/workspace/coverage/default/8.sram_ctrl_mem_walk.1397752682	Apr 15 12:42:07 PM PDT 24	Apr 15 12:44:15 PM PDT 24	7899496160 ps
T17	/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3340251228	Apr 15 12:41:45 PM PDT 24	Apr 15 12:56:44 PM PDT 24	44525303632 ps
T146	/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.889817543	Apr 15 12:42:12 PM PDT 24	Apr 15 12:42:20 PM PDT 24	3062737472 ps
T30	/workspace/coverage/default/29.sram_ctrl_ram_cfg.2516021578	Apr 15 12:43:16 PM PDT 24	Apr 15 12:43:20 PM PDT 24	562040756 ps
T76	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3195636628	Apr 15 12:42:48 PM PDT 24	Apr 15 12:43:59 PM PDT 24	2488663013 ps
T147	/workspace/coverage/default/24.sram_ctrl_bijection.1976300595	Apr 15 12:42:44 PM PDT 24	Apr 15 12:59:58 PM PDT 24	63481527197 ps
T77	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3186800951	Apr 15 12:42:29 PM PDT 24	Apr 15 12:50:57 PM PDT 24	8286154653 ps
T52	/workspace/coverage/default/0.sram_ctrl_regwen.2998956675	Apr 15 12:41:17 PM PDT 24	Apr 15 12:53:02 PM PDT 24	2365850305 ps
T148	/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.867199279	Apr 15 12:42:26 PM PDT 24	Apr 15 12:43:10 PM PDT 24	6778511172 ps
T28	/workspace/coverage/default/40.sram_ctrl_lc_escalation.3008446332	Apr 15 12:44:34 PM PDT 24	Apr 15 12:46:04 PM PDT 24	14329642283 ps
T149	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.663074331	Apr 15 12:42:30 PM PDT 24	Apr 15 12:43:41 PM PDT 24	1865426379 ps
T53	/workspace/coverage/default/26.sram_ctrl_stress_all.2578309232	Apr 15 12:42:53 PM PDT 24	Apr 15 01:36:28 PM PDT 24	116011102427 ps
T150	/workspace/coverage/default/37.sram_ctrl_smoke.2845568090	Apr 15 12:44:11 PM PDT 24	Apr 15 12:44:21 PM PDT 24	6463581568 ps
T151	/workspace/coverage/default/28.sram_ctrl_max_throughput.3611654730	Apr 15 12:43:06 PM PDT 24	Apr 15 12:44:33 PM PDT 24	3090260083 ps
T31	/workspace/coverage/default/38.sram_ctrl_ram_cfg.1281847945	Apr 15 12:44:29 PM PDT 24	Apr 15 12:44:32 PM PDT 24	353102586 ps
T152	/workspace/coverage/default/37.sram_ctrl_partial_access.2012550085	Apr 15 12:44:11 PM PDT 24	Apr 15 12:44:36 PM PDT 24	1471083342 ps
T91	/workspace/coverage/default/3.sram_ctrl_stress_pipeline.3432432381	Apr 15 12:41:46 PM PDT 24	Apr 15 12:47:11 PM PDT 24	6831774956 ps
T153	/workspace/coverage/default/34.sram_ctrl_bijection.2244017248	Apr 15 12:43:47 PM PDT 24	Apr 15 01:00:58 PM PDT 24	249038548239 ps
T54	/workspace/coverage/default/35.sram_ctrl_stress_all.1653248373	Apr 15 12:44:04 PM PDT 24	Apr 15 01:42:27 PM PDT 24	246144439442 ps
T154	/workspace/coverage/default/39.sram_ctrl_mem_walk.4243497811	Apr 15 12:44:32 PM PDT 24	Apr 15 12:48:33 PM PDT 24	3983601649 ps
T155	/workspace/coverage/default/42.sram_ctrl_max_throughput.3626968505	Apr 15 12:44:55 PM PDT 24	Apr 15 12:45:06 PM PDT 24	9723727154 ps
T45	/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1045177063	Apr 15 12:41:51 PM PDT 24	Apr 15 12:42:16 PM PDT 24	2089044110 ps
T156	/workspace/coverage/default/34.sram_ctrl_regwen.3312272664	Apr 15 12:43:53 PM PDT 24	Apr 15 12:53:58 PM PDT 24	3713963387 ps
T32	/workspace/coverage/default/12.sram_ctrl_ram_cfg.3171171188	Apr 15 12:42:24 PM PDT 24	Apr 15 12:42:28 PM PDT 24	711920700 ps
T92	/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1758447382	Apr 15 12:42:44 PM PDT 24	Apr 15 12:48:56 PM PDT 24	22594586660 ps
T93	/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2155616853	Apr 15 12:44:06 PM PDT 24	Apr 15 12:47:53 PM PDT 24	9605069417 ps
T157	/workspace/coverage/default/22.sram_ctrl_smoke.2363216644	Apr 15 12:42:38 PM PDT 24	Apr 15 12:42:48 PM PDT 24	2516268532 ps
T121	/workspace/coverage/default/5.sram_ctrl_lc_escalation.1684725005	Apr 15 12:41:49 PM PDT 24	Apr 15 12:42:59 PM PDT 24	10723082253 ps
T158	/workspace/coverage/default/1.sram_ctrl_max_throughput.2810590604	Apr 15 12:41:20 PM PDT 24	Apr 15 12:41:30 PM PDT 24	2831035350 ps
T44	/workspace/coverage/default/3.sram_ctrl_executable.2839835646	Apr 15 12:41:57 PM PDT 24	Apr 15 12:53:21 PM PDT 24	17400468361 ps
T159	/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.758108845	Apr 15 12:42:26 PM PDT 24	Apr 15 12:43:12 PM PDT 24	2943783406 ps
T160	/workspace/coverage/default/21.sram_ctrl_partial_access.836421987	Apr 15 12:42:38 PM PDT 24	Apr 15 12:42:45 PM PDT 24	425898838 ps
T26	/workspace/coverage/default/24.sram_ctrl_regwen.983682037	Apr 15 12:42:47 PM PDT 24	Apr 15 12:50:44 PM PDT 24	48359327978 ps
T161	/workspace/coverage/default/45.sram_ctrl_ram_cfg.3414778472	Apr 15 12:45:19 PM PDT 24	Apr 15 12:45:23 PM PDT 24	1403949167 ps
T46	/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1018422454	Apr 15 12:42:34 PM PDT 24	Apr 15 12:42:44 PM PDT 24	439820785 ps
T162	/workspace/coverage/default/37.sram_ctrl_mem_walk.3660288159	Apr 15 12:44:18 PM PDT 24	Apr 15 12:46:51 PM PDT 24	18262770605 ps
T163	/workspace/coverage/default/25.sram_ctrl_partial_access.2049936901	Apr 15 12:42:48 PM PDT 24	Apr 15 12:43:02 PM PDT 24	417651989 ps
T47	/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.180355321	Apr 15 12:43:02 PM PDT 24	Apr 15 12:43:13 PM PDT 24	918542466 ps
T164	/workspace/coverage/default/7.sram_ctrl_smoke.2101555163	Apr 15 12:41:54 PM PDT 24	Apr 15 12:42:45 PM PDT 24	1698426466 ps
T165	/workspace/coverage/default/44.sram_ctrl_multiple_keys.2968552982	Apr 15 12:45:09 PM PDT 24	Apr 15 01:07:07 PM PDT 24	19058902613 ps
T94	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.1638342470	Apr 15 12:44:37 PM PDT 24	Apr 15 12:50:36 PM PDT 24	4890637371 ps
T166	/workspace/coverage/default/25.sram_ctrl_mem_walk.2315348961	Apr 15 12:43:10 PM PDT 24	Apr 15 12:47:47 PM PDT 24	13750258562 ps
T167	/workspace/coverage/default/14.sram_ctrl_mem_walk.4242055740	Apr 15 12:42:22 PM PDT 24	Apr 15 12:45:03 PM PDT 24	29483783017 ps
T168	/workspace/coverage/default/0.sram_ctrl_multiple_keys.2482999787	Apr 15 12:41:14 PM PDT 24	Apr 15 01:03:48 PM PDT 24	91622632191 ps
T169	/workspace/coverage/default/39.sram_ctrl_stress_all.163668274	Apr 15 12:44:34 PM PDT 24	Apr 15 02:42:05 PM PDT 24	1720837815022 ps
T170	/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1950967334	Apr 15 12:42:23 PM PDT 24	Apr 15 12:49:20 PM PDT 24	9661496409 ps
T171	/workspace/coverage/default/29.sram_ctrl_bijection.2856594529	Apr 15 12:43:11 PM PDT 24	Apr 15 01:15:52 PM PDT 24	226031865217 ps
T172	/workspace/coverage/default/40.sram_ctrl_multiple_keys.1865686316	Apr 15 12:44:36 PM PDT 24	Apr 15 01:03:12 PM PDT 24	10069442155 ps
T27	/workspace/coverage/default/41.sram_ctrl_regwen.404141184	Apr 15 12:44:49 PM PDT 24	Apr 15 12:53:31 PM PDT 24	3599327797 ps
T173	/workspace/coverage/default/37.sram_ctrl_regwen.2371859762	Apr 15 12:44:18 PM PDT 24	Apr 15 01:08:12 PM PDT 24	86730049593 ps
T174	/workspace/coverage/default/41.sram_ctrl_multiple_keys.2953307229	Apr 15 12:44:44 PM PDT 24	Apr 15 12:58:32 PM PDT 24	5717746584 ps
T175	/workspace/coverage/default/21.sram_ctrl_multiple_keys.2116407782	Apr 15 12:42:39 PM PDT 24	Apr 15 12:43:35 PM PDT 24	13299357573 ps
T176	/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.46274516	Apr 15 12:41:46 PM PDT 24	Apr 15 12:42:34 PM PDT 24	2948863665 ps
T177	/workspace/coverage/default/24.sram_ctrl_max_throughput.3477694660	Apr 15 12:42:50 PM PDT 24	Apr 15 12:42:58 PM PDT 24	2393256612 ps
T178	/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1429621853	Apr 15 12:42:39 PM PDT 24	Apr 15 12:45:09 PM PDT 24	787889337 ps
T179	/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3949393033	Apr 15 12:43:18 PM PDT 24	Apr 15 12:43:28 PM PDT 24	2540076020 ps
T180	/workspace/coverage/default/8.sram_ctrl_multiple_keys.2148936668	Apr 15 12:41:57 PM PDT 24	Apr 15 12:50:44 PM PDT 24	52422373501 ps
T181	/workspace/coverage/default/16.sram_ctrl_partial_access.1229028526	Apr 15 12:42:32 PM PDT 24	Apr 15 12:42:41 PM PDT 24	2054711750 ps
T182	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3606290530	Apr 15 12:43:39 PM PDT 24	Apr 15 12:47:42 PM PDT 24	5036211311 ps
T183	/workspace/coverage/default/13.sram_ctrl_multiple_keys.955703888	Apr 15 12:42:20 PM PDT 24	Apr 15 12:45:33 PM PDT 24	7666150563 ps
T184	/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1280555819	Apr 15 12:42:30 PM PDT 24	Apr 15 12:46:45 PM PDT 24	42485938680 ps
T185	/workspace/coverage/default/24.sram_ctrl_mem_walk.160041720	Apr 15 12:42:46 PM PDT 24	Apr 15 12:48:23 PM PDT 24	105827132398 ps
T186	/workspace/coverage/default/8.sram_ctrl_smoke.721125607	Apr 15 12:42:01 PM PDT 24	Apr 15 12:42:12 PM PDT 24	496830887 ps
T78	/workspace/coverage/default/11.sram_ctrl_mem_partial_access.504723145	Apr 15 12:42:13 PM PDT 24	Apr 15 12:43:34 PM PDT 24	9774915861 ps
T187	/workspace/coverage/default/45.sram_ctrl_max_throughput.3725465853	Apr 15 12:45:19 PM PDT 24	Apr 15 12:45:29 PM PDT 24	1375429438 ps
T188	/workspace/coverage/default/29.sram_ctrl_multiple_keys.1618098041	Apr 15 12:43:11 PM PDT 24	Apr 15 12:52:37 PM PDT 24	46710802802 ps
T189	/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.966555018	Apr 15 12:44:03 PM PDT 24	Apr 15 12:48:13 PM PDT 24	17153362928 ps
T190	/workspace/coverage/default/21.sram_ctrl_executable.161386754	Apr 15 12:42:39 PM PDT 24	Apr 15 12:52:35 PM PDT 24	36116159822 ps
T191	/workspace/coverage/default/1.sram_ctrl_multiple_keys.3684226663	Apr 15 12:41:18 PM PDT 24	Apr 15 01:04:33 PM PDT 24	21045505449 ps
T192	/workspace/coverage/default/39.sram_ctrl_bijection.2518327720	Apr 15 12:44:26 PM PDT 24	Apr 15 01:07:04 PM PDT 24	20847512757 ps
T193	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3443718361	Apr 15 12:43:31 PM PDT 24	Apr 15 12:43:44 PM PDT 24	2878095181 ps
T79	/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2902476775	Apr 15 12:42:25 PM PDT 24	Apr 15 12:56:14 PM PDT 24	8608134870 ps
T18	/workspace/coverage/default/4.sram_ctrl_alert_test.3252334703	Apr 15 12:41:52 PM PDT 24	Apr 15 12:41:53 PM PDT 24	11047549 ps
T85	/workspace/coverage/default/34.sram_ctrl_mem_partial_access.594533143	Apr 15 12:43:51 PM PDT 24	Apr 15 12:46:12 PM PDT 24	5023319204 ps
T19	/workspace/coverage/default/43.sram_ctrl_alert_test.3563588340	Apr 15 12:45:09 PM PDT 24	Apr 15 12:45:11 PM PDT 24	24464036 ps
T194	/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2990199628	Apr 15 12:41:32 PM PDT 24	Apr 15 12:57:26 PM PDT 24	20724399760 ps
T195	/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1437431198	Apr 15 12:43:43 PM PDT 24	Apr 15 12:43:50 PM PDT 24	694775470 ps
T48	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.408132478	Apr 15 12:42:54 PM PDT 24	Apr 15 12:44:19 PM PDT 24	4163839752 ps
T140	/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2109203309	Apr 15 12:42:38 PM PDT 24	Apr 15 12:45:01 PM PDT 24	5900592006 ps
T196	/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2245850814	Apr 15 12:44:37 PM PDT 24	Apr 15 12:45:31 PM PDT 24	10642304022 ps
T49	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2439498825	Apr 15 12:41:26 PM PDT 24	Apr 15 12:41:44 PM PDT 24	4786996676 ps
T197	/workspace/coverage/default/27.sram_ctrl_partial_access.3610335964	Apr 15 12:43:00 PM PDT 24	Apr 15 12:43:16 PM PDT 24	557485486 ps
T198	/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2844379400	Apr 15 12:45:59 PM PDT 24	Apr 15 01:08:17 PM PDT 24	13580229186 ps
T135	/workspace/coverage/default/43.sram_ctrl_stress_all.2462835756	Apr 15 12:45:09 PM PDT 24	Apr 15 01:57:21 PM PDT 24	240428826308 ps
T199	/workspace/coverage/default/22.sram_ctrl_partial_access.951933130	Apr 15 12:42:43 PM PDT 24	Apr 15 12:44:43 PM PDT 24	868509164 ps
T200	/workspace/coverage/default/39.sram_ctrl_multiple_keys.1337308613	Apr 15 12:44:26 PM PDT 24	Apr 15 12:45:25 PM PDT 24	899655235 ps
T50	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2768494240	Apr 15 12:42:49 PM PDT 24	Apr 15 12:43:05 PM PDT 24	3412393722 ps
T201	/workspace/coverage/default/17.sram_ctrl_bijection.4206627926	Apr 15 12:42:29 PM PDT 24	Apr 15 01:03:21 PM PDT 24	362149223344 ps
T202	/workspace/coverage/default/3.sram_ctrl_lc_escalation.1932688836	Apr 15 12:41:48 PM PDT 24	Apr 15 12:43:11 PM PDT 24	13642516664 ps
T203	/workspace/coverage/default/25.sram_ctrl_max_throughput.1064876207	Apr 15 12:42:49 PM PDT 24	Apr 15 12:44:39 PM PDT 24	5332588457 ps
T204	/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.936561827	Apr 15 12:45:37 PM PDT 24	Apr 15 12:46:16 PM PDT 24	3301171172 ps
T205	/workspace/coverage/default/43.sram_ctrl_partial_access.536863412	Apr 15 12:45:04 PM PDT 24	Apr 15 12:45:24 PM PDT 24	1375180675 ps
T137	/workspace/coverage/default/35.sram_ctrl_multiple_keys.465423578	Apr 15 12:43:57 PM PDT 24	Apr 15 01:07:27 PM PDT 24	103015546543 ps
T206	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.2101624680	Apr 15 12:44:34 PM PDT 24	Apr 15 12:46:49 PM PDT 24	9112856052 ps
T207	/workspace/coverage/default/7.sram_ctrl_ram_cfg.3270936661	Apr 15 12:42:01 PM PDT 24	Apr 15 12:42:05 PM PDT 24	348138550 ps
T208	/workspace/coverage/default/22.sram_ctrl_regwen.1733861247	Apr 15 12:42:45 PM PDT 24	Apr 15 01:03:38 PM PDT 24	56558210076 ps
T209	/workspace/coverage/default/1.sram_ctrl_smoke.1138031107	Apr 15 12:41:18 PM PDT 24	Apr 15 12:41:33 PM PDT 24	3502942271 ps
T210	/workspace/coverage/default/43.sram_ctrl_smoke.2893307518	Apr 15 12:45:01 PM PDT 24	Apr 15 12:45:15 PM PDT 24	838722080 ps
T211	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.773059487	Apr 15 12:45:20 PM PDT 24	Apr 15 12:47:57 PM PDT 24	1575547305 ps
T212	/workspace/coverage/default/28.sram_ctrl_mem_walk.183037995	Apr 15 12:43:04 PM PDT 24	Apr 15 12:47:03 PM PDT 24	4065648277 ps
T213	/workspace/coverage/default/21.sram_ctrl_smoke.1396453156	Apr 15 12:42:39 PM PDT 24	Apr 15 12:43:36 PM PDT 24	8976460237 ps
T136	/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1781699711	Apr 15 12:44:37 PM PDT 24	Apr 15 12:48:45 PM PDT 24	11282416225 ps
T214	/workspace/coverage/default/5.sram_ctrl_bijection.3457865823	Apr 15 12:41:49 PM PDT 24	Apr 15 01:18:21 PM PDT 24	142263471216 ps
T215	/workspace/coverage/default/17.sram_ctrl_lc_escalation.3678744831	Apr 15 12:42:29 PM PDT 24	Apr 15 12:43:22 PM PDT 24	27233888697 ps
T216	/workspace/coverage/default/43.sram_ctrl_executable.436265845	Apr 15 12:45:05 PM PDT 24	Apr 15 12:56:17 PM PDT 24	6277882104 ps
T217	/workspace/coverage/default/28.sram_ctrl_ram_cfg.1628110702	Apr 15 12:43:07 PM PDT 24	Apr 15 12:43:11 PM PDT 24	362589279 ps
T218	/workspace/coverage/default/24.sram_ctrl_ram_cfg.1129701773	Apr 15 12:42:44 PM PDT 24	Apr 15 12:42:49 PM PDT 24	359118649 ps
T138	/workspace/coverage/default/41.sram_ctrl_executable.2942669285	Apr 15 12:44:49 PM PDT 24	Apr 15 12:55:04 PM PDT 24	179184685573 ps
T219	/workspace/coverage/default/17.sram_ctrl_regwen.2059661593	Apr 15 12:42:30 PM PDT 24	Apr 15 12:49:11 PM PDT 24	7701380622 ps
T220	/workspace/coverage/default/9.sram_ctrl_ram_cfg.1765135941	Apr 15 12:42:11 PM PDT 24	Apr 15 12:42:15 PM PDT 24	610230116 ps
T221	/workspace/coverage/default/27.sram_ctrl_stress_all.2619714618	Apr 15 12:43:04 PM PDT 24	Apr 15 01:31:31 PM PDT 24	79763204711 ps
T222	/workspace/coverage/default/11.sram_ctrl_smoke.3078696895	Apr 15 12:42:17 PM PDT 24	Apr 15 12:42:36 PM PDT 24	8537918120 ps
T223	/workspace/coverage/default/16.sram_ctrl_mem_walk.739753193	Apr 15 12:42:30 PM PDT 24	Apr 15 12:44:58 PM PDT 24	27531184036 ps
T224	/workspace/coverage/default/14.sram_ctrl_smoke.3345142478	Apr 15 12:42:22 PM PDT 24	Apr 15 12:42:48 PM PDT 24	7215388653 ps
T225	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.393711344	Apr 15 12:45:25 PM PDT 24	Apr 15 12:45:56 PM PDT 24	769308448 ps
T226	/workspace/coverage/default/14.sram_ctrl_ram_cfg.3872916839	Apr 15 12:42:23 PM PDT 24	Apr 15 12:42:28 PM PDT 24	1972216201 ps
T227	/workspace/coverage/default/5.sram_ctrl_partial_access.1406280435	Apr 15 12:42:02 PM PDT 24	Apr 15 12:43:38 PM PDT 24	3564743131 ps
T228	/workspace/coverage/default/40.sram_ctrl_smoke.803414917	Apr 15 12:44:36 PM PDT 24	Apr 15 12:44:56 PM PDT 24	3367556649 ps
T229	/workspace/coverage/default/7.sram_ctrl_regwen.4091722343	Apr 15 12:41:59 PM PDT 24	Apr 15 01:03:53 PM PDT 24	27228626871 ps
T230	/workspace/coverage/default/35.sram_ctrl_executable.1797184526	Apr 15 12:44:03 PM PDT 24	Apr 15 12:55:28 PM PDT 24	24065467912 ps
T231	/workspace/coverage/default/43.sram_ctrl_regwen.1934277301	Apr 15 12:45:03 PM PDT 24	Apr 15 12:46:43 PM PDT 24	2492141825 ps
T20	/workspace/coverage/default/14.sram_ctrl_alert_test.2233686049	Apr 15 12:42:32 PM PDT 24	Apr 15 12:42:34 PM PDT 24	20879459 ps
T232	/workspace/coverage/default/38.sram_ctrl_max_throughput.4039918086	Apr 15 12:44:22 PM PDT 24	Apr 15 12:44:36 PM PDT 24	1357965959 ps
T51	/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1169353550	Apr 15 12:41:45 PM PDT 24	Apr 15 12:44:29 PM PDT 24	6020617526 ps
T233	/workspace/coverage/default/27.sram_ctrl_bijection.2501905357	Apr 15 12:42:57 PM PDT 24	Apr 15 01:03:34 PM PDT 24	864261332007 ps
T234	/workspace/coverage/default/6.sram_ctrl_smoke.3061976661	Apr 15 12:41:51 PM PDT 24	Apr 15 12:41:59 PM PDT 24	3315021474 ps
T235	/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1891642256	Apr 15 12:45:48 PM PDT 24	Apr 15 12:50:11 PM PDT 24	18184906461 ps
T236	/workspace/coverage/default/9.sram_ctrl_partial_access.3878149390	Apr 15 12:42:04 PM PDT 24	Apr 15 12:42:09 PM PDT 24	2356113494 ps
T237	/workspace/coverage/default/31.sram_ctrl_multiple_keys.2785669623	Apr 15 12:43:22 PM PDT 24	Apr 15 12:55:51 PM PDT 24	25499835172 ps
T238	/workspace/coverage/default/13.sram_ctrl_regwen.2804318972	Apr 15 12:42:26 PM PDT 24	Apr 15 12:50:25 PM PDT 24	10431278619 ps
T239	/workspace/coverage/default/18.sram_ctrl_access_during_key_req.2788817496	Apr 15 12:42:34 PM PDT 24	Apr 15 12:53:45 PM PDT 24	75852889103 ps
T240	/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1153408642	Apr 15 12:43:40 PM PDT 24	Apr 15 12:49:25 PM PDT 24	9587846686 ps
T241	/workspace/coverage/default/49.sram_ctrl_stress_all.2706372729	Apr 15 12:45:59 PM PDT 24	Apr 15 01:35:22 PM PDT 24	97768718708 ps
T242	/workspace/coverage/default/29.sram_ctrl_smoke.303985365	Apr 15 12:43:10 PM PDT 24	Apr 15 12:43:30 PM PDT 24	2081945360 ps
T243	/workspace/coverage/default/11.sram_ctrl_bijection.1509031956	Apr 15 12:42:14 PM PDT 24	Apr 15 01:26:19 PM PDT 24	287092698643 ps
T22	/workspace/coverage/default/1.sram_ctrl_sec_cm.3340983698	Apr 15 12:41:25 PM PDT 24	Apr 15 12:41:28 PM PDT 24	319713498 ps
T35	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.215679035	Apr 15 12:44:54 PM PDT 24	Apr 15 12:45:12 PM PDT 24	728884628 ps
T36	/workspace/coverage/default/15.sram_ctrl_stress_all.3241303010	Apr 15 12:42:28 PM PDT 24	Apr 15 01:59:02 PM PDT 24	188227587191 ps
T37	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1962051260	Apr 15 12:41:51 PM PDT 24	Apr 15 12:42:05 PM PDT 24	697008880 ps
T38	/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1355389050	Apr 15 12:42:43 PM PDT 24	Apr 15 12:45:10 PM PDT 24	6386811495 ps
T39	/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.4262059148	Apr 15 12:44:53 PM PDT 24	Apr 15 12:45:02 PM PDT 24	174323045 ps
T40	/workspace/coverage/default/47.sram_ctrl_smoke.3312135827	Apr 15 12:45:34 PM PDT 24	Apr 15 12:45:53 PM PDT 24	3076811949 ps
T41	/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1287092637	Apr 15 12:41:28 PM PDT 24	Apr 15 12:46:38 PM PDT 24	14135016344 ps
T23	/workspace/coverage/default/2.sram_ctrl_sec_cm.551919626	Apr 15 12:41:56 PM PDT 24	Apr 15 12:42:00 PM PDT 24	675269023 ps
T42	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3730441436	Apr 15 12:45:49 PM PDT 24	Apr 15 12:47:08 PM PDT 24	25974463322 ps
T244	/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.919847537	Apr 15 12:43:27 PM PDT 24	Apr 15 12:45:21 PM PDT 24	782381888 ps
T245	/workspace/coverage/default/9.sram_ctrl_multiple_keys.1959155021	Apr 15 12:42:02 PM PDT 24	Apr 15 12:45:02 PM PDT 24	1628233298 ps
T246	/workspace/coverage/default/8.sram_ctrl_partial_access.1305959392	Apr 15 12:42:01 PM PDT 24	Apr 15 12:42:48 PM PDT 24	4870989648 ps
T247	/workspace/coverage/default/47.sram_ctrl_executable.2717479904	Apr 15 12:45:39 PM PDT 24	Apr 15 01:01:32 PM PDT 24	17996183662 ps
T248	/workspace/coverage/default/47.sram_ctrl_max_throughput.3299271838	Apr 15 12:45:41 PM PDT 24	Apr 15 12:47:55 PM PDT 24	3816815959 ps
T249	/workspace/coverage/default/38.sram_ctrl_mem_walk.3725671614	Apr 15 12:44:28 PM PDT 24	Apr 15 12:48:29 PM PDT 24	17901907117 ps
T250	/workspace/coverage/default/48.sram_ctrl_ram_cfg.1847723940	Apr 15 12:45:50 PM PDT 24	Apr 15 12:45:54 PM PDT 24	717809388 ps
T251	/workspace/coverage/default/12.sram_ctrl_stress_all.3040542106	Apr 15 12:42:16 PM PDT 24	Apr 15 02:17:29 PM PDT 24	137835125825 ps
T252	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1919358153	Apr 15 12:43:49 PM PDT 24	Apr 15 12:46:17 PM PDT 24	18131741736 ps
T253	/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.813900615	Apr 15 12:42:03 PM PDT 24	Apr 15 12:44:09 PM PDT 24	842893960 ps
T254	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.3625487063	Apr 15 12:42:54 PM PDT 24	Apr 15 12:45:02 PM PDT 24	7099514576 ps
T255	/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1366896006	Apr 15 12:42:29 PM PDT 24	Apr 15 12:43:30 PM PDT 24	4929755144 ps
T256	/workspace/coverage/default/30.sram_ctrl_partial_access.1134017413	Apr 15 12:43:17 PM PDT 24	Apr 15 12:43:43 PM PDT 24	3302969285 ps
T257	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.2488716454	Apr 15 12:42:40 PM PDT 24	Apr 15 12:47:44 PM PDT 24	4218242121 ps
T258	/workspace/coverage/default/33.sram_ctrl_multiple_keys.1204734652	Apr 15 12:43:39 PM PDT 24	Apr 15 01:02:39 PM PDT 24	25151552230 ps
T259	/workspace/coverage/default/16.sram_ctrl_executable.4139349351	Apr 15 12:42:33 PM PDT 24	Apr 15 12:52:33 PM PDT 24	90058045671 ps
T260	/workspace/coverage/default/45.sram_ctrl_alert_test.2446481532	Apr 15 12:45:21 PM PDT 24	Apr 15 12:45:22 PM PDT 24	35791442 ps
T102	/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3993931562	Apr 15 12:42:17 PM PDT 24	Apr 15 12:43:10 PM PDT 24	6732948823 ps
T112	/workspace/coverage/default/40.sram_ctrl_regwen.4008215211	Apr 15 12:44:36 PM PDT 24	Apr 15 01:15:35 PM PDT 24	21287002258 ps
T113	/workspace/coverage/default/6.sram_ctrl_multiple_keys.4180465781	Apr 15 12:41:56 PM PDT 24	Apr 15 12:59:14 PM PDT 24	49593774832 ps
T114	/workspace/coverage/default/6.sram_ctrl_ram_cfg.2275978714	Apr 15 12:42:02 PM PDT 24	Apr 15 12:42:06 PM PDT 24	712898908 ps
T115	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4122091793	Apr 15 12:41:14 PM PDT 24	Apr 15 12:41:34 PM PDT 24	686113894 ps
T116	/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.55354214	Apr 15 12:42:43 PM PDT 24	Apr 15 12:46:56 PM PDT 24	10186220555 ps
T117	/workspace/coverage/default/32.sram_ctrl_stress_all.3362600959	Apr 15 12:43:32 PM PDT 24	Apr 15 01:18:54 PM PDT 24	108448820416 ps
T118	/workspace/coverage/default/48.sram_ctrl_stress_all.2592807610	Apr 15 12:45:47 PM PDT 24	Apr 15 01:52:55 PM PDT 24	104000803005 ps
T119	/workspace/coverage/default/5.sram_ctrl_alert_test.1106448105	Apr 15 12:41:56 PM PDT 24	Apr 15 12:41:57 PM PDT 24	14760962 ps
T120	/workspace/coverage/default/25.sram_ctrl_multiple_keys.3028684861	Apr 15 12:42:52 PM PDT 24	Apr 15 12:55:15 PM PDT 24	33876235991 ps
T261	/workspace/coverage/default/25.sram_ctrl_access_during_key_req.1648940976	Apr 15 12:42:52 PM PDT 24	Apr 15 01:08:01 PM PDT 24	28079894111 ps
T262	/workspace/coverage/default/20.sram_ctrl_access_during_key_req.1493739035	Apr 15 12:42:39 PM PDT 24	Apr 15 01:02:35 PM PDT 24	19720493086 ps
T263	/workspace/coverage/default/34.sram_ctrl_smoke.4154417741	Apr 15 12:43:46 PM PDT 24	Apr 15 12:44:00 PM PDT 24	1484737614 ps
T264	/workspace/coverage/default/26.sram_ctrl_max_throughput.1542686431	Apr 15 12:42:58 PM PDT 24	Apr 15 12:43:06 PM PDT 24	3031711553 ps
T265	/workspace/coverage/default/26.sram_ctrl_partial_access.175898797	Apr 15 12:42:57 PM PDT 24	Apr 15 12:44:01 PM PDT 24	855616918 ps
T266	/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1374454975	Apr 15 12:42:12 PM PDT 24	Apr 15 12:44:41 PM PDT 24	13164277191 ps
T267	/workspace/coverage/default/42.sram_ctrl_alert_test.3412127190	Apr 15 12:45:05 PM PDT 24	Apr 15 12:45:06 PM PDT 24	13859507 ps
T268	/workspace/coverage/default/22.sram_ctrl_stress_all.2427572963	Apr 15 12:42:42 PM PDT 24	Apr 15 01:58:27 PM PDT 24	196820067279 ps
T269	/workspace/coverage/default/15.sram_ctrl_ram_cfg.203930422	Apr 15 12:42:31 PM PDT 24	Apr 15 12:42:35 PM PDT 24	401194242 ps
T270	/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2239277892	Apr 15 12:42:38 PM PDT 24	Apr 15 12:46:41 PM PDT 24	45069476768 ps
T271	/workspace/coverage/default/20.sram_ctrl_mem_walk.140605652	Apr 15 12:42:37 PM PDT 24	Apr 15 12:44:39 PM PDT 24	21908628614 ps
T272	/workspace/coverage/default/7.sram_ctrl_mem_partial_access.717917743	Apr 15 12:42:38 PM PDT 24	Apr 15 12:45:07 PM PDT 24	19123887033 ps
T273	/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3569792176	Apr 15 12:43:26 PM PDT 24	Apr 15 12:51:52 PM PDT 24	18790632575 ps
T274	/workspace/coverage/default/10.sram_ctrl_partial_access.372545058	Apr 15 12:42:07 PM PDT 24	Apr 15 12:42:22 PM PDT 24	4432833380 ps
T275	/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.4270666227	Apr 15 12:42:57 PM PDT 24	Apr 15 12:43:06 PM PDT 24	2706250211 ps
T276	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.4243626435	Apr 15 12:45:48 PM PDT 24	Apr 15 12:48:09 PM PDT 24	5243757379 ps
T277	/workspace/coverage/default/8.sram_ctrl_bijection.3706770393	Apr 15 12:42:00 PM PDT 24	Apr 15 12:50:36 PM PDT 24	43139583324 ps
T278	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1524331572	Apr 15 12:42:58 PM PDT 24	Apr 15 12:43:12 PM PDT 24	710191396 ps
T279	/workspace/coverage/default/30.sram_ctrl_max_throughput.3394136422	Apr 15 12:43:19 PM PDT 24	Apr 15 12:45:34 PM PDT 24	3056146446 ps
T280	/workspace/coverage/default/44.sram_ctrl_partial_access.4214555847	Apr 15 12:45:10 PM PDT 24	Apr 15 12:45:29 PM PDT 24	620763481 ps
T281	/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1155402815	Apr 15 12:41:17 PM PDT 24	Apr 15 12:41:25 PM PDT 24	711153725 ps
T282	/workspace/coverage/default/18.sram_ctrl_lc_escalation.3519503585	Apr 15 12:42:30 PM PDT 24	Apr 15 12:44:16 PM PDT 24	16568483015 ps
T283	/workspace/coverage/default/14.sram_ctrl_stress_all.1754730401	Apr 15 12:42:25 PM PDT 24	Apr 15 01:40:46 PM PDT 24	317785863607 ps
T139	/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2942424354	Apr 15 12:45:10 PM PDT 24	Apr 15 12:49:44 PM PDT 24	12535641600 ps
T284	/workspace/coverage/default/29.sram_ctrl_stress_pipeline.1631089151	Apr 15 12:43:14 PM PDT 24	Apr 15 12:46:57 PM PDT 24	3722571269 ps
T285	/workspace/coverage/default/9.sram_ctrl_mem_walk.3621530129	Apr 15 12:42:20 PM PDT 24	Apr 15 12:44:22 PM PDT 24	7890474525 ps
T286	/workspace/coverage/default/17.sram_ctrl_access_during_key_req.2026877308	Apr 15 12:42:30 PM PDT 24	Apr 15 12:51:23 PM PDT 24	11728601314 ps
T287	/workspace/coverage/default/31.sram_ctrl_executable.3884882337	Apr 15 12:43:26 PM PDT 24	Apr 15 12:56:02 PM PDT 24	46895405264 ps
T288	/workspace/coverage/default/41.sram_ctrl_mem_walk.171578410	Apr 15 12:44:49 PM PDT 24	Apr 15 12:49:46 PM PDT 24	14340607359 ps
T289	/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.396447299	Apr 15 12:42:22 PM PDT 24	Apr 15 12:45:54 PM PDT 24	36671884000 ps
T290	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1735561462	Apr 15 12:42:23 PM PDT 24	Apr 15 12:46:51 PM PDT 24	3781346610 ps
T291	/workspace/coverage/default/43.sram_ctrl_max_throughput.728111238	Apr 15 12:45:05 PM PDT 24	Apr 15 12:45:58 PM PDT 24	947923288 ps
T292	/workspace/coverage/default/23.sram_ctrl_mem_partial_access.176943323	Apr 15 12:42:44 PM PDT 24	Apr 15 12:45:11 PM PDT 24	10208425741 ps
T293	/workspace/coverage/default/9.sram_ctrl_stress_all.3774960951	Apr 15 12:42:17 PM PDT 24	Apr 15 01:18:07 PM PDT 24	56396878118 ps
T294	/workspace/coverage/default/8.sram_ctrl_lc_escalation.1578874149	Apr 15 12:42:05 PM PDT 24	Apr 15 12:43:17 PM PDT 24	24555128075 ps
T295	/workspace/coverage/default/47.sram_ctrl_lc_escalation.4058700361	Apr 15 12:45:39 PM PDT 24	Apr 15 12:47:08 PM PDT 24	46057495020 ps
T296	/workspace/coverage/default/15.sram_ctrl_lc_escalation.3609726654	Apr 15 12:42:27 PM PDT 24	Apr 15 12:42:43 PM PDT 24	2271454903 ps
T297	/workspace/coverage/default/1.sram_ctrl_bijection.3172980261	Apr 15 12:41:16 PM PDT 24	Apr 15 01:09:12 PM PDT 24	24992069304 ps
T298	/workspace/coverage/default/26.sram_ctrl_stress_pipeline.229386685	Apr 15 12:42:58 PM PDT 24	Apr 15 12:45:52 PM PDT 24	10014937773 ps
T299	/workspace/coverage/default/35.sram_ctrl_stress_pipeline.3599205342	Apr 15 12:43:56 PM PDT 24	Apr 15 12:48:23 PM PDT 24	3874539815 ps
T300	/workspace/coverage/default/9.sram_ctrl_max_throughput.2059851415	Apr 15 12:42:04 PM PDT 24	Apr 15 12:42:12 PM PDT 24	679350123 ps
T301	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3275009967	Apr 15 12:42:32 PM PDT 24	Apr 15 12:44:11 PM PDT 24	792743058 ps
T302	/workspace/coverage/default/6.sram_ctrl_mem_partial_access.192507285	Apr 15 12:41:51 PM PDT 24	Apr 15 12:44:00 PM PDT 24	12044159846 ps
T303	/workspace/coverage/default/22.sram_ctrl_executable.3048722590	Apr 15 12:42:43 PM PDT 24	Apr 15 12:47:18 PM PDT 24	9215659398 ps
T304	/workspace/coverage/default/23.sram_ctrl_max_throughput.1091106763	Apr 15 12:42:44 PM PDT 24	Apr 15 12:44:28 PM PDT 24	2885428356 ps