Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	144899238	1			T2	98303		T3	3199		T4	4888
triple_byte_access	2725192	1			T3	7006		T4	94		T5	2945
halfword_access	4179473	1			T3	13200		T4	137		T5	4421
byte_access	5834196	1			T3	24607		T4	205		T5	5872
zero_access	1758457	1			T3	14729		T4	58		T5	1411

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79504965

1

T2

32768

T3

31468

T4

2689

auto[1]

79891591

1

T2

65535

T3

31273

T4

2693

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	72122179	1			T2	32768		T3	262		T4	2438
auto[0]	triple_byte_access	1303014	1			T3	1422		T4	49		T5	1534
auto[0]	halfword_access	2043383	1			T3	4529		T4	65		T5	2211
auto[0]	byte_access	2990377	1			T3	13279		T4	105		T5	2993
auto[0]	zero_access	1046012	1			T3	11976		T4	32		T5	715
auto[1]	word_access	72777059	1			T2	65535		T3	2937		T4	2450
auto[1]	triple_byte_access	1422178	1			T3	5584		T4	45		T5	1411
auto[1]	halfword_access	2136090	1			T3	8671		T4	72		T5	2210
auto[1]	byte_access	2843819	1			T3	11328		T4	100		T5	2879
auto[1]	zero_access	712445	1			T3	2753		T4	26		T5	696