| T794 |
/workspace/coverage/default/29.sram_ctrl_alert_test.3836103409 |
|
|
Apr 15 12:43:18 PM PDT 24 |
Apr 15 12:43:19 PM PDT 24 |
42749568 ps |
| T795 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2806339958 |
|
|
Apr 15 12:42:32 PM PDT 24 |
Apr 15 12:49:35 PM PDT 24 |
52532187496 ps |
| T796 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.1942456203 |
|
|
Apr 15 12:44:08 PM PDT 24 |
Apr 15 12:47:35 PM PDT 24 |
23892148035 ps |
| T797 |
/workspace/coverage/default/4.sram_ctrl_bijection.3127913865 |
|
|
Apr 15 12:41:57 PM PDT 24 |
Apr 15 12:58:42 PM PDT 24 |
59084283801 ps |
| T798 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1055927671 |
|
|
Apr 15 12:44:55 PM PDT 24 |
Apr 15 12:46:31 PM PDT 24 |
31068432853 ps |
| T799 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.2644260247 |
|
|
Apr 15 12:44:33 PM PDT 24 |
Apr 15 12:44:37 PM PDT 24 |
362772064 ps |
| T800 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.1761386078 |
|
|
Apr 15 12:43:42 PM PDT 24 |
Apr 15 12:45:08 PM PDT 24 |
1185968062 ps |
| T801 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.4255139454 |
|
|
Apr 15 12:43:22 PM PDT 24 |
Apr 15 01:04:39 PM PDT 24 |
63670656293 ps |
| T802 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1034830153 |
|
|
Apr 15 12:45:15 PM PDT 24 |
Apr 15 12:58:46 PM PDT 24 |
17238587296 ps |
| T803 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3174601356 |
|
|
Apr 15 12:45:15 PM PDT 24 |
Apr 15 01:54:37 PM PDT 24 |
757388190137 ps |
| T804 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1083063490 |
|
|
Apr 15 12:45:15 PM PDT 24 |
Apr 15 12:45:20 PM PDT 24 |
2254004869 ps |
| T805 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2099555593 |
|
|
Apr 15 12:42:05 PM PDT 24 |
Apr 15 12:56:06 PM PDT 24 |
19907305988 ps |
| T806 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.3301353659 |
|
|
Apr 15 12:42:42 PM PDT 24 |
Apr 15 12:42:52 PM PDT 24 |
1051135931 ps |
| T807 |
/workspace/coverage/default/21.sram_ctrl_alert_test.1707032083 |
|
|
Apr 15 12:42:39 PM PDT 24 |
Apr 15 12:42:41 PM PDT 24 |
43515380 ps |
| T808 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2256934859 |
|
|
Apr 15 12:44:28 PM PDT 24 |
Apr 15 12:44:41 PM PDT 24 |
3213281775 ps |
| T809 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.3725101862 |
|
|
Apr 15 12:43:20 PM PDT 24 |
Apr 15 12:44:53 PM PDT 24 |
14325934055 ps |
| T810 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2015165491 |
|
|
Apr 15 12:43:04 PM PDT 24 |
Apr 15 12:51:35 PM PDT 24 |
44938877289 ps |
| T811 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.760294562 |
|
|
Apr 15 12:42:40 PM PDT 24 |
Apr 15 12:44:13 PM PDT 24 |
52156733025 ps |
| T812 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.1554643687 |
|
|
Apr 15 12:42:32 PM PDT 24 |
Apr 15 12:52:50 PM PDT 24 |
12680725198 ps |
| T813 |
/workspace/coverage/default/18.sram_ctrl_regwen.3877553458 |
|
|
Apr 15 12:42:32 PM PDT 24 |
Apr 15 12:59:47 PM PDT 24 |
3692086701 ps |
| T814 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3059755613 |
|
|
Apr 15 12:42:41 PM PDT 24 |
Apr 15 12:42:58 PM PDT 24 |
735591759 ps |
| T815 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.373529431 |
|
|
Apr 15 12:42:49 PM PDT 24 |
Apr 15 12:45:49 PM PDT 24 |
5429741634 ps |
| T816 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.539332438 |
|
|
Apr 15 12:43:05 PM PDT 24 |
Apr 15 12:46:50 PM PDT 24 |
16352303891 ps |
| T817 |
/workspace/coverage/default/1.sram_ctrl_partial_access.2254453287 |
|
|
Apr 15 12:41:22 PM PDT 24 |
Apr 15 12:41:28 PM PDT 24 |
396189329 ps |
| T818 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.3034105552 |
|
|
Apr 15 12:43:31 PM PDT 24 |
Apr 15 12:48:15 PM PDT 24 |
28124257497 ps |
| T819 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.2836451055 |
|
|
Apr 15 12:41:47 PM PDT 24 |
Apr 15 01:00:11 PM PDT 24 |
15808349580 ps |
| T820 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2276602246 |
|
|
Apr 15 12:41:59 PM PDT 24 |
Apr 15 12:42:54 PM PDT 24 |
8155427963 ps |
| T821 |
/workspace/coverage/default/46.sram_ctrl_smoke.3996510365 |
|
|
Apr 15 12:45:21 PM PDT 24 |
Apr 15 12:46:56 PM PDT 24 |
1223665141 ps |
| T822 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1619192130 |
|
|
Apr 15 12:43:15 PM PDT 24 |
Apr 15 12:49:46 PM PDT 24 |
15669391261 ps |
| T823 |
/workspace/coverage/default/28.sram_ctrl_smoke.2486624372 |
|
|
Apr 15 12:43:04 PM PDT 24 |
Apr 15 12:43:22 PM PDT 24 |
848404814 ps |
| T824 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.2969019338 |
|
|
Apr 15 12:43:21 PM PDT 24 |
Apr 15 12:48:20 PM PDT 24 |
4696304344 ps |
| T825 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.349378031 |
|
|
Apr 15 12:44:50 PM PDT 24 |
Apr 15 12:46:37 PM PDT 24 |
96606635633 ps |
| T826 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2939729729 |
|
|
Apr 15 12:42:26 PM PDT 24 |
Apr 15 12:48:09 PM PDT 24 |
11140927244 ps |
| T827 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.2632311347 |
|
|
Apr 15 12:41:45 PM PDT 24 |
Apr 15 12:41:49 PM PDT 24 |
410397297 ps |
| T828 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2960072753 |
|
|
Apr 15 12:45:38 PM PDT 24 |
Apr 15 12:45:43 PM PDT 24 |
1771806689 ps |
| T829 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2073368264 |
|
|
Apr 15 12:41:54 PM PDT 24 |
Apr 15 12:54:33 PM PDT 24 |
33817277896 ps |
| T830 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1667045125 |
|
|
Apr 15 12:45:49 PM PDT 24 |
Apr 15 12:50:46 PM PDT 24 |
2740236051 ps |
| T831 |
/workspace/coverage/default/41.sram_ctrl_bijection.2804634374 |
|
|
Apr 15 12:44:46 PM PDT 24 |
Apr 15 12:59:03 PM PDT 24 |
231294852132 ps |
| T832 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.4003465147 |
|
|
Apr 15 12:43:23 PM PDT 24 |
Apr 15 12:44:27 PM PDT 24 |
3764550903 ps |
| T833 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.3919428341 |
|
|
Apr 15 12:42:57 PM PDT 24 |
Apr 15 12:46:48 PM PDT 24 |
7580285364 ps |
| T834 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2041688156 |
|
|
Apr 15 12:42:40 PM PDT 24 |
Apr 15 12:48:05 PM PDT 24 |
16886789746 ps |
| T835 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.94192894 |
|
|
Apr 15 12:41:49 PM PDT 24 |
Apr 15 12:41:53 PM PDT 24 |
1609396319 ps |
| T836 |
/workspace/coverage/default/8.sram_ctrl_regwen.3159954498 |
|
|
Apr 15 12:42:06 PM PDT 24 |
Apr 15 12:57:02 PM PDT 24 |
3658159218 ps |
| T837 |
/workspace/coverage/default/38.sram_ctrl_stress_all.1603920558 |
|
|
Apr 15 12:44:30 PM PDT 24 |
Apr 15 01:26:08 PM PDT 24 |
66623414700 ps |
| T838 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.1860250509 |
|
|
Apr 15 12:43:25 PM PDT 24 |
Apr 15 12:46:47 PM PDT 24 |
26618324915 ps |
| T839 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3233215279 |
|
|
Apr 15 12:42:17 PM PDT 24 |
Apr 15 12:58:52 PM PDT 24 |
14212457456 ps |
| T840 |
/workspace/coverage/default/33.sram_ctrl_stress_all.2090919860 |
|
|
Apr 15 12:43:46 PM PDT 24 |
Apr 15 01:33:02 PM PDT 24 |
238734261616 ps |
| T841 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.3881691834 |
|
|
Apr 15 12:42:36 PM PDT 24 |
Apr 15 12:54:36 PM PDT 24 |
13445694474 ps |
| T842 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3348840111 |
|
|
Apr 15 12:45:59 PM PDT 24 |
Apr 15 12:53:19 PM PDT 24 |
54904029064 ps |
| T843 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.580492819 |
|
|
Apr 15 12:42:13 PM PDT 24 |
Apr 15 12:46:16 PM PDT 24 |
7948398173 ps |
| T844 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.431664716 |
|
|
Apr 15 12:42:43 PM PDT 24 |
Apr 15 12:42:52 PM PDT 24 |
1958255685 ps |
| T845 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.2715487935 |
|
|
Apr 15 12:42:32 PM PDT 24 |
Apr 15 12:47:29 PM PDT 24 |
28615181027 ps |
| T846 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.3604911638 |
|
|
Apr 15 12:44:34 PM PDT 24 |
Apr 15 12:46:20 PM PDT 24 |
1591133973 ps |
| T847 |
/workspace/coverage/default/45.sram_ctrl_stress_all.573494140 |
|
|
Apr 15 12:45:21 PM PDT 24 |
Apr 15 01:24:09 PM PDT 24 |
246889749632 ps |
| T848 |
/workspace/coverage/default/23.sram_ctrl_alert_test.1539361264 |
|
|
Apr 15 12:42:45 PM PDT 24 |
Apr 15 12:42:47 PM PDT 24 |
12017607 ps |
| T849 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.765083330 |
|
|
Apr 15 12:41:50 PM PDT 24 |
Apr 15 12:41:54 PM PDT 24 |
2112948005 ps |
| T850 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.3801718197 |
|
|
Apr 15 12:45:27 PM PDT 24 |
Apr 15 12:49:35 PM PDT 24 |
8388743860 ps |
| T851 |
/workspace/coverage/default/17.sram_ctrl_smoke.2967051245 |
|
|
Apr 15 12:42:30 PM PDT 24 |
Apr 15 12:42:47 PM PDT 24 |
2716528454 ps |
| T852 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.4219377461 |
|
|
Apr 15 12:41:43 PM PDT 24 |
Apr 15 12:41:50 PM PDT 24 |
690917516 ps |
| T853 |
/workspace/coverage/default/34.sram_ctrl_stress_all.1768277337 |
|
|
Apr 15 12:43:53 PM PDT 24 |
Apr 15 01:30:53 PM PDT 24 |
42859233926 ps |
| T854 |
/workspace/coverage/default/1.sram_ctrl_executable.238725053 |
|
|
Apr 15 12:41:27 PM PDT 24 |
Apr 15 12:56:17 PM PDT 24 |
26837994749 ps |
| T855 |
/workspace/coverage/default/0.sram_ctrl_alert_test.2105468536 |
|
|
Apr 15 12:41:14 PM PDT 24 |
Apr 15 12:41:15 PM PDT 24 |
29547602 ps |
| T856 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1152697917 |
|
|
Apr 15 12:42:22 PM PDT 24 |
Apr 15 12:48:23 PM PDT 24 |
32162943776 ps |
| T857 |
/workspace/coverage/default/10.sram_ctrl_regwen.4283095222 |
|
|
Apr 15 12:42:20 PM PDT 24 |
Apr 15 12:55:24 PM PDT 24 |
46074848399 ps |
| T858 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3731703105 |
|
|
Apr 15 12:42:04 PM PDT 24 |
Apr 15 12:44:45 PM PDT 24 |
20390681525 ps |
| T859 |
/workspace/coverage/default/39.sram_ctrl_regwen.504661369 |
|
|
Apr 15 12:44:31 PM PDT 24 |
Apr 15 12:48:00 PM PDT 24 |
16846899820 ps |
| T860 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1406356213 |
|
|
Apr 15 12:41:23 PM PDT 24 |
Apr 15 12:41:38 PM PDT 24 |
735323353 ps |
| T861 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2461609431 |
|
|
Apr 15 12:43:12 PM PDT 24 |
Apr 15 12:45:23 PM PDT 24 |
3131413164 ps |
| T862 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.2941256461 |
|
|
Apr 15 12:42:29 PM PDT 24 |
Apr 15 12:42:33 PM PDT 24 |
1410499109 ps |
| T863 |
/workspace/coverage/default/34.sram_ctrl_partial_access.3678804124 |
|
|
Apr 15 12:43:45 PM PDT 24 |
Apr 15 12:44:06 PM PDT 24 |
1815921293 ps |
| T864 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.626524406 |
|
|
Apr 15 12:45:16 PM PDT 24 |
Apr 15 12:46:01 PM PDT 24 |
5468290114 ps |
| T865 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.412340705 |
|
|
Apr 15 12:43:26 PM PDT 24 |
Apr 15 12:44:40 PM PDT 24 |
5775211172 ps |
| T866 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.4098787264 |
|
|
Apr 15 12:42:01 PM PDT 24 |
Apr 15 12:44:26 PM PDT 24 |
7198897628 ps |
| T867 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1875968868 |
|
|
Apr 15 12:42:37 PM PDT 24 |
Apr 15 12:42:41 PM PDT 24 |
366946166 ps |
| T868 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.3948059934 |
|
|
Apr 15 12:42:24 PM PDT 24 |
Apr 15 12:43:55 PM PDT 24 |
3174714456 ps |
| T869 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.871047061 |
|
|
Apr 15 12:45:34 PM PDT 24 |
Apr 15 12:55:31 PM PDT 24 |
38512018965 ps |
| T870 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2209819472 |
|
|
Apr 15 12:42:12 PM PDT 24 |
Apr 15 12:42:17 PM PDT 24 |
1460664719 ps |
| T871 |
/workspace/coverage/default/9.sram_ctrl_regwen.3288034613 |
|
|
Apr 15 12:42:03 PM PDT 24 |
Apr 15 12:53:26 PM PDT 24 |
5264752762 ps |
| T872 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.3793530781 |
|
|
Apr 15 12:45:51 PM PDT 24 |
Apr 15 12:46:27 PM PDT 24 |
1694249730 ps |
| T873 |
/workspace/coverage/default/13.sram_ctrl_executable.2335517283 |
|
|
Apr 15 12:42:20 PM PDT 24 |
Apr 15 12:47:14 PM PDT 24 |
4827175393 ps |
| T874 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.3838320216 |
|
|
Apr 15 12:44:16 PM PDT 24 |
Apr 15 12:55:40 PM PDT 24 |
75286492436 ps |
| T33 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.2436441668 |
|
|
Apr 15 12:41:59 PM PDT 24 |
Apr 15 12:42:03 PM PDT 24 |
380258186 ps |
| T875 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3317659408 |
|
|
Apr 15 12:45:57 PM PDT 24 |
Apr 15 12:47:47 PM PDT 24 |
16022847745 ps |
| T876 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1927095432 |
|
|
Apr 15 12:45:43 PM PDT 24 |
Apr 15 01:07:33 PM PDT 24 |
52276184576 ps |
| T877 |
/workspace/coverage/default/5.sram_ctrl_smoke.3400299479 |
|
|
Apr 15 12:41:50 PM PDT 24 |
Apr 15 12:44:03 PM PDT 24 |
473610672 ps |
| T878 |
/workspace/coverage/default/25.sram_ctrl_stress_all.470860931 |
|
|
Apr 15 12:42:58 PM PDT 24 |
Apr 15 01:30:53 PM PDT 24 |
22875188305 ps |
| T879 |
/workspace/coverage/default/36.sram_ctrl_alert_test.760745345 |
|
|
Apr 15 12:44:12 PM PDT 24 |
Apr 15 12:44:13 PM PDT 24 |
43384885 ps |
| T880 |
/workspace/coverage/default/2.sram_ctrl_executable.435719142 |
|
|
Apr 15 12:41:39 PM PDT 24 |
Apr 15 12:55:31 PM PDT 24 |
32927068610 ps |
| T881 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2910684226 |
|
|
Apr 15 12:45:05 PM PDT 24 |
Apr 15 12:50:36 PM PDT 24 |
14284491720 ps |
| T882 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.379982113 |
|
|
Apr 15 12:42:19 PM PDT 24 |
Apr 15 12:46:23 PM PDT 24 |
10830427979 ps |
| T883 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1811724680 |
|
|
Apr 15 12:45:14 PM PDT 24 |
Apr 15 12:46:27 PM PDT 24 |
3025798195 ps |
| T884 |
/workspace/coverage/default/9.sram_ctrl_executable.2211431810 |
|
|
Apr 15 12:42:06 PM PDT 24 |
Apr 15 12:45:13 PM PDT 24 |
24942253859 ps |
| T885 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.3632599206 |
|
|
Apr 15 12:43:47 PM PDT 24 |
Apr 15 12:49:05 PM PDT 24 |
35775076067 ps |
| T886 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.2712340414 |
|
|
Apr 15 12:43:41 PM PDT 24 |
Apr 15 12:44:06 PM PDT 24 |
13854216686 ps |
| T887 |
/workspace/coverage/default/42.sram_ctrl_smoke.1034299031 |
|
|
Apr 15 12:44:50 PM PDT 24 |
Apr 15 12:46:22 PM PDT 24 |
1531373570 ps |
| T888 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.580082368 |
|
|
Apr 15 12:41:52 PM PDT 24 |
Apr 15 12:42:13 PM PDT 24 |
1466602628 ps |
| T889 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1302682437 |
|
|
Apr 15 12:45:08 PM PDT 24 |
Apr 15 12:47:15 PM PDT 24 |
6510993661 ps |
| T890 |
/workspace/coverage/default/20.sram_ctrl_executable.3518839952 |
|
|
Apr 15 12:42:37 PM PDT 24 |
Apr 15 01:09:25 PM PDT 24 |
22609164001 ps |
| T891 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.3779907546 |
|
|
Apr 15 12:43:18 PM PDT 24 |
Apr 15 12:56:39 PM PDT 24 |
32989111227 ps |
| T892 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.1166440568 |
|
|
Apr 15 12:42:12 PM PDT 24 |
Apr 15 12:43:51 PM PDT 24 |
795030754 ps |
| T893 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3734084249 |
|
|
Apr 15 12:45:45 PM PDT 24 |
Apr 15 01:51:43 PM PDT 24 |
342327948940 ps |
| T894 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2420205781 |
|
|
Apr 15 12:42:00 PM PDT 24 |
Apr 15 12:43:47 PM PDT 24 |
1635235316 ps |
| T895 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.4286313692 |
|
|
Apr 15 12:41:53 PM PDT 24 |
Apr 15 12:42:55 PM PDT 24 |
3049244689 ps |
| T896 |
/workspace/coverage/default/16.sram_ctrl_alert_test.980167944 |
|
|
Apr 15 12:42:27 PM PDT 24 |
Apr 15 12:42:28 PM PDT 24 |
16629076 ps |
| T897 |
/workspace/coverage/default/9.sram_ctrl_smoke.2970136231 |
|
|
Apr 15 12:42:03 PM PDT 24 |
Apr 15 12:43:58 PM PDT 24 |
5106014647 ps |
| T898 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.417470290 |
|
|
Apr 15 12:41:53 PM PDT 24 |
Apr 15 12:42:56 PM PDT 24 |
945228802 ps |
| T899 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.775394448 |
|
|
Apr 15 12:43:21 PM PDT 24 |
Apr 15 12:43:25 PM PDT 24 |
711203322 ps |
| T900 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.585144206 |
|
|
Apr 15 12:42:50 PM PDT 24 |
Apr 15 12:42:54 PM PDT 24 |
358462925 ps |
| T901 |
/workspace/coverage/default/14.sram_ctrl_bijection.1010834559 |
|
|
Apr 15 12:42:25 PM PDT 24 |
Apr 15 01:16:04 PM PDT 24 |
29187766117 ps |
| T902 |
/workspace/coverage/default/3.sram_ctrl_alert_test.2558426371 |
|
|
Apr 15 12:41:43 PM PDT 24 |
Apr 15 12:41:45 PM PDT 24 |
35087271 ps |
| T903 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1363704715 |
|
|
Apr 15 12:42:42 PM PDT 24 |
Apr 15 12:49:04 PM PDT 24 |
28558107310 ps |
| T904 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.78790068 |
|
|
Apr 15 12:44:02 PM PDT 24 |
Apr 15 12:46:04 PM PDT 24 |
6219966412 ps |
| T905 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.4023114523 |
|
|
Apr 15 12:41:08 PM PDT 24 |
Apr 15 12:43:22 PM PDT 24 |
9515305030 ps |
| T906 |
/workspace/coverage/default/12.sram_ctrl_alert_test.2054941969 |
|
|
Apr 15 12:42:18 PM PDT 24 |
Apr 15 12:42:19 PM PDT 24 |
26673338 ps |
| T907 |
/workspace/coverage/default/21.sram_ctrl_regwen.1407986680 |
|
|
Apr 15 12:42:42 PM PDT 24 |
Apr 15 12:54:48 PM PDT 24 |
12892261229 ps |
| T908 |
/workspace/coverage/default/32.sram_ctrl_alert_test.1199889405 |
|
|
Apr 15 12:43:32 PM PDT 24 |
Apr 15 12:43:33 PM PDT 24 |
24501632 ps |
| T909 |
/workspace/coverage/default/25.sram_ctrl_regwen.3457068705 |
|
|
Apr 15 12:42:46 PM PDT 24 |
Apr 15 12:52:41 PM PDT 24 |
28397400531 ps |
| T910 |
/workspace/coverage/default/23.sram_ctrl_bijection.1862048509 |
|
|
Apr 15 12:42:41 PM PDT 24 |
Apr 15 01:08:36 PM PDT 24 |
94324913808 ps |
| T911 |
/workspace/coverage/default/36.sram_ctrl_bijection.3941642383 |
|
|
Apr 15 12:44:07 PM PDT 24 |
Apr 15 01:12:18 PM PDT 24 |
371748382296 ps |
| T912 |
/workspace/coverage/default/32.sram_ctrl_regwen.4058514784 |
|
|
Apr 15 12:43:33 PM PDT 24 |
Apr 15 01:00:05 PM PDT 24 |
6559625401 ps |
| T913 |
/workspace/coverage/default/38.sram_ctrl_alert_test.2787120004 |
|
|
Apr 15 12:44:27 PM PDT 24 |
Apr 15 12:44:28 PM PDT 24 |
49797881 ps |
| T914 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.109646492 |
|
|
Apr 15 12:43:31 PM PDT 24 |
Apr 15 12:43:35 PM PDT 24 |
1612084439 ps |
| T915 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1531588661 |
|
|
Apr 15 12:42:05 PM PDT 24 |
Apr 15 12:53:11 PM PDT 24 |
11323322116 ps |
| T916 |
/workspace/coverage/default/26.sram_ctrl_alert_test.4137517465 |
|
|
Apr 15 12:42:57 PM PDT 24 |
Apr 15 12:42:59 PM PDT 24 |
27738077 ps |
| T917 |
/workspace/coverage/default/20.sram_ctrl_partial_access.1000594184 |
|
|
Apr 15 12:42:39 PM PDT 24 |
Apr 15 12:42:44 PM PDT 24 |
371302364 ps |
| T918 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.1921680372 |
|
|
Apr 15 12:42:48 PM PDT 24 |
Apr 15 12:44:02 PM PDT 24 |
2349659352 ps |
| T919 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2216961918 |
|
|
Apr 15 12:45:54 PM PDT 24 |
Apr 15 12:50:51 PM PDT 24 |
4184922048 ps |
| T920 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.1630181711 |
|
|
Apr 15 12:43:17 PM PDT 24 |
Apr 15 12:45:21 PM PDT 24 |
8226478734 ps |
| T921 |
/workspace/coverage/default/19.sram_ctrl_stress_all.2032512430 |
|
|
Apr 15 12:42:37 PM PDT 24 |
Apr 15 01:53:46 PM PDT 24 |
296983446110 ps |
| T922 |
/workspace/coverage/default/30.sram_ctrl_alert_test.1654707686 |
|
|
Apr 15 12:43:23 PM PDT 24 |
Apr 15 12:43:24 PM PDT 24 |
14747451 ps |
| T923 |
/workspace/coverage/default/25.sram_ctrl_smoke.2599679656 |
|
|
Apr 15 12:42:48 PM PDT 24 |
Apr 15 12:42:56 PM PDT 24 |
778083761 ps |
| T924 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1003318208 |
|
|
Apr 15 12:41:58 PM PDT 24 |
Apr 15 12:57:58 PM PDT 24 |
28569682304 ps |
| T925 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3339202617 |
|
|
Apr 15 12:42:37 PM PDT 24 |
Apr 15 12:48:20 PM PDT 24 |
5677897458 ps |
| T926 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.3153249647 |
|
|
Apr 15 12:42:23 PM PDT 24 |
Apr 15 01:04:38 PM PDT 24 |
23008753610 ps |
| T927 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.821443357 |
|
|
Apr 15 12:45:00 PM PDT 24 |
Apr 15 12:47:35 PM PDT 24 |
17420689664 ps |
| T34 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.309505469 |
|
|
Apr 15 12:41:18 PM PDT 24 |
Apr 15 12:41:21 PM PDT 24 |
630221304 ps |
| T928 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.3314219930 |
|
|
Apr 15 12:42:30 PM PDT 24 |
Apr 15 12:45:34 PM PDT 24 |
85918995765 ps |
| T929 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3024131934 |
|
|
Apr 15 12:42:33 PM PDT 24 |
Apr 15 12:44:12 PM PDT 24 |
7598769407 ps |
| T930 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.3328192078 |
|
|
Apr 15 12:44:44 PM PDT 24 |
Apr 15 12:44:48 PM PDT 24 |
1349897863 ps |
| T931 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3737751281 |
|
|
Apr 15 12:45:04 PM PDT 24 |
Apr 15 12:46:04 PM PDT 24 |
1712869109 ps |
| T932 |
/workspace/coverage/default/41.sram_ctrl_smoke.54363194 |
|
|
Apr 15 12:44:41 PM PDT 24 |
Apr 15 12:46:04 PM PDT 24 |
3329831872 ps |
| T933 |
/workspace/coverage/default/4.sram_ctrl_regwen.3226216995 |
|
|
Apr 15 12:41:59 PM PDT 24 |
Apr 15 12:44:58 PM PDT 24 |
1778587091 ps |
| T934 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3173259471 |
|
|
Apr 15 12:43:48 PM PDT 24 |
Apr 15 12:43:56 PM PDT 24 |
497188103 ps |
| T935 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3727160800 |
|
|
Apr 15 12:42:27 PM PDT 24 |
Apr 15 12:43:40 PM PDT 24 |
2666584766 ps |
| T936 |
/workspace/coverage/default/3.sram_ctrl_bijection.693089961 |
|
|
Apr 15 12:41:56 PM PDT 24 |
Apr 15 12:53:51 PM PDT 24 |
45019687705 ps |
| T937 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1041489695 |
|
|
Apr 15 12:42:44 PM PDT 24 |
Apr 15 12:43:20 PM PDT 24 |
8127695202 ps |
| T938 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.3911759796 |
|
|
Apr 15 12:43:53 PM PDT 24 |
Apr 15 12:48:55 PM PDT 24 |
65552613782 ps |
| T939 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.140616238 |
|
|
Apr 15 12:43:21 PM PDT 24 |
Apr 15 12:44:24 PM PDT 24 |
4128700855 ps |
| T940 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2693360046 |
|
|
Apr 15 12:45:05 PM PDT 24 |
Apr 15 12:58:16 PM PDT 24 |
64939587081 ps |
| T941 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.819284653 |
|
|
Apr 15 12:42:30 PM PDT 24 |
Apr 15 12:42:34 PM PDT 24 |
400064613 ps |
| T942 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.337474440 |
|
|
Apr 15 12:42:24 PM PDT 24 |
Apr 15 12:44:52 PM PDT 24 |
9318524634 ps |
| T95 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2719877202 |
|
|
Apr 15 12:19:58 PM PDT 24 |
Apr 15 12:20:00 PM PDT 24 |
67439390 ps |
| T943 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1662767921 |
|
|
Apr 15 12:20:09 PM PDT 24 |
Apr 15 12:20:14 PM PDT 24 |
39744461 ps |
| T99 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1712357758 |
|
|
Apr 15 12:20:09 PM PDT 24 |
Apr 15 12:20:13 PM PDT 24 |
920513907 ps |
| T56 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.550185474 |
|
|
Apr 15 12:20:10 PM PDT 24 |
Apr 15 12:20:41 PM PDT 24 |
7695945055 ps |
| T57 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.209839774 |
|
|
Apr 15 12:20:05 PM PDT 24 |
Apr 15 12:20:07 PM PDT 24 |
15880849 ps |
| T944 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1072700172 |
|
|
Apr 15 12:19:58 PM PDT 24 |
Apr 15 12:20:02 PM PDT 24 |
719283654 ps |
| T58 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1151276082 |
|
|
Apr 15 12:20:09 PM PDT 24 |
Apr 15 12:20:38 PM PDT 24 |
3793919756 ps |
| T945 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4168431063 |
|
|
Apr 15 12:20:11 PM PDT 24 |
Apr 15 12:20:15 PM PDT 24 |
730771124 ps |
| T946 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2362173656 |
|
|
Apr 15 12:20:08 PM PDT 24 |
Apr 15 12:20:12 PM PDT 24 |
172432355 ps |
| T947 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1106286197 |
|
|
Apr 15 12:20:05 PM PDT 24 |
Apr 15 12:20:09 PM PDT 24 |
134026432 ps |
| T100 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.435879141 |
|
|
Apr 15 12:20:10 PM PDT 24 |
Apr 15 12:20:14 PM PDT 24 |
198229874 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.678863850 |
|
|
Apr 15 12:19:51 PM PDT 24 |
Apr 15 12:19:55 PM PDT 24 |
21184456 ps |
| T948 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3352103873 |
|
|
Apr 15 12:20:12 PM PDT 24 |
Apr 15 12:20:18 PM PDT 24 |
364916065 ps |
| T949 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1021370525 |
|
|
Apr 15 12:20:01 PM PDT 24 |
Apr 15 12:20:05 PM PDT 24 |
1413975250 ps |
| T59 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3562889037 |
|
|
Apr 15 12:20:07 PM PDT 24 |
Apr 15 12:20:09 PM PDT 24 |
51553922 ps |
| T86 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1474153424 |
|
|
Apr 15 12:20:02 PM PDT 24 |
Apr 15 12:20:04 PM PDT 24 |
33505541 ps |
| T97 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3312837640 |
|
|
Apr 15 12:19:49 PM PDT 24 |
Apr 15 12:19:52 PM PDT 24 |
24848737 ps |
| T101 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.72172335 |
|
|
Apr 15 12:19:48 PM PDT 24 |
Apr 15 12:19:50 PM PDT 24 |
170725393 ps |
| T87 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1404171445 |
|
|
Apr 15 12:20:05 PM PDT 24 |
Apr 15 12:20:07 PM PDT 24 |
80423957 ps |
| T60 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.655808395 |
|
|
Apr 15 12:20:04 PM PDT 24 |
Apr 15 12:20:06 PM PDT 24 |
21480573 ps |
| T88 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1965234042 |
|
|
Apr 15 12:19:52 PM PDT 24 |
Apr 15 12:19:56 PM PDT 24 |
44031533 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.237727724 |
|
|
Apr 15 12:20:00 PM PDT 24 |
Apr 15 12:20:05 PM PDT 24 |
311545897 ps |
| T125 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.54639215 |
|
|
Apr 15 12:19:49 PM PDT 24 |
Apr 15 12:19:54 PM PDT 24 |
460524254 ps |
| T61 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2993035606 |
|
|
Apr 15 12:20:09 PM PDT 24 |
Apr 15 12:21:00 PM PDT 24 |
7113569556 ps |
| T62 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4114104447 |
|
|
Apr 15 12:19:52 PM PDT 24 |
Apr 15 12:19:56 PM PDT 24 |
20518885 ps |
| T63 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3914407853 |
|
|
Apr 15 12:20:13 PM PDT 24 |
Apr 15 12:21:03 PM PDT 24 |
7455230603 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2336831794 |
|
|
Apr 15 12:20:06 PM PDT 24 |
Apr 15 12:20:10 PM PDT 24 |
710992226 ps |
| T64 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3369301979 |
|
|
Apr 15 12:20:09 PM PDT 24 |
Apr 15 12:20:11 PM PDT 24 |
37965011 ps |
| T126 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3407922487 |
|
|
Apr 15 12:20:07 PM PDT 24 |
Apr 15 12:20:11 PM PDT 24 |
160427692 ps |
| T952 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.355313665 |
|
|
Apr 15 12:20:00 PM PDT 24 |
Apr 15 12:20:01 PM PDT 24 |
26137088 ps |
| T953 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.633845852 |
|
|
Apr 15 12:20:12 PM PDT 24 |
Apr 15 12:20:15 PM PDT 24 |
165710334 ps |
| T954 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3310696722 |
|
|
Apr 15 12:20:10 PM PDT 24 |
Apr 15 12:20:16 PM PDT 24 |
1463974407 ps |
| T65 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3482158868 |
|
|
Apr 15 12:20:08 PM PDT 24 |
Apr 15 12:20:10 PM PDT 24 |
48182988 ps |
| T955 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2612512938 |
|
|
Apr 15 12:20:03 PM PDT 24 |
Apr 15 12:20:04 PM PDT 24 |
23230412 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.734362262 |
|
|
Apr 15 12:20:20 PM PDT 24 |
Apr 15 12:20:21 PM PDT 24 |
40985459 ps |
| T957 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1864496674 |
|
|
Apr 15 12:20:03 PM PDT 24 |
Apr 15 12:20:08 PM PDT 24 |
179493748 ps |
| T69 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1142896245 |
|
|
Apr 15 12:20:07 PM PDT 24 |
Apr 15 12:20:36 PM PDT 24 |
3784186362 ps |
| T958 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3448741564 |
|
|
Apr 15 12:20:09 PM PDT 24 |
Apr 15 12:20:13 PM PDT 24 |
22807626 ps |
| T959 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1970158559 |
|
|
Apr 15 12:19:48 PM PDT 24 |
Apr 15 12:19:55 PM PDT 24 |
138435153 ps |
| T70 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.246735083 |
|
|
Apr 15 12:19:54 PM PDT 24 |
Apr 15 12:19:57 PM PDT 24 |
21252140 ps |
| T960 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3643641881 |
|
|
Apr 15 12:20:09 PM PDT 24 |
Apr 15 12:20:11 PM PDT 24 |
12854707 ps |
| T961 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3242259059 |
|
|
Apr 15 12:19:50 PM PDT 24 |
Apr 15 12:19:56 PM PDT 24 |
367051424 ps |
| T962 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1994080613 |
|
|
Apr 15 12:20:03 PM PDT 24 |
Apr 15 12:20:04 PM PDT 24 |
36011251 ps |
| T963 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2324210894 |
|
|
Apr 15 12:20:11 PM PDT 24 |
Apr 15 12:20:40 PM PDT 24 |
17665896116 ps |
| T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.914797823 |
|
|
Apr 15 12:20:04 PM PDT 24 |
Apr 15 12:20:06 PM PDT 24 |
99401613 ps |
| T71 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2141388643 |
|
|
Apr 15 12:20:09 PM PDT 24 |
Apr 15 12:21:04 PM PDT 24 |
28305617431 ps |
| T965 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.787382596 |
|
|
Apr 15 12:20:05 PM PDT 24 |
Apr 15 12:20:07 PM PDT 24 |
61563219 ps |
| T72 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1128079489 |
|
|
Apr 15 12:19:59 PM PDT 24 |
Apr 15 12:20:27 PM PDT 24 |
7559556415 ps |
| T966 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1511612168 |
|
|
Apr 15 12:19:52 PM PDT 24 |
Apr 15 12:19:56 PM PDT 24 |
40118822 ps |
| T967 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.175161072 |
|
|
Apr 15 12:20:03 PM PDT 24 |
Apr 15 12:20:05 PM PDT 24 |
91245337 ps |
| T968 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2674909510 |
|
|
Apr 15 12:20:15 PM PDT 24 |
Apr 15 12:20:17 PM PDT 24 |
37487251 ps |
| T969 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2107101933 |
|
|
Apr 15 12:19:59 PM PDT 24 |
Apr 15 12:20:00 PM PDT 24 |
43521711 ps |
| T970 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1723447898 |
|
|
Apr 15 12:19:55 PM PDT 24 |
Apr 15 12:20:00 PM PDT 24 |
2282722536 ps |
| T971 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1223198762 |
|
|
Apr 15 12:20:13 PM PDT 24 |
Apr 15 12:20:15 PM PDT 24 |
70533452 ps |
| T972 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.12729563 |
|
|
Apr 15 12:20:05 PM PDT 24 |
Apr 15 12:20:07 PM PDT 24 |
32448195 ps |
| T973 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2950890414 |
|
|
Apr 15 12:20:15 PM PDT 24 |
Apr 15 12:20:19 PM PDT 24 |
762755209 ps |
| T128 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1448594290 |
|
|
Apr 15 12:20:02 PM PDT 24 |
Apr 15 12:20:05 PM PDT 24 |
186190077 ps |
| T974 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2110200462 |
|
|
Apr 15 12:20:20 PM PDT 24 |
Apr 15 12:20:23 PM PDT 24 |
63807500 ps |
| T975 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2967270163 |
|
|
Apr 15 12:20:03 PM PDT 24 |
Apr 15 12:20:08 PM PDT 24 |
3541923488 ps |
| T73 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4040520709 |
|
|
Apr 15 12:19:53 PM PDT 24 |
Apr 15 12:19:57 PM PDT 24 |
24859144 ps |
| T976 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.558842831 |
|
|
Apr 15 12:20:04 PM PDT 24 |
Apr 15 12:20:08 PM PDT 24 |
363630325 ps |
| T977 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3793952513 |
|
|
Apr 15 12:20:10 PM PDT 24 |
Apr 15 12:20:16 PM PDT 24 |
746696729 ps |
| T74 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1432638779 |
|
|
Apr 15 12:19:59 PM PDT 24 |
Apr 15 12:20:01 PM PDT 24 |
12893531 ps |
| T978 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1074483840 |
|
|
Apr 15 12:20:00 PM PDT 24 |
Apr 15 12:20:01 PM PDT 24 |
41928379 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2945022039 |
|
|
Apr 15 12:20:09 PM PDT 24 |
Apr 15 12:20:12 PM PDT 24 |
157552740 ps |
| T980 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2173333900 |
|
|
Apr 15 12:19:53 PM PDT 24 |
Apr 15 12:19:57 PM PDT 24 |
21054831 ps |
| T981 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.278486117 |
|
|
Apr 15 12:20:03 PM PDT 24 |
Apr 15 12:20:04 PM PDT 24 |
24172766 ps |
| T127 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2169573739 |
|
|
Apr 15 12:19:58 PM PDT 24 |
Apr 15 12:20:01 PM PDT 24 |
697418992 ps |
| T75 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.897314684 |
|
|
Apr 15 12:19:49 PM PDT 24 |
Apr 15 12:19:52 PM PDT 24 |
44208005 ps |
| T982 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.735835575 |
|
|
Apr 15 12:20:00 PM PDT 24 |
Apr 15 12:20:01 PM PDT 24 |
12793178 ps |
| T82 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1384803724 |
|
|
Apr 15 12:20:02 PM PDT 24 |
Apr 15 12:20:28 PM PDT 24 |
3753204354 ps |
| T122 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2798898577 |
|
|
Apr 15 12:20:06 PM PDT 24 |
Apr 15 12:20:09 PM PDT 24 |
236077499 ps |
| T983 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.882502379 |
|
|
Apr 15 12:20:13 PM PDT 24 |
Apr 15 12:20:17 PM PDT 24 |
1648875878 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2248682533 |
|
|
Apr 15 12:19:46 PM PDT 24 |
Apr 15 12:19:47 PM PDT 24 |
52871613 ps |
| T985 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3883965624 |
|
|
Apr 15 12:20:00 PM PDT 24 |
Apr 15 12:20:01 PM PDT 24 |
18289768 ps |
| T986 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.124866475 |
|
|
Apr 15 12:19:47 PM PDT 24 |
Apr 15 12:19:52 PM PDT 24 |
64856956 ps |
| T987 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.679482688 |
|
|
Apr 15 12:19:50 PM PDT 24 |
Apr 15 12:19:54 PM PDT 24 |
663962338 ps |
| T988 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2659601372 |
|
|
Apr 15 12:20:12 PM PDT 24 |
Apr 15 12:20:15 PM PDT 24 |
24586169 ps |
| T989 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2009827130 |
|
|
Apr 15 12:20:10 PM PDT 24 |
Apr 15 12:20:13 PM PDT 24 |
13136101 ps |
| T990 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.886644662 |
|
|
Apr 15 12:19:54 PM PDT 24 |
Apr 15 12:19:59 PM PDT 24 |
26880701 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.253136635 |
|
|
Apr 15 12:19:53 PM PDT 24 |
Apr 15 12:19:57 PM PDT 24 |
29018660 ps |
| T123 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3051775164 |
|
|
Apr 15 12:20:12 PM PDT 24 |
Apr 15 12:20:16 PM PDT 24 |
1063156819 ps |
| T992 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.78587893 |
|
|
Apr 15 12:20:08 PM PDT 24 |
Apr 15 12:20:13 PM PDT 24 |
1613860146 ps |
| T81 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.791411573 |
|
|
Apr 15 12:20:07 PM PDT 24 |
Apr 15 12:21:02 PM PDT 24 |
41457159532 ps |
| T993 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2458662603 |
|
|
Apr 15 12:19:50 PM PDT 24 |
Apr 15 12:19:53 PM PDT 24 |
65479834 ps |
| T129 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2055717474 |
|
|
Apr 15 12:20:00 PM PDT 24 |
Apr 15 12:20:02 PM PDT 24 |
433151983 ps |
| T994 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1965279631 |
|
|
Apr 15 12:20:07 PM PDT 24 |
Apr 15 12:20:12 PM PDT 24 |
373489055 ps |
| T995 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.701744058 |
|
|
Apr 15 12:20:05 PM PDT 24 |
Apr 15 12:20:06 PM PDT 24 |
15833554 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.396047818 |
|
|
Apr 15 12:20:03 PM PDT 24 |
Apr 15 12:20:04 PM PDT 24 |
23531847 ps |
| T997 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.805205247 |
|
|
Apr 15 12:20:02 PM PDT 24 |
Apr 15 12:20:04 PM PDT 24 |
240438696 ps |
| T83 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.700615858 |
|
|
Apr 15 12:20:01 PM PDT 24 |
Apr 15 12:21:03 PM PDT 24 |
29388677425 ps |
| T84 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1594989249 |
|
|
Apr 15 12:19:54 PM PDT 24 |
Apr 15 12:20:23 PM PDT 24 |
7372064719 ps |
| T998 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.306579347 |
|
|
Apr 15 12:20:06 PM PDT 24 |
Apr 15 12:20:09 PM PDT 24 |
65306214 ps |
| T999 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1293755337 |
|
|
Apr 15 12:19:48 PM PDT 24 |
Apr 15 12:19:51 PM PDT 24 |
44904968 ps |
| T1000 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3361571629 |
|
|
Apr 15 12:20:19 PM PDT 24 |
Apr 15 12:20:23 PM PDT 24 |
726680709 ps |
| T130 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4264034521 |
|
|
Apr 15 12:19:58 PM PDT 24 |
Apr 15 12:20:01 PM PDT 24 |
189986710 ps |
| T1001 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1109482777 |
|
|
Apr 15 12:20:04 PM PDT 24 |
Apr 15 12:20:05 PM PDT 24 |
19648144 ps |
| T1002 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3482685415 |
|
|
Apr 15 12:20:09 PM PDT 24 |
Apr 15 12:20:14 PM PDT 24 |
690168334 ps |
| T1003 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1143235793 |
|
|
Apr 15 12:20:15 PM PDT 24 |
Apr 15 12:20:17 PM PDT 24 |
49516502 ps |