Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	347054116	1			T1	4584		T3	5434		T4	19076
instr_valid_dis	306569367	1			T1	4584		T3	5434		T4	19076
instr_en	30251924	1			T10	68298		T6	292196		T14	39384

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	15731682	1			T10	10420		T6	59478		T14	167320
sram_ifetch_valid_disable	300376455	1			T1	4584		T3	5434		T4	19076
sram_ifetch_enable	30945979	1			T10	165944		T6	100392		T14	102532

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	347054116	1			T1	4584		T3	5434		T4	19076
hw_debug_en_valid_off	301914285	1			T1	4584		T3	5434		T4	19076
hw_debug_en_on	31778196	1			T10	10420		T6	160690		T14	101350

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	300376455	1			T1	4584		T3	5434		T4	19076
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	283558284	1			T1	4584		T3	5434		T4	19076
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13367468	1			T6	187034		T28	164128		T22	71636
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4593626	1			T6	36874		T14	102950		T28	27252
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1773726	1			T14	87704		T96	67384		T22	13996
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1813982	1			T6	36874		T14	15246		T28	27252
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	9218368	1			T10	10420		T6	20000		T14	64370
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	6705638	1			T14	52768		T96	141656		T127	11440
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1679146	1			T10	10420		T6	20000		T14	11602
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	12227692	1			T6	125346		T28	18234		T96	55156
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5357588	1			T96	55156		T22	100416		T125	146090
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5594072	1			T6	125346		T28	18234		T22	64390

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12489678	1			T10	57878		T6	45684		T14	12536
lc_exec_en	10332136	1			T6	15344		T14	36980		T28	94762
valid_exec_dis	297719334	1			T1	4584		T3	5434		T4	19076
invalid_exec_dis	46677661	1			T10	176364		T6	159870		T14	269852