| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2136283966 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3442202372 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1302956092 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4045154127 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2164827552 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1255679753 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3883701696 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3461447691 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3729502956 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1313141903 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1986598546 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1386170924 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2164640805 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2817145504 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.807455707 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.62505871 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.182979676 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3739451352 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1838349075 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1877227942 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3128883504 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2933028765 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.528301009 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2932398814 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1878738723 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3627066088 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1366080129 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4031130750 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1066806116 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.210512180 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2479572221 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2282174146 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2739464120 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2090192010 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1103368830 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.93179420 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2530366210 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3811897308 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2808011614 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.914335982 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.328685749 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.802675718 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.561916733 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3591512208 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3646204815 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2267737316 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.147864373 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.15036154 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2168638156 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.700244220 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2879461610 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2013820221 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2622741405 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3505848198 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3378774916 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2735426877 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3976190812 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1052293730 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.658256039 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2958187625 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3987323999 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4221718743 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2533343906 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3361964190 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1812088076 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3894227352 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3399275106 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.55702924 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1846381881 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2320548067 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3278034952 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1158241507 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1424256726 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1855079858 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2476142279 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1815598293 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2705527794 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3393857467 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1813527542 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2031012235 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.439568766 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.165618293 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2168044665 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2089503222 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3830446568 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.250394259 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1230750545 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2267093412 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3019699997 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.211637565 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1460374179 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2863447940 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1989846726 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2751320044 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2417914993 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4198293228 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3302259469 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.927713222 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2104983151 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1374825838 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3708073226 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.630445898 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2515554034 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.470292497 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1859623576 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3149513896 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.583675337 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4151365695 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1445915854 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2353675101 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2990810252 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1195882140 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.706959818 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2311681764 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1301855465 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2533583308 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1491985032 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2399130511 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2663674595 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.228976713 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1927204210 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.202087919 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.304280263 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.95349519 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4021898462 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4168356086 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.541442490 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.576500861 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1013783225 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2953879240 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1793334888 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3644459791 |
| /workspace/coverage/default/0.sram_ctrl_bijection.2468364557 |
| /workspace/coverage/default/0.sram_ctrl_executable.2459250914 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.71777015 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.51014930 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2065767521 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.3642628664 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.3988275192 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.3608882796 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2708381388 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.1326744229 |
| /workspace/coverage/default/0.sram_ctrl_regwen.470717018 |
| /workspace/coverage/default/0.sram_ctrl_smoke.32070588 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.3419683830 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.93307314 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1661969262 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.17615636 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.1126693835 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.2257483505 |
| /workspace/coverage/default/1.sram_ctrl_bijection.2541681505 |
| /workspace/coverage/default/1.sram_ctrl_executable.4266482891 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.4151735228 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.702865941 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1952267782 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.2009846077 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.4007866437 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.1555655291 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.837537314 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.4204419355 |
| /workspace/coverage/default/1.sram_ctrl_regwen.313279374 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.2610660734 |
| /workspace/coverage/default/1.sram_ctrl_smoke.165382287 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.291995954 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1662113708 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2831088021 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3647286612 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1285302239 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.3469472104 |
| /workspace/coverage/default/10.sram_ctrl_bijection.33883912 |
| /workspace/coverage/default/10.sram_ctrl_executable.3275928766 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.4237218572 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.3562159152 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3476162183 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.338656233 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.1783857817 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.928774029 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1399123746 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.3194368641 |
| /workspace/coverage/default/10.sram_ctrl_regwen.1504471337 |
| /workspace/coverage/default/10.sram_ctrl_smoke.2979908079 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.3949785927 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2253833080 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1436007337 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.698120062 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.422320260 |
| /workspace/coverage/default/11.sram_ctrl_bijection.1948897192 |
| /workspace/coverage/default/11.sram_ctrl_executable.2521270650 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.4187671319 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.1349975000 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1217258164 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.2335126777 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.2698512432 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.3939523435 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2088960836 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.3113584417 |
| /workspace/coverage/default/11.sram_ctrl_regwen.3814029338 |
| /workspace/coverage/default/11.sram_ctrl_smoke.2807046774 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.1216439399 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2283027514 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1989760052 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1139584092 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.4012527701 |
| /workspace/coverage/default/12.sram_ctrl_bijection.2931374314 |
| /workspace/coverage/default/12.sram_ctrl_executable.3006741256 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.3766471778 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.1168958897 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2854305271 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.2117333119 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.2230413783 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.831664558 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1919781815 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.75776480 |
| /workspace/coverage/default/12.sram_ctrl_regwen.790052082 |
| /workspace/coverage/default/12.sram_ctrl_smoke.1715657284 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.3298315956 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1323751323 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3527171097 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3890360971 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2033909500 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.3853322934 |
| /workspace/coverage/default/13.sram_ctrl_bijection.3677632912 |
| /workspace/coverage/default/13.sram_ctrl_executable.2597904964 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.3400824628 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.111889778 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3131854531 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.2148878659 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.105792034 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.2058332508 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2491571452 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.1597136787 |
| /workspace/coverage/default/13.sram_ctrl_regwen.2211297613 |
| /workspace/coverage/default/13.sram_ctrl_smoke.882083483 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.338653889 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2845804483 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3493484456 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2639849537 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2269420725 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.775548616 |
| /workspace/coverage/default/14.sram_ctrl_bijection.2250214490 |
| /workspace/coverage/default/14.sram_ctrl_executable.1498655370 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.1239917201 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.1885681658 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3161830240 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.1150302569 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.3818094492 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.2075432597 |
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| /workspace/coverage/default/42.sram_ctrl_multiple_keys.2869898692 |
| /workspace/coverage/default/42.sram_ctrl_partial_access.2461699554 |
| /workspace/coverage/default/42.sram_ctrl_ram_cfg.345492482 |
| /workspace/coverage/default/42.sram_ctrl_regwen.589475871 |
| /workspace/coverage/default/42.sram_ctrl_smoke.1276737619 |
| /workspace/coverage/default/42.sram_ctrl_stress_all.4251970646 |
| /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2461257158 |
| /workspace/coverage/default/42.sram_ctrl_stress_pipeline.321726738 |
| /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1017500913 |
| /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2430708418 |
| /workspace/coverage/default/43.sram_ctrl_alert_test.154770583 |
| /workspace/coverage/default/43.sram_ctrl_bijection.4029348554 |
| /workspace/coverage/default/43.sram_ctrl_executable.2353272022 |
| /workspace/coverage/default/43.sram_ctrl_lc_escalation.4097275785 |
| /workspace/coverage/default/43.sram_ctrl_max_throughput.2332535404 |
| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.1427537660 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.488083777 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.112555646 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.1734953589 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.209180560 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.2096233073 |
| /workspace/coverage/default/43.sram_ctrl_regwen.3365458006 |
| /workspace/coverage/default/43.sram_ctrl_smoke.2787963599 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.731215412 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.4171438154 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1563255109 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3290947492 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2802843738 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.2710961108 |
| /workspace/coverage/default/44.sram_ctrl_bijection.740888892 |
| /workspace/coverage/default/44.sram_ctrl_executable.3385402986 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.1841051970 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.3196649744 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.984869879 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.3749486662 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.3438938702 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.2324480140 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.320991540 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.3580422061 |
| /workspace/coverage/default/44.sram_ctrl_regwen.521757268 |
| /workspace/coverage/default/44.sram_ctrl_smoke.3933900336 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.330471294 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2756414567 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.553609161 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3345891665 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1602345233 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.2004573942 |
| /workspace/coverage/default/45.sram_ctrl_bijection.1832783575 |
| /workspace/coverage/default/45.sram_ctrl_executable.213592668 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.878727126 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.2033363943 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1616725878 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.957802890 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.3327873092 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.2979907024 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2464144687 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.2067444209 |
| /workspace/coverage/default/45.sram_ctrl_regwen.4009255962 |
| /workspace/coverage/default/45.sram_ctrl_smoke.4043649094 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.885778484 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3477033125 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.473003136 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.215973184 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.4268687982 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.1418366150 |
| /workspace/coverage/default/46.sram_ctrl_bijection.1533055956 |
| /workspace/coverage/default/46.sram_ctrl_executable.224526763 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.577327248 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.620066322 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1570738828 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.2977740007 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.3400349317 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.1453305473 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3409342720 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.3088144945 |
| /workspace/coverage/default/46.sram_ctrl_regwen.979401206 |
| /workspace/coverage/default/46.sram_ctrl_smoke.3665172697 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.785399017 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2417270760 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.4037189587 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2352618280 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1615636225 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.544534180 |
| /workspace/coverage/default/47.sram_ctrl_bijection.286609190 |
| /workspace/coverage/default/47.sram_ctrl_executable.2383499965 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.1847338887 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.3293082114 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3142304269 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.2702620712 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.3586646607 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.2869520254 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1926508659 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.2051215196 |
| /workspace/coverage/default/47.sram_ctrl_regwen.1722661609 |
| /workspace/coverage/default/47.sram_ctrl_smoke.2930166076 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.3342661481 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1067288913 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1873101521 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.432947604 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.4259904250 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.297871903 |
| /workspace/coverage/default/48.sram_ctrl_bijection.3799068681 |
| /workspace/coverage/default/48.sram_ctrl_executable.3404106413 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.2542766459 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.3648657892 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3361824017 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.1103096906 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.2795317097 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.1549463230 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4045934272 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.209220622 |
| /workspace/coverage/default/48.sram_ctrl_regwen.4111671039 |
| /workspace/coverage/default/48.sram_ctrl_smoke.3865463851 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.3443700104 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3666580590 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3635403961 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2739903026 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1427564123 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.1334216779 |
| /workspace/coverage/default/49.sram_ctrl_bijection.1393257054 |
| /workspace/coverage/default/49.sram_ctrl_executable.1254050972 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.946961819 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.3811784966 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3538029195 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.3415863407 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.4191488355 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.2777359876 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2299648645 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.1769290163 |
| /workspace/coverage/default/49.sram_ctrl_regwen.3132962483 |
| /workspace/coverage/default/49.sram_ctrl_smoke.2302215746 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.2077243745 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2743799915 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1405609774 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3492840039 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1987264747 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.2181968643 |
| /workspace/coverage/default/5.sram_ctrl_bijection.3596611771 |
| /workspace/coverage/default/5.sram_ctrl_executable.1427280583 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.3201884922 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.2366327188 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3011748061 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.2949679379 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.1244119737 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.2008749177 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2808097746 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.1830100459 |
| /workspace/coverage/default/5.sram_ctrl_regwen.1520832622 |
| /workspace/coverage/default/5.sram_ctrl_smoke.2838424102 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.1485544468 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.613551277 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2221131458 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1104913937 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3618756740 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.4089458047 |
| /workspace/coverage/default/6.sram_ctrl_bijection.1078362213 |
| /workspace/coverage/default/6.sram_ctrl_executable.1567949607 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.854553188 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.3378953238 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2442485743 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.3176397219 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.3769992917 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.1047485073 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.620492448 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.2677789981 |
| /workspace/coverage/default/6.sram_ctrl_regwen.3215122012 |
| /workspace/coverage/default/6.sram_ctrl_smoke.1448950919 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.2257760263 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4262122523 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.854262375 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1752925270 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.763233328 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.2893462724 |
| /workspace/coverage/default/7.sram_ctrl_bijection.2547846065 |
| /workspace/coverage/default/7.sram_ctrl_executable.1039894088 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.1547790227 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.3666663125 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2802357865 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.1183076052 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.1832857608 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.3691455261 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4100082009 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.3819391292 |
| /workspace/coverage/default/7.sram_ctrl_regwen.769196774 |
| /workspace/coverage/default/7.sram_ctrl_smoke.1058469172 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.3151291579 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1474185748 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.357885162 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1214308333 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2727758280 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.2510976111 |
| /workspace/coverage/default/8.sram_ctrl_executable.1278033713 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.1176526581 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.1036716011 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2780088355 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.1927041405 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.54977508 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.1055272646 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2522769146 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.405104223 |
| /workspace/coverage/default/8.sram_ctrl_regwen.421745485 |
| /workspace/coverage/default/8.sram_ctrl_smoke.3333595485 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.3282210827 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2287771037 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.318265918 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.348155560 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2845191811 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1040412817 |
| /workspace/coverage/default/9.sram_ctrl_bijection.543154370 |
| /workspace/coverage/default/9.sram_ctrl_executable.2813693915 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.1322313941 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.4258840855 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1560928046 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.4067747454 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.1901765471 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.1586114527 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3217661100 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.885604475 |
| /workspace/coverage/default/9.sram_ctrl_regwen.2154730531 |
| /workspace/coverage/default/9.sram_ctrl_smoke.1816262432 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.3191989096 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1038223631 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.870389705 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3126112093 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3974480020 |
|
|
Apr 16 02:12:46 PM PDT 24 |
Apr 16 02:12:58 PM PDT 24 |
817214714 ps |
| T2 |
/workspace/coverage/default/8.sram_ctrl_alert_test.2510976111 |
|
|
Apr 16 02:11:40 PM PDT 24 |
Apr 16 02:11:42 PM PDT 24 |
15393248 ps |
| T3 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.1879006595 |
|
|
Apr 16 02:12:55 PM PDT 24 |
Apr 16 02:13:47 PM PDT 24 |
7759189353 ps |
| T4 |
/workspace/coverage/default/33.sram_ctrl_smoke.431126555 |
|
|
Apr 16 02:14:33 PM PDT 24 |
Apr 16 02:14:51 PM PDT 24 |
1069664550 ps |
| T5 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1047485073 |
|
|
Apr 16 02:11:33 PM PDT 24 |
Apr 16 02:12:02 PM PDT 24 |
4758193711 ps |
| T8 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3361824017 |
|
|
Apr 16 02:16:59 PM PDT 24 |
Apr 16 02:19:35 PM PDT 24 |
5087670854 ps |
| T9 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.209220622 |
|
|
Apr 16 02:16:57 PM PDT 24 |
Apr 16 02:17:01 PM PDT 24 |
712865105 ps |
| T10 |
/workspace/coverage/default/18.sram_ctrl_executable.4258494665 |
|
|
Apr 16 02:12:32 PM PDT 24 |
Apr 16 02:26:36 PM PDT 24 |
10883064257 ps |
| T6 |
/workspace/coverage/default/22.sram_ctrl_stress_all.4185520773 |
|
|
Apr 16 02:13:03 PM PDT 24 |
Apr 16 02:28:02 PM PDT 24 |
30147654335 ps |
| T7 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.4251343598 |
|
|
Apr 16 02:14:33 PM PDT 24 |
Apr 16 02:15:40 PM PDT 24 |
41415799302 ps |
| T11 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.763233328 |
|
|
Apr 16 02:11:38 PM PDT 24 |
Apr 16 02:25:12 PM PDT 24 |
12028800433 ps |
| T12 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.54762328 |
|
|
Apr 16 02:14:52 PM PDT 24 |
Apr 16 02:18:02 PM PDT 24 |
137535023914 ps |
| T13 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.4097275785 |
|
|
Apr 16 02:16:07 PM PDT 24 |
Apr 16 02:16:59 PM PDT 24 |
28460038519 ps |
| T15 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.765789964 |
|
|
Apr 16 02:15:43 PM PDT 24 |
Apr 16 02:53:33 PM PDT 24 |
96212554045 ps |
| T63 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2702620712 |
|
|
Apr 16 02:16:44 PM PDT 24 |
Apr 16 02:18:59 PM PDT 24 |
7185695758 ps |
| T95 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3379854554 |
|
|
Apr 16 02:14:11 PM PDT 24 |
Apr 16 02:14:21 PM PDT 24 |
696343889 ps |
| T40 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2831088021 |
|
|
Apr 16 02:11:22 PM PDT 24 |
Apr 16 02:15:17 PM PDT 24 |
6820742791 ps |
| T81 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3164496749 |
|
|
Apr 16 02:15:03 PM PDT 24 |
Apr 16 02:17:24 PM PDT 24 |
922425432 ps |
| T20 |
/workspace/coverage/default/48.sram_ctrl_alert_test.297871903 |
|
|
Apr 16 02:16:58 PM PDT 24 |
Apr 16 02:17:00 PM PDT 24 |
12489078 ps |
| T82 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.3365731787 |
|
|
Apr 16 02:14:03 PM PDT 24 |
Apr 16 02:19:17 PM PDT 24 |
21531152175 ps |
| T16 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1602345233 |
|
|
Apr 16 02:16:19 PM PDT 24 |
Apr 16 02:51:22 PM PDT 24 |
46549820562 ps |
| T50 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1547790227 |
|
|
Apr 16 02:11:37 PM PDT 24 |
Apr 16 02:12:00 PM PDT 24 |
3263866096 ps |
| T83 |
/workspace/coverage/default/37.sram_ctrl_smoke.2621191345 |
|
|
Apr 16 02:15:02 PM PDT 24 |
Apr 16 02:15:18 PM PDT 24 |
1476533388 ps |
| T14 |
/workspace/coverage/default/36.sram_ctrl_stress_all.3851555068 |
|
|
Apr 16 02:15:02 PM PDT 24 |
Apr 16 03:19:09 PM PDT 24 |
604313279641 ps |
| T84 |
/workspace/coverage/default/38.sram_ctrl_bijection.2555664558 |
|
|
Apr 16 02:15:13 PM PDT 24 |
Apr 16 02:46:07 PM PDT 24 |
391634852900 ps |
| T85 |
/workspace/coverage/default/3.sram_ctrl_smoke.2271104405 |
|
|
Apr 16 02:11:27 PM PDT 24 |
Apr 16 02:11:38 PM PDT 24 |
384975434 ps |
| T89 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2199051011 |
|
|
Apr 16 02:15:54 PM PDT 24 |
Apr 16 02:23:05 PM PDT 24 |
19403793910 ps |
| T69 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1730181741 |
|
|
Apr 16 02:14:45 PM PDT 24 |
Apr 16 02:35:14 PM PDT 24 |
16598675347 ps |
| T51 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3778449634 |
|
|
Apr 16 02:13:10 PM PDT 24 |
Apr 16 02:13:37 PM PDT 24 |
8453850003 ps |
| T130 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.236392851 |
|
|
Apr 16 02:14:32 PM PDT 24 |
Apr 16 02:17:05 PM PDT 24 |
828560361 ps |
| T100 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.2802879276 |
|
|
Apr 16 02:11:23 PM PDT 24 |
Apr 16 02:24:12 PM PDT 24 |
17066874946 ps |
| T25 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.849573068 |
|
|
Apr 16 02:11:51 PM PDT 24 |
Apr 16 02:12:13 PM PDT 24 |
830693296 ps |
| T48 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1084305366 |
|
|
Apr 16 02:14:07 PM PDT 24 |
Apr 16 02:14:30 PM PDT 24 |
731916460 ps |
| T29 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.2953184993 |
|
|
Apr 16 02:15:01 PM PDT 24 |
Apr 16 02:15:05 PM PDT 24 |
1253577471 ps |
| T30 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.353035544 |
|
|
Apr 16 02:11:21 PM PDT 24 |
Apr 16 02:11:25 PM PDT 24 |
1398065756 ps |
| T49 |
/workspace/coverage/default/47.sram_ctrl_bijection.286609190 |
|
|
Apr 16 02:16:39 PM PDT 24 |
Apr 16 03:00:53 PM PDT 24 |
751950459938 ps |
| T17 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.3914130586 |
|
|
Apr 16 02:11:16 PM PDT 24 |
Apr 16 02:11:19 PM PDT 24 |
539406773 ps |
| T33 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2942124217 |
|
|
Apr 16 02:13:58 PM PDT 24 |
Apr 16 02:15:41 PM PDT 24 |
1610861372 ps |
| T34 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.642995489 |
|
|
Apr 16 02:15:16 PM PDT 24 |
Apr 16 02:17:00 PM PDT 24 |
798683836 ps |
| T35 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.203264804 |
|
|
Apr 16 02:12:10 PM PDT 24 |
Apr 16 02:15:47 PM PDT 24 |
6151221613 ps |
| T36 |
/workspace/coverage/default/20.sram_ctrl_partial_access.3353784098 |
|
|
Apr 16 02:12:45 PM PDT 24 |
Apr 16 02:12:56 PM PDT 24 |
710191491 ps |
| T37 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.1748111109 |
|
|
Apr 16 02:12:48 PM PDT 24 |
Apr 16 02:14:24 PM PDT 24 |
755190837 ps |
| T26 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3066506896 |
|
|
Apr 16 02:15:14 PM PDT 24 |
Apr 16 02:16:01 PM PDT 24 |
13255614107 ps |
| T21 |
/workspace/coverage/default/0.sram_ctrl_alert_test.769020772 |
|
|
Apr 16 02:11:20 PM PDT 24 |
Apr 16 02:11:21 PM PDT 24 |
30726818 ps |
| T38 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.902917846 |
|
|
Apr 16 02:11:56 PM PDT 24 |
Apr 16 02:37:13 PM PDT 24 |
16742243522 ps |
| T39 |
/workspace/coverage/default/28.sram_ctrl_alert_test.1877676412 |
|
|
Apr 16 02:13:52 PM PDT 24 |
Apr 16 02:13:54 PM PDT 24 |
13473209 ps |
| T108 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2677789981 |
|
|
Apr 16 02:11:33 PM PDT 24 |
Apr 16 02:11:38 PM PDT 24 |
444555556 ps |
| T109 |
/workspace/coverage/default/36.sram_ctrl_alert_test.70117688 |
|
|
Apr 16 02:15:01 PM PDT 24 |
Apr 16 02:15:02 PM PDT 24 |
48809531 ps |
| T90 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1781851848 |
|
|
Apr 16 02:15:29 PM PDT 24 |
Apr 16 02:23:28 PM PDT 24 |
24150916095 ps |
| T110 |
/workspace/coverage/default/35.sram_ctrl_smoke.2761951365 |
|
|
Apr 16 02:14:46 PM PDT 24 |
Apr 16 02:15:22 PM PDT 24 |
7289839596 ps |
| T28 |
/workspace/coverage/default/48.sram_ctrl_regwen.4111671039 |
|
|
Apr 16 02:16:58 PM PDT 24 |
Apr 16 02:32:54 PM PDT 24 |
10472674953 ps |
| T52 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.4151735228 |
|
|
Apr 16 02:11:22 PM PDT 24 |
Apr 16 02:12:04 PM PDT 24 |
6384300606 ps |
| T131 |
/workspace/coverage/default/7.sram_ctrl_bijection.2547846065 |
|
|
Apr 16 02:11:38 PM PDT 24 |
Apr 16 02:49:11 PM PDT 24 |
478533978232 ps |
| T132 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.1349975000 |
|
|
Apr 16 02:11:51 PM PDT 24 |
Apr 16 02:11:59 PM PDT 24 |
2809472626 ps |
| T133 |
/workspace/coverage/default/4.sram_ctrl_smoke.2860876517 |
|
|
Apr 16 02:11:26 PM PDT 24 |
Apr 16 02:13:50 PM PDT 24 |
1305262212 ps |
| T27 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2287771037 |
|
|
Apr 16 02:11:41 PM PDT 24 |
Apr 16 02:11:52 PM PDT 24 |
285073320 ps |
| T96 |
/workspace/coverage/default/30.sram_ctrl_stress_all.740909937 |
|
|
Apr 16 02:14:06 PM PDT 24 |
Apr 16 02:53:55 PM PDT 24 |
46427951469 ps |
| T91 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1037053636 |
|
|
Apr 16 02:13:58 PM PDT 24 |
Apr 16 02:18:42 PM PDT 24 |
50827835034 ps |
| T134 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.3399395341 |
|
|
Apr 16 02:12:31 PM PDT 24 |
Apr 16 02:13:29 PM PDT 24 |
20153055835 ps |
| T41 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3549679627 |
|
|
Apr 16 02:14:44 PM PDT 24 |
Apr 16 02:14:56 PM PDT 24 |
306861483 ps |
| T135 |
/workspace/coverage/default/28.sram_ctrl_smoke.182611578 |
|
|
Apr 16 02:13:41 PM PDT 24 |
Apr 16 02:14:40 PM PDT 24 |
733642019 ps |
| T136 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.997235049 |
|
|
Apr 16 02:15:24 PM PDT 24 |
Apr 16 02:20:59 PM PDT 24 |
42134932648 ps |
| T42 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.170766453 |
|
|
Apr 16 02:14:29 PM PDT 24 |
Apr 16 02:15:09 PM PDT 24 |
3331696367 ps |
| T92 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.3733365175 |
|
|
Apr 16 02:12:22 PM PDT 24 |
Apr 16 02:16:18 PM PDT 24 |
4198644089 ps |
| T137 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.1551584494 |
|
|
Apr 16 02:15:16 PM PDT 24 |
Apr 16 02:15:20 PM PDT 24 |
1462513022 ps |
| T138 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.2094661875 |
|
|
Apr 16 02:12:21 PM PDT 24 |
Apr 16 02:12:25 PM PDT 24 |
755207211 ps |
| T139 |
/workspace/coverage/default/0.sram_ctrl_bijection.2468364557 |
|
|
Apr 16 02:11:18 PM PDT 24 |
Apr 16 02:38:20 PM PDT 24 |
99737865765 ps |
| T140 |
/workspace/coverage/default/29.sram_ctrl_bijection.2628608287 |
|
|
Apr 16 02:13:56 PM PDT 24 |
Apr 16 02:24:59 PM PDT 24 |
111554305839 ps |
| T141 |
/workspace/coverage/default/18.sram_ctrl_alert_test.3439193491 |
|
|
Apr 16 02:12:32 PM PDT 24 |
Apr 16 02:12:33 PM PDT 24 |
73541254 ps |
| T93 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.209180560 |
|
|
Apr 16 02:16:12 PM PDT 24 |
Apr 16 02:19:48 PM PDT 24 |
9057336334 ps |
| T142 |
/workspace/coverage/default/12.sram_ctrl_alert_test.4012527701 |
|
|
Apr 16 02:11:57 PM PDT 24 |
Apr 16 02:11:59 PM PDT 24 |
21568943 ps |
| T22 |
/workspace/coverage/default/15.sram_ctrl_stress_all.498267407 |
|
|
Apr 16 02:12:13 PM PDT 24 |
Apr 16 03:12:33 PM PDT 24 |
79855509342 ps |
| T143 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2639849537 |
|
|
Apr 16 02:12:03 PM PDT 24 |
Apr 16 02:13:05 PM PDT 24 |
1482188132 ps |
| T144 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.1483801025 |
|
|
Apr 16 02:15:54 PM PDT 24 |
Apr 16 02:16:03 PM PDT 24 |
704295395 ps |
| T145 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.1974897279 |
|
|
Apr 16 02:11:22 PM PDT 24 |
Apr 16 02:13:55 PM PDT 24 |
38291758598 ps |
| T43 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2596651883 |
|
|
Apr 16 02:15:21 PM PDT 24 |
Apr 16 02:15:54 PM PDT 24 |
4111769898 ps |
| T125 |
/workspace/coverage/default/2.sram_ctrl_regwen.335597374 |
|
|
Apr 16 02:11:23 PM PDT 24 |
Apr 16 02:25:11 PM PDT 24 |
33188002414 ps |
| T146 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.3865000119 |
|
|
Apr 16 02:12:46 PM PDT 24 |
Apr 16 02:14:13 PM PDT 24 |
14563641788 ps |
| T147 |
/workspace/coverage/default/36.sram_ctrl_partial_access.1887090687 |
|
|
Apr 16 02:14:57 PM PDT 24 |
Apr 16 02:15:16 PM PDT 24 |
1245227470 ps |
| T148 |
/workspace/coverage/default/0.sram_ctrl_smoke.32070588 |
|
|
Apr 16 02:11:21 PM PDT 24 |
Apr 16 02:11:39 PM PDT 24 |
1064690224 ps |
| T44 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.874748720 |
|
|
Apr 16 02:12:12 PM PDT 24 |
Apr 16 02:12:24 PM PDT 24 |
868966306 ps |
| T149 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1638368492 |
|
|
Apr 16 02:13:17 PM PDT 24 |
Apr 16 02:13:22 PM PDT 24 |
1296193203 ps |
| T150 |
/workspace/coverage/default/48.sram_ctrl_smoke.3865463851 |
|
|
Apr 16 02:16:49 PM PDT 24 |
Apr 16 02:18:15 PM PDT 24 |
763387489 ps |
| T151 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.2872585512 |
|
|
Apr 16 02:14:48 PM PDT 24 |
Apr 16 02:16:56 PM PDT 24 |
8224761103 ps |
| T94 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3635403961 |
|
|
Apr 16 02:16:58 PM PDT 24 |
Apr 16 02:23:04 PM PDT 24 |
23086514343 ps |
| T70 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.1162149915 |
|
|
Apr 16 02:16:02 PM PDT 24 |
Apr 16 02:18:09 PM PDT 24 |
1603968754 ps |
| T152 |
/workspace/coverage/default/10.sram_ctrl_smoke.2979908079 |
|
|
Apr 16 02:11:49 PM PDT 24 |
Apr 16 02:11:54 PM PDT 24 |
1895338877 ps |
| T71 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.1603323869 |
|
|
Apr 16 02:13:19 PM PDT 24 |
Apr 16 02:14:36 PM PDT 24 |
2448209378 ps |
| T126 |
/workspace/coverage/default/6.sram_ctrl_stress_all.2257760263 |
|
|
Apr 16 02:11:42 PM PDT 24 |
Apr 16 03:19:16 PM PDT 24 |
466441223077 ps |
| T153 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.2585064435 |
|
|
Apr 16 02:15:25 PM PDT 24 |
Apr 16 02:15:29 PM PDT 24 |
361379179 ps |
| T72 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2727758280 |
|
|
Apr 16 02:11:41 PM PDT 24 |
Apr 16 02:25:29 PM PDT 24 |
29919006723 ps |
| T154 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.824918790 |
|
|
Apr 16 02:13:22 PM PDT 24 |
Apr 16 02:21:06 PM PDT 24 |
101750373723 ps |
| T127 |
/workspace/coverage/default/48.sram_ctrl_executable.3404106413 |
|
|
Apr 16 02:16:57 PM PDT 24 |
Apr 16 02:25:10 PM PDT 24 |
35066091618 ps |
| T155 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.656040293 |
|
|
Apr 16 02:14:32 PM PDT 24 |
Apr 16 02:40:08 PM PDT 24 |
168730772413 ps |
| T123 |
/workspace/coverage/default/39.sram_ctrl_stress_all.3222717760 |
|
|
Apr 16 02:15:29 PM PDT 24 |
Apr 16 02:57:25 PM PDT 24 |
52343546636 ps |
| T156 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.207063597 |
|
|
Apr 16 02:13:15 PM PDT 24 |
Apr 16 02:15:47 PM PDT 24 |
43069299993 ps |
| T157 |
/workspace/coverage/default/34.sram_ctrl_bijection.940300196 |
|
|
Apr 16 02:14:40 PM PDT 24 |
Apr 16 02:36:46 PM PDT 24 |
304142738822 ps |
| T158 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1919781815 |
|
|
Apr 16 02:11:52 PM PDT 24 |
Apr 16 02:17:41 PM PDT 24 |
26176035636 ps |
| T159 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.3873383999 |
|
|
Apr 16 02:14:03 PM PDT 24 |
Apr 16 02:23:11 PM PDT 24 |
13742479466 ps |
| T160 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3562159152 |
|
|
Apr 16 02:11:45 PM PDT 24 |
Apr 16 02:12:49 PM PDT 24 |
3390403487 ps |
| T161 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.3965834947 |
|
|
Apr 16 02:12:29 PM PDT 24 |
Apr 16 02:18:28 PM PDT 24 |
33707143760 ps |
| T162 |
/workspace/coverage/default/36.sram_ctrl_bijection.65562145 |
|
|
Apr 16 02:15:03 PM PDT 24 |
Apr 16 02:38:24 PM PDT 24 |
331805273717 ps |
| T163 |
/workspace/coverage/default/29.sram_ctrl_executable.3934818771 |
|
|
Apr 16 02:13:58 PM PDT 24 |
Apr 16 02:43:45 PM PDT 24 |
213185807286 ps |
| T164 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3580422061 |
|
|
Apr 16 02:16:17 PM PDT 24 |
Apr 16 02:16:22 PM PDT 24 |
1406642241 ps |
| T165 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.3666663125 |
|
|
Apr 16 02:11:44 PM PDT 24 |
Apr 16 02:11:58 PM PDT 24 |
726074795 ps |
| T73 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1427537660 |
|
|
Apr 16 02:16:15 PM PDT 24 |
Apr 16 02:18:20 PM PDT 24 |
3075799134 ps |
| T166 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2126221436 |
|
|
Apr 16 02:15:50 PM PDT 24 |
Apr 16 02:16:56 PM PDT 24 |
974909169 ps |
| T167 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3251985691 |
|
|
Apr 16 02:13:09 PM PDT 24 |
Apr 16 02:17:30 PM PDT 24 |
43918035728 ps |
| T168 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.54977508 |
|
|
Apr 16 02:11:37 PM PDT 24 |
Apr 16 02:32:42 PM PDT 24 |
165681637511 ps |
| T169 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.1654212065 |
|
|
Apr 16 02:14:43 PM PDT 24 |
Apr 16 02:17:31 PM PDT 24 |
6925652024 ps |
| T45 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1616440205 |
|
|
Apr 16 02:15:03 PM PDT 24 |
Apr 16 02:15:13 PM PDT 24 |
233011458 ps |
| T170 |
/workspace/coverage/default/29.sram_ctrl_stress_all.166054589 |
|
|
Apr 16 02:14:05 PM PDT 24 |
Apr 16 02:49:08 PM PDT 24 |
255700661218 ps |
| T171 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2983133650 |
|
|
Apr 16 02:11:28 PM PDT 24 |
Apr 16 02:17:21 PM PDT 24 |
55538265917 ps |
| T172 |
/workspace/coverage/default/35.sram_ctrl_alert_test.2962590115 |
|
|
Apr 16 02:14:53 PM PDT 24 |
Apr 16 02:14:55 PM PDT 24 |
38101746 ps |
| T173 |
/workspace/coverage/default/43.sram_ctrl_alert_test.154770583 |
|
|
Apr 16 02:16:13 PM PDT 24 |
Apr 16 02:16:14 PM PDT 24 |
19052290 ps |
| T174 |
/workspace/coverage/default/27.sram_ctrl_bijection.2101254039 |
|
|
Apr 16 02:13:37 PM PDT 24 |
Apr 16 02:31:04 PM PDT 24 |
171236624582 ps |
| T175 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1242785721 |
|
|
Apr 16 02:15:15 PM PDT 24 |
Apr 16 02:24:07 PM PDT 24 |
62369362348 ps |
| T176 |
/workspace/coverage/default/32.sram_ctrl_partial_access.2131597465 |
|
|
Apr 16 02:14:21 PM PDT 24 |
Apr 16 02:16:21 PM PDT 24 |
3398549192 ps |
| T177 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.2148878659 |
|
|
Apr 16 02:12:04 PM PDT 24 |
Apr 16 02:17:18 PM PDT 24 |
18625248081 ps |
| T178 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.3259657224 |
|
|
Apr 16 02:14:40 PM PDT 24 |
Apr 16 02:14:44 PM PDT 24 |
344049151 ps |
| T124 |
/workspace/coverage/default/12.sram_ctrl_regwen.790052082 |
|
|
Apr 16 02:11:57 PM PDT 24 |
Apr 16 02:14:54 PM PDT 24 |
5489053263 ps |
| T128 |
/workspace/coverage/default/30.sram_ctrl_executable.1013506310 |
|
|
Apr 16 02:14:09 PM PDT 24 |
Apr 16 02:28:23 PM PDT 24 |
167200802401 ps |
| T129 |
/workspace/coverage/default/11.sram_ctrl_executable.2521270650 |
|
|
Apr 16 02:11:53 PM PDT 24 |
Apr 16 02:27:04 PM PDT 24 |
12213817789 ps |
| T179 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.1879050119 |
|
|
Apr 16 02:13:48 PM PDT 24 |
Apr 16 02:28:03 PM PDT 24 |
89533084384 ps |
| T180 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.1982641876 |
|
|
Apr 16 02:13:30 PM PDT 24 |
Apr 16 02:15:36 PM PDT 24 |
785618507 ps |
| T18 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.3317584724 |
|
|
Apr 16 02:11:28 PM PDT 24 |
Apr 16 02:11:32 PM PDT 24 |
467571451 ps |
| T181 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3259615265 |
|
|
Apr 16 02:14:50 PM PDT 24 |
Apr 16 02:17:23 PM PDT 24 |
20355704956 ps |
| T23 |
/workspace/coverage/default/23.sram_ctrl_stress_all.2403704168 |
|
|
Apr 16 02:13:13 PM PDT 24 |
Apr 16 02:43:06 PM PDT 24 |
133717547469 ps |
| T182 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2244155351 |
|
|
Apr 16 02:14:56 PM PDT 24 |
Apr 16 02:15:33 PM PDT 24 |
2979344523 ps |
| T183 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.4037189587 |
|
|
Apr 16 02:16:22 PM PDT 24 |
Apr 16 02:21:12 PM PDT 24 |
18794603136 ps |
| T184 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.1638591714 |
|
|
Apr 16 02:11:24 PM PDT 24 |
Apr 16 02:11:34 PM PDT 24 |
2850352359 ps |
| T185 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.3422737800 |
|
|
Apr 16 02:13:00 PM PDT 24 |
Apr 16 02:15:48 PM PDT 24 |
79583389024 ps |
| T186 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.722730358 |
|
|
Apr 16 02:13:41 PM PDT 24 |
Apr 16 02:13:45 PM PDT 24 |
1087232352 ps |
| T187 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3482915516 |
|
|
Apr 16 02:14:38 PM PDT 24 |
Apr 16 02:18:01 PM PDT 24 |
17889945171 ps |
| T188 |
/workspace/coverage/default/2.sram_ctrl_alert_test.4043180272 |
|
|
Apr 16 02:11:28 PM PDT 24 |
Apr 16 02:11:30 PM PDT 24 |
14352277 ps |
| T189 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1161974735 |
|
|
Apr 16 02:15:44 PM PDT 24 |
Apr 16 02:16:03 PM PDT 24 |
737804158 ps |
| T190 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3257819570 |
|
|
Apr 16 02:12:57 PM PDT 24 |
Apr 16 02:16:06 PM PDT 24 |
5769368097 ps |
| T191 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.3138967887 |
|
|
Apr 16 02:15:13 PM PDT 24 |
Apr 16 02:15:30 PM PDT 24 |
4686417365 ps |
| T192 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.3085305623 |
|
|
Apr 16 02:14:48 PM PDT 24 |
Apr 16 02:16:32 PM PDT 24 |
85717402236 ps |
| T193 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3170229827 |
|
|
Apr 16 02:14:56 PM PDT 24 |
Apr 16 02:17:52 PM PDT 24 |
6852253515 ps |
| T46 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.4285381217 |
|
|
Apr 16 02:13:43 PM PDT 24 |
Apr 16 02:14:50 PM PDT 24 |
4091103686 ps |
| T194 |
/workspace/coverage/default/24.sram_ctrl_partial_access.3004611756 |
|
|
Apr 16 02:13:22 PM PDT 24 |
Apr 16 02:14:51 PM PDT 24 |
1693778525 ps |
| T24 |
/workspace/coverage/default/30.sram_ctrl_regwen.2895005328 |
|
|
Apr 16 02:14:08 PM PDT 24 |
Apr 16 02:28:48 PM PDT 24 |
55695573345 ps |
| T195 |
/workspace/coverage/default/34.sram_ctrl_alert_test.803720429 |
|
|
Apr 16 02:14:47 PM PDT 24 |
Apr 16 02:14:48 PM PDT 24 |
17331897 ps |
| T196 |
/workspace/coverage/default/17.sram_ctrl_regwen.3120493377 |
|
|
Apr 16 02:12:26 PM PDT 24 |
Apr 16 02:15:39 PM PDT 24 |
21083968494 ps |
| T197 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1405609774 |
|
|
Apr 16 02:17:01 PM PDT 24 |
Apr 16 02:20:32 PM PDT 24 |
3615372549 ps |
| T198 |
/workspace/coverage/default/0.sram_ctrl_executable.2459250914 |
|
|
Apr 16 02:11:15 PM PDT 24 |
Apr 16 02:20:54 PM PDT 24 |
10899171009 ps |
| T199 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2487998582 |
|
|
Apr 16 02:14:25 PM PDT 24 |
Apr 16 02:14:26 PM PDT 24 |
13507771 ps |
| T200 |
/workspace/coverage/default/3.sram_ctrl_alert_test.474852032 |
|
|
Apr 16 02:11:30 PM PDT 24 |
Apr 16 02:11:31 PM PDT 24 |
22861615 ps |
| T201 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3091342948 |
|
|
Apr 16 02:13:38 PM PDT 24 |
Apr 16 02:21:01 PM PDT 24 |
153490412777 ps |
| T202 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.3772824672 |
|
|
Apr 16 02:14:36 PM PDT 24 |
Apr 16 02:15:40 PM PDT 24 |
4092592278 ps |
| T203 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.4051961015 |
|
|
Apr 16 02:15:25 PM PDT 24 |
Apr 16 02:16:24 PM PDT 24 |
787593588 ps |
| T204 |
/workspace/coverage/default/28.sram_ctrl_bijection.91092662 |
|
|
Apr 16 02:13:48 PM PDT 24 |
Apr 16 02:28:06 PM PDT 24 |
77215954687 ps |
| T205 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.3774344012 |
|
|
Apr 16 02:12:09 PM PDT 24 |
Apr 16 02:13:37 PM PDT 24 |
3159386424 ps |
| T206 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.806558113 |
|
|
Apr 16 02:15:12 PM PDT 24 |
Apr 16 02:26:43 PM PDT 24 |
9637785608 ps |
| T207 |
/workspace/coverage/default/26.sram_ctrl_partial_access.3133977348 |
|
|
Apr 16 02:13:28 PM PDT 24 |
Apr 16 02:13:35 PM PDT 24 |
2765064223 ps |
| T208 |
/workspace/coverage/default/15.sram_ctrl_executable.936718322 |
|
|
Apr 16 02:12:13 PM PDT 24 |
Apr 16 02:23:41 PM PDT 24 |
48436554055 ps |
| T209 |
/workspace/coverage/default/29.sram_ctrl_partial_access.3545477442 |
|
|
Apr 16 02:13:58 PM PDT 24 |
Apr 16 02:14:11 PM PDT 24 |
875908761 ps |
| T210 |
/workspace/coverage/default/21.sram_ctrl_executable.1114032974 |
|
|
Apr 16 02:12:55 PM PDT 24 |
Apr 16 02:14:43 PM PDT 24 |
5699280216 ps |
| T211 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.4007866437 |
|
|
Apr 16 02:11:16 PM PDT 24 |
Apr 16 02:36:47 PM PDT 24 |
99002011117 ps |
| T212 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3819391292 |
|
|
Apr 16 02:11:36 PM PDT 24 |
Apr 16 02:11:41 PM PDT 24 |
2097082751 ps |
| T213 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.885604475 |
|
|
Apr 16 02:11:44 PM PDT 24 |
Apr 16 02:11:48 PM PDT 24 |
1401756581 ps |
| T214 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.3718932104 |
|
|
Apr 16 02:12:49 PM PDT 24 |
Apr 16 02:17:39 PM PDT 24 |
14048876284 ps |
| T47 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3410974931 |
|
|
Apr 16 02:11:30 PM PDT 24 |
Apr 16 02:13:22 PM PDT 24 |
1791085596 ps |
| T215 |
/workspace/coverage/default/27.sram_ctrl_partial_access.2479575627 |
|
|
Apr 16 02:13:37 PM PDT 24 |
Apr 16 02:13:54 PM PDT 24 |
1194518522 ps |
| T216 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3808240621 |
|
|
Apr 16 02:12:47 PM PDT 24 |
Apr 16 02:16:14 PM PDT 24 |
12345036627 ps |
| T217 |
/workspace/coverage/default/49.sram_ctrl_smoke.2302215746 |
|
|
Apr 16 02:16:55 PM PDT 24 |
Apr 16 02:19:09 PM PDT 24 |
1809959316 ps |
| T218 |
/workspace/coverage/default/3.sram_ctrl_bijection.3837193631 |
|
|
Apr 16 02:11:28 PM PDT 24 |
Apr 16 02:42:41 PM PDT 24 |
27872523083 ps |
| T219 |
/workspace/coverage/default/12.sram_ctrl_executable.3006741256 |
|
|
Apr 16 02:11:59 PM PDT 24 |
Apr 16 02:16:22 PM PDT 24 |
8945671699 ps |
| T220 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1711979079 |
|
|
Apr 16 02:14:47 PM PDT 24 |
Apr 16 02:20:38 PM PDT 24 |
11917830055 ps |
| T221 |
/workspace/coverage/default/32.sram_ctrl_bijection.1376235471 |
|
|
Apr 16 02:14:23 PM PDT 24 |
Apr 16 02:31:30 PM PDT 24 |
67082008700 ps |
| T222 |
/workspace/coverage/default/38.sram_ctrl_executable.1696154401 |
|
|
Apr 16 02:15:16 PM PDT 24 |
Apr 16 02:32:59 PM PDT 24 |
110812603089 ps |
| T223 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.1447741705 |
|
|
Apr 16 02:13:27 PM PDT 24 |
Apr 16 02:13:50 PM PDT 24 |
1484761290 ps |
| T224 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2430708418 |
|
|
Apr 16 02:16:07 PM PDT 24 |
Apr 16 02:25:57 PM PDT 24 |
18809919382 ps |
| T225 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3208920345 |
|
|
Apr 16 02:11:28 PM PDT 24 |
Apr 16 02:13:25 PM PDT 24 |
11175996179 ps |
| T226 |
/workspace/coverage/default/22.sram_ctrl_regwen.2662343335 |
|
|
Apr 16 02:13:06 PM PDT 24 |
Apr 16 02:24:35 PM PDT 24 |
3034140787 ps |
| T227 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1150302569 |
|
|
Apr 16 02:12:16 PM PDT 24 |
Apr 16 02:14:40 PM PDT 24 |
18624749475 ps |
| T228 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.3558752598 |
|
|
Apr 16 02:15:56 PM PDT 24 |
Apr 16 02:24:11 PM PDT 24 |
32791662210 ps |
| T229 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1239917201 |
|
|
Apr 16 02:12:10 PM PDT 24 |
Apr 16 02:12:44 PM PDT 24 |
8980445206 ps |
| T101 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1474185748 |
|
|
Apr 16 02:11:39 PM PDT 24 |
Apr 16 02:11:44 PM PDT 24 |
113632071 ps |
| T230 |
/workspace/coverage/default/14.sram_ctrl_regwen.3568598085 |
|
|
Apr 16 02:12:10 PM PDT 24 |
Apr 16 02:29:55 PM PDT 24 |
24064235463 ps |
| T231 |
/workspace/coverage/default/10.sram_ctrl_regwen.1504471337 |
|
|
Apr 16 02:11:46 PM PDT 24 |
Apr 16 02:16:03 PM PDT 24 |
2487430394 ps |
| T232 |
/workspace/coverage/default/35.sram_ctrl_regwen.359465109 |
|
|
Apr 16 02:14:54 PM PDT 24 |
Apr 16 02:26:24 PM PDT 24 |
43359428759 ps |
| T233 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.1350521990 |
|
|
Apr 16 02:14:11 PM PDT 24 |
Apr 16 02:32:57 PM PDT 24 |
32074924497 ps |
| T234 |
/workspace/coverage/default/1.sram_ctrl_bijection.2541681505 |
|
|
Apr 16 02:11:21 PM PDT 24 |
Apr 16 02:34:23 PM PDT 24 |
62462665335 ps |
| T235 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1104913937 |
|
|
Apr 16 02:11:40 PM PDT 24 |
Apr 16 02:12:43 PM PDT 24 |
9244636868 ps |
| T236 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.4242734825 |
|
|
Apr 16 02:13:39 PM PDT 24 |
Apr 16 02:20:37 PM PDT 24 |
17301918865 ps |
| T237 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.780461344 |
|
|
Apr 16 02:15:29 PM PDT 24 |
Apr 16 02:17:51 PM PDT 24 |
10194211317 ps |
| T238 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.4245122498 |
|
|
Apr 16 02:15:01 PM PDT 24 |
Apr 16 02:19:52 PM PDT 24 |
22157704069 ps |
| T239 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1849055464 |
|
|
Apr 16 02:15:49 PM PDT 24 |
Apr 16 02:16:32 PM PDT 24 |
1198804658 ps |
| T240 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3217661100 |
|
|
Apr 16 02:11:48 PM PDT 24 |
Apr 16 02:20:47 PM PDT 24 |
135601864373 ps |
| T241 |
/workspace/coverage/default/5.sram_ctrl_regwen.1520832622 |
|
|
Apr 16 02:11:33 PM PDT 24 |
Apr 16 02:23:58 PM PDT 24 |
22965199866 ps |
| T242 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.1702765262 |
|
|
Apr 16 02:15:34 PM PDT 24 |
Apr 16 02:15:38 PM PDT 24 |
705846176 ps |
| T243 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.173040014 |
|
|
Apr 16 02:12:25 PM PDT 24 |
Apr 16 02:38:12 PM PDT 24 |
8707557344 ps |
| T244 |
/workspace/coverage/default/27.sram_ctrl_alert_test.1869016438 |
|
|
Apr 16 02:13:41 PM PDT 24 |
Apr 16 02:13:42 PM PDT 24 |
13628823 ps |
| T245 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2780088355 |
|
|
Apr 16 02:11:48 PM PDT 24 |
Apr 16 02:12:48 PM PDT 24 |
955286884 ps |
| T246 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.837537314 |
|
|
Apr 16 02:11:17 PM PDT 24 |
Apr 16 02:16:00 PM PDT 24 |
11926129344 ps |
| T247 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.291432412 |
|
|
Apr 16 02:11:28 PM PDT 24 |
Apr 16 02:12:45 PM PDT 24 |
44368118684 ps |
| T248 |
/workspace/coverage/default/43.sram_ctrl_partial_access.1734953589 |
|
|
Apr 16 02:16:06 PM PDT 24 |
Apr 16 02:17:10 PM PDT 24 |
5282586255 ps |
| T249 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.3916406799 |
|
|
Apr 16 02:12:27 PM PDT 24 |
Apr 16 02:14:22 PM PDT 24 |
40573852407 ps |
| T250 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3769992917 |
|
|
Apr 16 02:11:31 PM PDT 24 |
Apr 16 02:21:28 PM PDT 24 |
47028769241 ps |
| T251 |
/workspace/coverage/default/24.sram_ctrl_alert_test.818022230 |
|
|
Apr 16 02:13:22 PM PDT 24 |
Apr 16 02:13:24 PM PDT 24 |
61469030 ps |
| T252 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.946961819 |
|
|
Apr 16 02:17:01 PM PDT 24 |
Apr 16 02:18:26 PM PDT 24 |
51162161043 ps |
| T253 |
/workspace/coverage/default/14.sram_ctrl_executable.1498655370 |
|
|
Apr 16 02:12:12 PM PDT 24 |
Apr 16 02:16:22 PM PDT 24 |
9482981480 ps |
| T254 |
/workspace/coverage/default/28.sram_ctrl_regwen.3380673958 |
|
|
Apr 16 02:13:53 PM PDT 24 |
Apr 16 02:30:47 PM PDT 24 |
32490825753 ps |
| T255 |
/workspace/coverage/default/20.sram_ctrl_stress_all.207595679 |
|
|
Apr 16 02:12:49 PM PDT 24 |
Apr 16 03:13:48 PM PDT 24 |
328047705449 ps |
| T256 |
/workspace/coverage/default/46.sram_ctrl_executable.224526763 |
|
|
Apr 16 02:16:32 PM PDT 24 |
Apr 16 02:31:03 PM PDT 24 |
30246265672 ps |
| T257 |
/workspace/coverage/default/38.sram_ctrl_smoke.2892040998 |
|
|
Apr 16 02:15:12 PM PDT 24 |
Apr 16 02:15:31 PM PDT 24 |
3605368051 ps |
| T258 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2051215196 |
|
|
Apr 16 02:16:43 PM PDT 24 |
Apr 16 02:16:47 PM PDT 24 |
1525776629 ps |
| T259 |
/workspace/coverage/default/39.sram_ctrl_executable.3910276036 |
|
|
Apr 16 02:15:26 PM PDT 24 |
Apr 16 02:30:02 PM PDT 24 |
38618350404 ps |
| T260 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3492840039 |
|
|
Apr 16 02:17:04 PM PDT 24 |
Apr 16 02:17:22 PM PDT 24 |
2824448197 ps |
| T261 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.369662680 |
|
|
Apr 16 02:12:37 PM PDT 24 |
Apr 16 02:17:49 PM PDT 24 |
33516326285 ps |
| T19 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.2610660734 |
|
|
Apr 16 02:11:21 PM PDT 24 |
Apr 16 02:11:25 PM PDT 24 |
448428665 ps |
| T262 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2106292392 |
|
|
Apr 16 02:12:52 PM PDT 24 |
Apr 16 02:13:30 PM PDT 24 |
4078509652 ps |
| T263 |
/workspace/coverage/default/40.sram_ctrl_partial_access.226579798 |
|
|
Apr 16 02:15:32 PM PDT 24 |
Apr 16 02:15:38 PM PDT 24 |
688036656 ps |
| T264 |
/workspace/coverage/default/46.sram_ctrl_regwen.979401206 |
|
|
Apr 16 02:16:34 PM PDT 24 |
Apr 16 02:40:13 PM PDT 24 |
3162782581 ps |
| T265 |
/workspace/coverage/default/41.sram_ctrl_regwen.2589868600 |
|
|
Apr 16 02:15:44 PM PDT 24 |
Apr 16 02:31:06 PM PDT 24 |
12152001849 ps |
| T266 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2854305271 |
|
|
Apr 16 02:11:57 PM PDT 24 |
Apr 16 02:14:36 PM PDT 24 |
17525113067 ps |
| T31 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.1096119220 |
|
|
Apr 16 02:11:27 PM PDT 24 |
Apr 16 02:11:31 PM PDT 24 |
971929569 ps |
| T267 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1294884923 |
|
|
Apr 16 02:12:40 PM PDT 24 |
Apr 16 02:14:57 PM PDT 24 |
18021347287 ps |
| T268 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3172090391 |
|
|
Apr 16 02:13:14 PM PDT 24 |
Apr 16 02:15:44 PM PDT 24 |
18077777126 ps |
| T269 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.889024067 |
|
|
Apr 16 02:12:55 PM PDT 24 |
Apr 16 02:12:59 PM PDT 24 |
359468002 ps |
| T270 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.1963725699 |
|
|
Apr 16 02:11:27 PM PDT 24 |
Apr 16 02:11:31 PM PDT 24 |
704810191 ps |
| T102 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.832968515 |
|
|
Apr 16 02:14:04 PM PDT 24 |
Apr 16 02:14:09 PM PDT 24 |
135705064 ps |
| T271 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3345891665 |
|
|
Apr 16 02:16:13 PM PDT 24 |
Apr 16 02:18:12 PM PDT 24 |
4267999698 ps |
| T272 |
/workspace/coverage/default/20.sram_ctrl_executable.1133926028 |
|
|
Apr 16 02:12:53 PM PDT 24 |
Apr 16 02:20:49 PM PDT 24 |
5173487068 ps |
| T273 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.1302582278 |
|
|
Apr 16 02:12:37 PM PDT 24 |
Apr 16 02:27:26 PM PDT 24 |
12897278130 ps |
| T274 |
/workspace/coverage/default/34.sram_ctrl_partial_access.1742352154 |
|
|
Apr 16 02:14:38 PM PDT 24 |
Apr 16 02:14:59 PM PDT 24 |
5638101287 ps |
| T275 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.2033909500 |
|
|
Apr 16 02:12:01 PM PDT 24 |
Apr 16 02:21:45 PM PDT 24 |
22401057666 ps |
| T276 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.1560506813 |
|
|
Apr 16 02:13:52 PM PDT 24 |
Apr 16 02:16:21 PM PDT 24 |
21494221362 ps |
| T277 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2065767521 |
|
|
Apr 16 02:11:16 PM PDT 24 |
Apr 16 02:13:45 PM PDT 24 |
4964399505 ps |
| T278 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.1278687218 |
|
|
Apr 16 02:12:16 PM PDT 24 |
Apr 16 02:17:28 PM PDT 24 |
229306966134 ps |
| T279 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3672330576 |
|
|
Apr 16 02:14:53 PM PDT 24 |
Apr 16 02:15:27 PM PDT 24 |
5756078112 ps |
| T280 |
/workspace/coverage/default/39.sram_ctrl_bijection.171364988 |
|
|
Apr 16 02:15:23 PM PDT 24 |
Apr 16 02:32:00 PM PDT 24 |
25482369017 ps |
| T281 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.93307314 |
|
|
Apr 16 02:11:17 PM PDT 24 |
Apr 16 02:11:28 PM PDT 24 |
793127753 ps |
| T282 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1952267782 |
|
|
Apr 16 02:11:16 PM PDT 24 |
Apr 16 02:13:36 PM PDT 24 |
8920707890 ps |
| T283 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.3691605576 |
|
|
Apr 16 02:15:38 PM PDT 24 |
Apr 16 02:18:04 PM PDT 24 |
2455811579 ps |
| T284 |
/workspace/coverage/default/7.sram_ctrl_smoke.1058469172 |
|
|
Apr 16 02:11:45 PM PDT 24 |
Apr 16 02:11:53 PM PDT 24 |
429781274 ps |
| T285 |
/workspace/coverage/default/30.sram_ctrl_smoke.47350075 |
|
|
Apr 16 02:14:04 PM PDT 24 |
Apr 16 02:14:35 PM PDT 24 |
419009207 ps |
| T286 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3477033125 |
|
|
Apr 16 02:16:26 PM PDT 24 |
Apr 16 02:19:46 PM PDT 24 |
1388288900 ps |
| T287 |
/workspace/coverage/default/17.sram_ctrl_executable.1377355691 |
|
|
Apr 16 02:12:22 PM PDT 24 |
Apr 16 02:31:45 PM PDT 24 |
86196903213 ps |
| T288 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1139584092 |
|
|
Apr 16 02:11:57 PM PDT 24 |
Apr 16 02:17:42 PM PDT 24 |
7587708348 ps |
| T289 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2354333471 |
|
|
Apr 16 02:13:49 PM PDT 24 |
Apr 16 02:15:29 PM PDT 24 |
3141214704 ps |
| T290 |
/workspace/coverage/default/19.sram_ctrl_stress_all.188970586 |
|
|
Apr 16 02:12:39 PM PDT 24 |
Apr 16 03:27:48 PM PDT 24 |
86037506168 ps |
| T291 |
/workspace/coverage/default/33.sram_ctrl_regwen.2720953856 |
|
|
Apr 16 02:14:37 PM PDT 24 |
Apr 16 02:28:42 PM PDT 24 |
27804315614 ps |
| T292 |
/workspace/coverage/default/20.sram_ctrl_bijection.3307985404 |
|
|
Apr 16 02:12:46 PM PDT 24 |
Apr 16 02:30:26 PM PDT 24 |
16927811381 ps |
| T293 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1149655979 |
|
|
Apr 16 02:13:00 PM PDT 24 |
Apr 16 02:19:11 PM PDT 24 |
16326745271 ps |
| T294 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.4006460060 |
|
|
Apr 16 02:14:03 PM PDT 24 |
Apr 16 02:15:25 PM PDT 24 |
52935622088 ps |
| T295 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.3251244362 |
|
|
Apr 16 02:11:29 PM PDT 24 |
Apr 16 02:26:56 PM PDT 24 |
74263057361 ps |
| T296 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1588372018 |
|
|
Apr 16 02:13:20 PM PDT 24 |
Apr 16 02:14:16 PM PDT 24 |
1990635858 ps |