Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	144473375	1			T1	1890		T3	173		T4	8647
triple_byte_access	2770125	1			T1	81		T4	173		T5	1562
halfword_access	4260104	1			T1	118		T3	5		T4	297
byte_access	5972673	1			T1	169		T3	3		T4	341
zero_access	1821365	1			T1	34		T4	80		T5	808

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79362855

1

T1

1125

T3

85

T4

4869

auto[1]

79934787

1

T1

1167

T3

96

T4

4669

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	71815621	1			T1	932		T3	80		T4	4396
auto[0]	triple_byte_access	1313925	1			T1	37		T4	91		T5	735
auto[0]	halfword_access	2077134	1			T1	64		T3	3		T4	148
auto[0]	byte_access	3060247	1			T1	72		T3	2		T4	190
auto[0]	zero_access	1095928	1			T1	20		T4	44		T5	421
auto[1]	word_access	72657754	1			T1	958		T3	93		T4	4251
auto[1]	triple_byte_access	1456200	1			T1	44		T4	82		T5	827
auto[1]	halfword_access	2182970	1			T1	54		T3	2		T4	149
auto[1]	byte_access	2912426	1			T1	97		T3	1		T4	151
auto[1]	zero_access	725437	1			T1	14		T4	36		T5	387