Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	349380164	1			T1	128420		T2	196606		T3	583774
instr_valid_dis	306498574	1			T1	128420		T2	196606		T3	583774
instr_en	29804861	1			T30	244980		T31	86		T32	14966

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11534550	1			T13	7624		T30	119272		T31	62716
sram_ifetch_valid_disable	305122758	1			T1	128420		T2	196606		T3	583774
sram_ifetch_enable	32722856	1			T30	205894		T31	164064		T32	13962

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	349380164	1			T1	128420		T2	196606		T3	583774
hw_debug_en_valid_off	297125340	1			T1	128420		T2	196606		T3	583774
hw_debug_en_on	30493530	1			T30	255584		T31	112488		T26	9162

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	305122758	1			T1	128420		T2	196606		T3	583774
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	283871168	1			T1	128420		T2	196606		T3	583774
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13448281	1			T30	94062		T31	86		T26	23710
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3937458	1			T13	7624		T30	18192		T31	34554
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1540762	1			T13	7624		T30	18192		T31	34554
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1795656	1			T26	49518		T121	13346		T122	25420
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4598998	1			T30	101080		T31	28162		T121	10518
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1714764	1			T31	28162		T121	10518		T7	306634
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2117600	1			T30	78094		T122	13928		T29	19010
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	14573422	1			T30	91556		T31	11040		T26	9086
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5996678	1			T30	43250		T31	10954		T7	155160
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	6673172	1			T30	28306		T31	86		T26	9086

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11604956	1			T30	72824		T32	13962		T26	17486
lc_exec_en	11321110	1			T30	62948		T31	73286		T26	76
valid_exec_dis	296509912	1			T1	128420		T2	196606		T3	583774
invalid_exec_dis	44257406	1			T13	7624		T30	325166		T31	226780