| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1475593784 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2172671323 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.691118970 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4232348455 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2240786057 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3205777101 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1924566693 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3402986797 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.224908304 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3348669198 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2396925203 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.209755049 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3495850907 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1475853792 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2160735699 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.377132683 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4246026938 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.743673045 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1168160475 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3435614790 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3704517305 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.287308885 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3180696553 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2739250690 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2929337470 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3387007841 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2904256933 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2818888451 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3639202027 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3391237811 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2782934593 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.862315648 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1998700559 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1647864594 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1938319149 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2659714811 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1523586304 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2296338161 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1863886295 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1054403372 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.931556471 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4222473904 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.884560199 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.839392645 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2494294431 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2473071009 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3497474644 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2419831128 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.424492843 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1204719234 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3661954804 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2889635887 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4196605207 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2318086747 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1364146668 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1979536026 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1407277173 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2129076614 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.677081466 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1900422207 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2491867465 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1698128099 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.129030471 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1709291419 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2170440899 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2306416721 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3249344808 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1960977274 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3313904199 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3250266093 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1775446183 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2743563359 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1096050825 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2233504987 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2080723888 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1436105608 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2915745555 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1579216738 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3475236970 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.384194617 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3794355404 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1848341517 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2314753837 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2198917120 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1111639375 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3565731304 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.68351616 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3800598409 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1796629538 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1162521828 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2300497207 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3845260556 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.912190083 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2494099426 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3977122029 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1399838297 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3933974482 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2813960077 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3561097979 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1999687439 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3130658299 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2046699994 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3314495792 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3766443864 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1298043743 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1807642511 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3489332129 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2162146016 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4075291918 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3938694405 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.905703315 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.894316814 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2912092871 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3992857223 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1723748514 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.29096943 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3513739082 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1411450921 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2338243128 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1828910266 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3061553071 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2525787514 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3920290407 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1750158312 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4216621909 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2834300231 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.419667169 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3919143609 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2326538321 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2341928086 |
| /workspace/coverage/default/0.sram_ctrl_bijection.834554371 |
| /workspace/coverage/default/0.sram_ctrl_executable.30734661 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.3055477135 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.2274346077 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.378919996 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.359463455 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.904304276 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.2263463568 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1074508105 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.3318364441 |
| /workspace/coverage/default/0.sram_ctrl_regwen.3876976981 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.1663175523 |
| /workspace/coverage/default/0.sram_ctrl_smoke.2278076538 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.210812029 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.426105350 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.826232779 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3553846789 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.876576652 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.2061019338 |
| /workspace/coverage/default/1.sram_ctrl_bijection.3688042061 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.165808488 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.3671224615 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3699177509 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.2457773155 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.3394056367 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.3097475375 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2044576081 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.2336630892 |
| /workspace/coverage/default/1.sram_ctrl_regwen.343131579 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.721300019 |
| /workspace/coverage/default/1.sram_ctrl_smoke.2477239278 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.241260008 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.416377557 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2637978032 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1208312807 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.3959863035 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.543506738 |
| /workspace/coverage/default/10.sram_ctrl_bijection.2416202683 |
| /workspace/coverage/default/10.sram_ctrl_executable.3421567747 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.3692994759 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.2120716071 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.421890797 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.3830195455 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.2616084756 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.324246027 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3620881301 |
| /workspace/coverage/default/10.sram_ctrl_regwen.3635865826 |
| /workspace/coverage/default/10.sram_ctrl_smoke.592311662 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.1030835357 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3944807469 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.4033359792 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2865898854 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3649896391 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.2074545100 |
| /workspace/coverage/default/11.sram_ctrl_bijection.1856221329 |
| /workspace/coverage/default/11.sram_ctrl_executable.566304892 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.2561251415 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.2791411019 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.477865875 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.2407534023 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.4058182215 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.1406300861 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.13541860 |
| /workspace/coverage/default/11.sram_ctrl_regwen.1424038591 |
| /workspace/coverage/default/11.sram_ctrl_smoke.3751309013 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.2448098950 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3776107400 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1291365123 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3509579277 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.4143294636 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.1435167016 |
| /workspace/coverage/default/12.sram_ctrl_bijection.2659138437 |
| /workspace/coverage/default/12.sram_ctrl_executable.2659088641 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.3594963003 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.187067921 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.413515306 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.1204532444 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.3216256121 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.2949390451 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3894543651 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.4269802176 |
| /workspace/coverage/default/12.sram_ctrl_regwen.3505593083 |
| /workspace/coverage/default/12.sram_ctrl_smoke.1318018166 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.616021924 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3382520851 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.4264316685 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1021902357 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.3246284890 |
| /workspace/coverage/default/13.sram_ctrl_bijection.1083653440 |
| /workspace/coverage/default/13.sram_ctrl_executable.2311357268 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.2386713772 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.3263689803 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.656655515 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.330295070 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.844362977 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.84009230 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1622364431 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.659114549 |
| /workspace/coverage/default/13.sram_ctrl_smoke.93721529 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.3616866911 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.183361662 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2724681329 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1752408044 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.4081899518 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.975633973 |
| /workspace/coverage/default/14.sram_ctrl_bijection.2294139515 |
| /workspace/coverage/default/14.sram_ctrl_executable.250862743 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.2060808084 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.689294989 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.272233125 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.68823672 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.3771747569 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.3367520189 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.972854470 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.3451774017 |
| /workspace/coverage/default/14.sram_ctrl_regwen.2275275431 |
| /workspace/coverage/default/14.sram_ctrl_smoke.177503141 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.929272087 |
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| /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.180456890 |
| /workspace/coverage/default/43.sram_ctrl_access_during_key_req.329645734 |
| /workspace/coverage/default/43.sram_ctrl_alert_test.2145152779 |
| /workspace/coverage/default/43.sram_ctrl_bijection.81531940 |
| /workspace/coverage/default/43.sram_ctrl_executable.1329605722 |
| /workspace/coverage/default/43.sram_ctrl_lc_escalation.2647410168 |
| /workspace/coverage/default/43.sram_ctrl_max_throughput.1061348446 |
| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.1300855508 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.1722794206 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.186831672 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.3577813274 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1183006262 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.34619049 |
| /workspace/coverage/default/43.sram_ctrl_regwen.920233526 |
| /workspace/coverage/default/43.sram_ctrl_smoke.1561015809 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.2119483687 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1183099396 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2042809612 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1826179270 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1793564549 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.469590828 |
| /workspace/coverage/default/44.sram_ctrl_bijection.3454438598 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.1078105248 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.3128180500 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1183948319 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.3328186560 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.2812769658 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.1721249923 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1194572746 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.1150945588 |
| /workspace/coverage/default/44.sram_ctrl_regwen.3598657529 |
| /workspace/coverage/default/44.sram_ctrl_smoke.3959660803 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.3484136168 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2777204393 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1655072948 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3324252844 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3910518893 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.485010539 |
| /workspace/coverage/default/45.sram_ctrl_bijection.2964218343 |
| /workspace/coverage/default/45.sram_ctrl_executable.3688307370 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.3222714975 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.2071720489 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2995201885 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.2592379356 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.887063754 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.3668098158 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.96223053 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.4233489265 |
| /workspace/coverage/default/45.sram_ctrl_regwen.458702626 |
| /workspace/coverage/default/45.sram_ctrl_smoke.3349377198 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.1524759796 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1853099285 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2061676206 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.791631657 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2585347190 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.925546835 |
| /workspace/coverage/default/46.sram_ctrl_bijection.3670939797 |
| /workspace/coverage/default/46.sram_ctrl_executable.3487717557 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.1529672827 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.3352536290 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1098059113 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.4121243713 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.1697695999 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.382405537 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.349705893 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.225935296 |
| /workspace/coverage/default/46.sram_ctrl_regwen.731541808 |
| /workspace/coverage/default/46.sram_ctrl_smoke.2999882539 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.627219169 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3930709777 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2030607219 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3765650601 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1293614011 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.1538608758 |
| /workspace/coverage/default/47.sram_ctrl_bijection.410033396 |
| /workspace/coverage/default/47.sram_ctrl_executable.1745727106 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.2236253623 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.3560362379 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2860571195 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.2854363352 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.4191451349 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.834079546 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.4290973733 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.3680614363 |
| /workspace/coverage/default/47.sram_ctrl_regwen.3089019442 |
| /workspace/coverage/default/47.sram_ctrl_smoke.2359886323 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.2004543591 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.263191137 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3969307850 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4035268397 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1456316785 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.2139206307 |
| /workspace/coverage/default/48.sram_ctrl_bijection.3126393948 |
| /workspace/coverage/default/48.sram_ctrl_executable.2808203061 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.2252278509 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.214954023 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.2715308308 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.4849189 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.1866239055 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4224567950 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.3387681593 |
| /workspace/coverage/default/48.sram_ctrl_regwen.1661996122 |
| /workspace/coverage/default/48.sram_ctrl_smoke.2709515098 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.3862662455 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2658761899 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.294228409 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1893987972 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1818523892 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.2630493123 |
| /workspace/coverage/default/49.sram_ctrl_bijection.1722845436 |
| /workspace/coverage/default/49.sram_ctrl_executable.229935543 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.4144352088 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.152234972 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.4055845493 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.1353052682 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.2665676811 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.1637916264 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3698090389 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.2613687958 |
| /workspace/coverage/default/49.sram_ctrl_regwen.425063291 |
| /workspace/coverage/default/49.sram_ctrl_smoke.1761001018 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1918151688 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.469386759 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2468998217 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1758965388 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.488382292 |
| /workspace/coverage/default/5.sram_ctrl_bijection.2519689748 |
| /workspace/coverage/default/5.sram_ctrl_executable.4169102153 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.4047950598 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.1350601254 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.2121254633 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.2017445455 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.1287605031 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3800601717 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.3010099474 |
| /workspace/coverage/default/5.sram_ctrl_regwen.2355780261 |
| /workspace/coverage/default/5.sram_ctrl_smoke.1163845590 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.1257846790 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2080206435 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2744910328 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1519760412 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1936685316 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.3350217116 |
| /workspace/coverage/default/6.sram_ctrl_bijection.271902972 |
| /workspace/coverage/default/6.sram_ctrl_executable.120580982 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.2041534095 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.2541419205 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1060215444 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.3821591000 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.3167649991 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.349711373 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3167851535 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.1304569347 |
| /workspace/coverage/default/6.sram_ctrl_regwen.2976698993 |
| /workspace/coverage/default/6.sram_ctrl_smoke.3099528573 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.2081669002 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2948713383 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.407513955 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3643052651 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1737757427 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.923455579 |
| /workspace/coverage/default/7.sram_ctrl_bijection.1696899627 |
| /workspace/coverage/default/7.sram_ctrl_executable.1240558210 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.1543684033 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.84607897 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.786426118 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.228303239 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.3018074309 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.3745422048 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2039160587 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.850655361 |
| /workspace/coverage/default/7.sram_ctrl_regwen.515913956 |
| /workspace/coverage/default/7.sram_ctrl_smoke.2904669497 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.337136441 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2176468243 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.770865329 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.697645449 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.1810299184 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.2425411395 |
| /workspace/coverage/default/8.sram_ctrl_bijection.641701354 |
| /workspace/coverage/default/8.sram_ctrl_executable.3861332816 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.3014006514 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.2706656135 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3743129124 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.1099903325 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.2982498701 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.3534034111 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3095554541 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.2940164340 |
| /workspace/coverage/default/8.sram_ctrl_regwen.3477311869 |
| /workspace/coverage/default/8.sram_ctrl_smoke.984783399 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.1664097035 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3655189954 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.4152783908 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2491379362 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.30667852 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.2561871793 |
| /workspace/coverage/default/9.sram_ctrl_bijection.4063219377 |
| /workspace/coverage/default/9.sram_ctrl_executable.3993381728 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.3911945714 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.2422161597 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.493846724 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.3149210771 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.3595384333 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.570621967 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2885306993 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.3319296880 |
| /workspace/coverage/default/9.sram_ctrl_regwen.3219703710 |
| /workspace/coverage/default/9.sram_ctrl_smoke.447134605 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.1353720689 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3594455890 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3398441890 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3199940359 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2474909215 |
|
|
Apr 18 02:31:07 PM PDT 24 |
Apr 18 02:33:32 PM PDT 24 |
4559897608 ps |
| T2 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.1359227518 |
|
|
Apr 18 02:33:56 PM PDT 24 |
Apr 18 02:36:39 PM PDT 24 |
21518669857 ps |
| T3 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.900500621 |
|
|
Apr 18 02:42:37 PM PDT 24 |
Apr 18 02:51:30 PM PDT 24 |
43431457105 ps |
| T4 |
/workspace/coverage/default/47.sram_ctrl_partial_access.834079546 |
|
|
Apr 18 02:44:48 PM PDT 24 |
Apr 18 02:45:02 PM PDT 24 |
3065815469 ps |
| T8 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3065474461 |
|
|
Apr 18 02:32:23 PM PDT 24 |
Apr 18 02:32:29 PM PDT 24 |
321822103 ps |
| T9 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1313024511 |
|
|
Apr 18 02:31:56 PM PDT 24 |
Apr 18 02:38:48 PM PDT 24 |
59373849988 ps |
| T10 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3990562801 |
|
|
Apr 18 02:39:46 PM PDT 24 |
Apr 18 02:42:35 PM PDT 24 |
1843371387 ps |
| T11 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.459890245 |
|
|
Apr 18 02:33:53 PM PDT 24 |
Apr 18 02:34:24 PM PDT 24 |
1509754111 ps |
| T5 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.4028627339 |
|
|
Apr 18 02:45:18 PM PDT 24 |
Apr 18 02:46:35 PM PDT 24 |
11114716932 ps |
| T12 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.2485743178 |
|
|
Apr 18 02:33:47 PM PDT 24 |
Apr 18 02:37:59 PM PDT 24 |
17956026080 ps |
| T15 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.3463086868 |
|
|
Apr 18 02:35:06 PM PDT 24 |
Apr 18 02:40:12 PM PDT 24 |
89792195997 ps |
| T19 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.3451774017 |
|
|
Apr 18 02:32:51 PM PDT 24 |
Apr 18 02:32:55 PM PDT 24 |
359562036 ps |
| T13 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3938103564 |
|
|
Apr 18 02:35:26 PM PDT 24 |
Apr 18 02:36:09 PM PDT 24 |
1380796434 ps |
| T23 |
/workspace/coverage/default/30.sram_ctrl_alert_test.392943515 |
|
|
Apr 18 02:38:19 PM PDT 24 |
Apr 18 02:38:20 PM PDT 24 |
69965027 ps |
| T16 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.2902546908 |
|
|
Apr 18 02:36:43 PM PDT 24 |
Apr 18 02:38:19 PM PDT 24 |
1922561068 ps |
| T33 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.875963455 |
|
|
Apr 18 02:31:45 PM PDT 24 |
Apr 18 02:31:49 PM PDT 24 |
1343251282 ps |
| T6 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1543684033 |
|
|
Apr 18 02:31:14 PM PDT 24 |
Apr 18 02:31:50 PM PDT 24 |
5288257258 ps |
| T55 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.4849189 |
|
|
Apr 18 02:45:16 PM PDT 24 |
Apr 18 03:06:35 PM PDT 24 |
36122481421 ps |
| T92 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.4282979296 |
|
|
Apr 18 02:34:26 PM PDT 24 |
Apr 18 02:39:14 PM PDT 24 |
4728185131 ps |
| T30 |
/workspace/coverage/default/0.sram_ctrl_executable.30734661 |
|
|
Apr 18 02:30:36 PM PDT 24 |
Apr 18 02:53:10 PM PDT 24 |
13320373331 ps |
| T31 |
/workspace/coverage/default/47.sram_ctrl_regwen.3089019442 |
|
|
Apr 18 02:45:01 PM PDT 24 |
Apr 18 02:54:44 PM PDT 24 |
25724066412 ps |
| T32 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3203286948 |
|
|
Apr 18 02:34:48 PM PDT 24 |
Apr 18 02:36:11 PM PDT 24 |
4213748682 ps |
| T134 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.4280684645 |
|
|
Apr 18 02:42:07 PM PDT 24 |
Apr 18 02:56:22 PM PDT 24 |
34020471982 ps |
| T66 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.3624203123 |
|
|
Apr 18 02:37:14 PM PDT 24 |
Apr 18 02:39:44 PM PDT 24 |
18170819139 ps |
| T26 |
/workspace/coverage/default/30.sram_ctrl_regwen.2816958583 |
|
|
Apr 18 02:38:14 PM PDT 24 |
Apr 18 02:41:21 PM PDT 24 |
4215700893 ps |
| T135 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.689294989 |
|
|
Apr 18 02:32:50 PM PDT 24 |
Apr 18 02:33:01 PM PDT 24 |
3099615465 ps |
| T132 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2748939970 |
|
|
Apr 18 02:36:27 PM PDT 24 |
Apr 18 02:58:45 PM PDT 24 |
78279159471 ps |
| T136 |
/workspace/coverage/default/24.sram_ctrl_smoke.3759288581 |
|
|
Apr 18 02:35:51 PM PDT 24 |
Apr 18 02:36:13 PM PDT 24 |
3292798401 ps |
| T67 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.2196612471 |
|
|
Apr 18 02:34:04 PM PDT 24 |
Apr 18 02:59:40 PM PDT 24 |
53525958028 ps |
| T137 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.3350713856 |
|
|
Apr 18 02:39:19 PM PDT 24 |
Apr 18 02:41:26 PM PDT 24 |
7307284088 ps |
| T14 |
/workspace/coverage/default/42.sram_ctrl_smoke.866945624 |
|
|
Apr 18 02:42:37 PM PDT 24 |
Apr 18 02:44:26 PM PDT 24 |
2108639164 ps |
| T47 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2653106196 |
|
|
Apr 18 02:33:57 PM PDT 24 |
Apr 18 02:34:04 PM PDT 24 |
647666879 ps |
| T73 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.2490103042 |
|
|
Apr 18 02:37:52 PM PDT 24 |
Apr 18 02:39:04 PM PDT 24 |
4803035913 ps |
| T121 |
/workspace/coverage/default/41.sram_ctrl_executable.662768840 |
|
|
Apr 18 02:42:27 PM PDT 24 |
Apr 18 02:49:14 PM PDT 24 |
18023020849 ps |
| T93 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.1018419079 |
|
|
Apr 18 02:37:19 PM PDT 24 |
Apr 18 02:39:38 PM PDT 24 |
6666836261 ps |
| T7 |
/workspace/coverage/default/41.sram_ctrl_stress_all.3578744367 |
|
|
Apr 18 02:42:27 PM PDT 24 |
Apr 18 03:26:09 PM PDT 24 |
126999890501 ps |
| T94 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3167851535 |
|
|
Apr 18 02:31:08 PM PDT 24 |
Apr 18 02:38:19 PM PDT 24 |
35411857511 ps |
| T95 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1793012013 |
|
|
Apr 18 02:39:55 PM PDT 24 |
Apr 18 02:46:21 PM PDT 24 |
29391610432 ps |
| T138 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.3128180500 |
|
|
Apr 18 02:43:30 PM PDT 24 |
Apr 18 02:43:40 PM PDT 24 |
1118433351 ps |
| T139 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.233696726 |
|
|
Apr 18 02:35:37 PM PDT 24 |
Apr 18 02:36:30 PM PDT 24 |
3897613974 ps |
| T34 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.3003253962 |
|
|
Apr 18 02:34:39 PM PDT 24 |
Apr 18 02:34:43 PM PDT 24 |
1539931289 ps |
| T140 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.186831672 |
|
|
Apr 18 02:42:59 PM PDT 24 |
Apr 18 02:44:12 PM PDT 24 |
15411455456 ps |
| T141 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.2362086285 |
|
|
Apr 18 02:36:32 PM PDT 24 |
Apr 18 02:36:57 PM PDT 24 |
14048378537 ps |
| T131 |
/workspace/coverage/default/21.sram_ctrl_bijection.2521086153 |
|
|
Apr 18 02:34:55 PM PDT 24 |
Apr 18 03:08:35 PM PDT 24 |
61927365987 ps |
| T142 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.659114549 |
|
|
Apr 18 02:32:40 PM PDT 24 |
Apr 18 02:32:43 PM PDT 24 |
1158953056 ps |
| T143 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.959663311 |
|
|
Apr 18 02:33:15 PM PDT 24 |
Apr 18 02:34:30 PM PDT 24 |
3042746724 ps |
| T122 |
/workspace/coverage/default/44.sram_ctrl_executable.1569776430 |
|
|
Apr 18 02:43:46 PM PDT 24 |
Apr 18 02:55:45 PM PDT 24 |
7057334218 ps |
| T144 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2652324359 |
|
|
Apr 18 02:34:28 PM PDT 24 |
Apr 18 02:35:45 PM PDT 24 |
1573623796 ps |
| T145 |
/workspace/coverage/default/35.sram_ctrl_partial_access.2976806200 |
|
|
Apr 18 02:39:54 PM PDT 24 |
Apr 18 02:40:18 PM PDT 24 |
17284802966 ps |
| T53 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.2259348864 |
|
|
Apr 18 02:33:51 PM PDT 24 |
Apr 18 02:34:44 PM PDT 24 |
9308496816 ps |
| T146 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1181237678 |
|
|
Apr 18 02:34:57 PM PDT 24 |
Apr 18 02:35:51 PM PDT 24 |
3117102313 ps |
| T133 |
/workspace/coverage/default/27.sram_ctrl_bijection.2348537789 |
|
|
Apr 18 02:37:01 PM PDT 24 |
Apr 18 03:01:58 PM PDT 24 |
42625543432 ps |
| T24 |
/workspace/coverage/default/35.sram_ctrl_alert_test.1114834777 |
|
|
Apr 18 02:40:10 PM PDT 24 |
Apr 18 02:40:11 PM PDT 24 |
22382271 ps |
| T96 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.1798658897 |
|
|
Apr 18 02:30:53 PM PDT 24 |
Apr 18 02:36:38 PM PDT 24 |
18531307780 ps |
| T25 |
/workspace/coverage/default/42.sram_ctrl_alert_test.2945263050 |
|
|
Apr 18 02:42:58 PM PDT 24 |
Apr 18 02:42:59 PM PDT 24 |
41327917 ps |
| T147 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.659881511 |
|
|
Apr 18 02:39:03 PM PDT 24 |
Apr 18 02:43:46 PM PDT 24 |
14334656386 ps |
| T148 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1835721377 |
|
|
Apr 18 02:37:49 PM PDT 24 |
Apr 18 02:40:17 PM PDT 24 |
1634500020 ps |
| T46 |
/workspace/coverage/default/26.sram_ctrl_executable.1793324438 |
|
|
Apr 18 02:36:43 PM PDT 24 |
Apr 18 02:50:11 PM PDT 24 |
27154328700 ps |
| T97 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2030607219 |
|
|
Apr 18 02:44:18 PM PDT 24 |
Apr 18 02:45:37 PM PDT 24 |
4156769899 ps |
| T149 |
/workspace/coverage/default/4.sram_ctrl_alert_test.1939050906 |
|
|
Apr 18 02:30:57 PM PDT 24 |
Apr 18 02:30:58 PM PDT 24 |
68133976 ps |
| T17 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3070883178 |
|
|
Apr 18 02:33:16 PM PDT 24 |
Apr 18 02:45:34 PM PDT 24 |
45281793892 ps |
| T150 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.2013913850 |
|
|
Apr 18 02:40:52 PM PDT 24 |
Apr 18 02:42:57 PM PDT 24 |
8228390640 ps |
| T27 |
/workspace/coverage/default/27.sram_ctrl_regwen.3895259569 |
|
|
Apr 18 02:37:03 PM PDT 24 |
Apr 18 02:50:47 PM PDT 24 |
3190832604 ps |
| T28 |
/workspace/coverage/default/25.sram_ctrl_regwen.1485513803 |
|
|
Apr 18 02:36:23 PM PDT 24 |
Apr 18 03:03:50 PM PDT 24 |
21415643727 ps |
| T29 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1438710192 |
|
|
Apr 18 02:39:07 PM PDT 24 |
Apr 18 04:20:58 PM PDT 24 |
88711333696 ps |
| T54 |
/workspace/coverage/default/23.sram_ctrl_stress_all.2363567587 |
|
|
Apr 18 02:35:54 PM PDT 24 |
Apr 18 04:18:21 PM PDT 24 |
245513836902 ps |
| T48 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.263191137 |
|
|
Apr 18 02:45:05 PM PDT 24 |
Apr 18 02:45:29 PM PDT 24 |
869460203 ps |
| T107 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.3479300460 |
|
|
Apr 18 02:38:57 PM PDT 24 |
Apr 18 02:39:43 PM PDT 24 |
33651528445 ps |
| T151 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3476357880 |
|
|
Apr 18 02:35:17 PM PDT 24 |
Apr 18 02:35:41 PM PDT 24 |
8817196446 ps |
| T152 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3534034111 |
|
|
Apr 18 02:31:25 PM PDT 24 |
Apr 18 02:31:43 PM PDT 24 |
625780961 ps |
| T153 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.2751061357 |
|
|
Apr 18 02:30:55 PM PDT 24 |
Apr 18 02:35:31 PM PDT 24 |
6517112930 ps |
| T154 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.4057748621 |
|
|
Apr 18 02:40:01 PM PDT 24 |
Apr 18 02:41:12 PM PDT 24 |
10592429629 ps |
| T155 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.228293299 |
|
|
Apr 18 02:34:56 PM PDT 24 |
Apr 18 02:35:50 PM PDT 24 |
28570591433 ps |
| T156 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.4152783908 |
|
|
Apr 18 02:31:20 PM PDT 24 |
Apr 18 02:36:38 PM PDT 24 |
5335836112 ps |
| T157 |
/workspace/coverage/default/15.sram_ctrl_alert_test.807128071 |
|
|
Apr 18 02:33:11 PM PDT 24 |
Apr 18 02:33:12 PM PDT 24 |
24089593 ps |
| T158 |
/workspace/coverage/default/33.sram_ctrl_bijection.4029480001 |
|
|
Apr 18 02:39:11 PM PDT 24 |
Apr 18 03:26:49 PM PDT 24 |
689571393104 ps |
| T159 |
/workspace/coverage/default/40.sram_ctrl_smoke.3510434210 |
|
|
Apr 18 02:41:47 PM PDT 24 |
Apr 18 02:41:59 PM PDT 24 |
909921741 ps |
| T49 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1853099285 |
|
|
Apr 18 02:44:17 PM PDT 24 |
Apr 18 02:47:26 PM PDT 24 |
10233152124 ps |
| T160 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3509579277 |
|
|
Apr 18 02:32:03 PM PDT 24 |
Apr 18 02:32:47 PM PDT 24 |
4090566227 ps |
| T161 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.4049314012 |
|
|
Apr 18 02:35:36 PM PDT 24 |
Apr 18 02:37:30 PM PDT 24 |
797395639 ps |
| T162 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2145152779 |
|
|
Apr 18 02:43:26 PM PDT 24 |
Apr 18 02:43:27 PM PDT 24 |
26807261 ps |
| T163 |
/workspace/coverage/default/1.sram_ctrl_smoke.2477239278 |
|
|
Apr 18 02:30:39 PM PDT 24 |
Apr 18 02:30:56 PM PDT 24 |
4281872989 ps |
| T164 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2295083295 |
|
|
Apr 18 02:39:15 PM PDT 24 |
Apr 18 02:39:26 PM PDT 24 |
2849857296 ps |
| T165 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.333651374 |
|
|
Apr 18 02:41:42 PM PDT 24 |
Apr 18 02:46:53 PM PDT 24 |
21522555842 ps |
| T18 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1818523892 |
|
|
Apr 18 02:45:44 PM PDT 24 |
Apr 18 03:01:23 PM PDT 24 |
22532268559 ps |
| T50 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.183361662 |
|
|
Apr 18 02:32:40 PM PDT 24 |
Apr 18 02:32:51 PM PDT 24 |
619219390 ps |
| T74 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.2199185423 |
|
|
Apr 18 02:30:59 PM PDT 24 |
Apr 18 02:33:07 PM PDT 24 |
6464548786 ps |
| T51 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2184893339 |
|
|
Apr 18 02:35:45 PM PDT 24 |
Apr 18 02:35:54 PM PDT 24 |
3126679000 ps |
| T166 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1150945588 |
|
|
Apr 18 02:43:47 PM PDT 24 |
Apr 18 02:43:51 PM PDT 24 |
5611550471 ps |
| T167 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.1813369372 |
|
|
Apr 18 02:30:51 PM PDT 24 |
Apr 18 02:30:55 PM PDT 24 |
1604622643 ps |
| T75 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.4081899518 |
|
|
Apr 18 02:32:50 PM PDT 24 |
Apr 18 02:47:42 PM PDT 24 |
46243942058 ps |
| T76 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1183948319 |
|
|
Apr 18 02:43:54 PM PDT 24 |
Apr 18 02:45:03 PM PDT 24 |
4684491298 ps |
| T168 |
/workspace/coverage/default/47.sram_ctrl_executable.1745727106 |
|
|
Apr 18 02:44:59 PM PDT 24 |
Apr 18 02:57:17 PM PDT 24 |
6616433673 ps |
| T169 |
/workspace/coverage/default/18.sram_ctrl_stress_all.2296381142 |
|
|
Apr 18 02:33:57 PM PDT 24 |
Apr 18 03:39:33 PM PDT 24 |
37288994227 ps |
| T52 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2435456179 |
|
|
Apr 18 02:30:50 PM PDT 24 |
Apr 18 02:31:37 PM PDT 24 |
5628325096 ps |
| T77 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3926454906 |
|
|
Apr 18 02:30:34 PM PDT 24 |
Apr 18 02:53:19 PM PDT 24 |
223751392202 ps |
| T87 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2733497616 |
|
|
Apr 18 02:33:56 PM PDT 24 |
Apr 18 02:36:29 PM PDT 24 |
5190458435 ps |
| T170 |
/workspace/coverage/default/7.sram_ctrl_stress_all.337136441 |
|
|
Apr 18 02:31:20 PM PDT 24 |
Apr 18 04:13:18 PM PDT 24 |
65689664619 ps |
| T171 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.2454743010 |
|
|
Apr 18 02:37:39 PM PDT 24 |
Apr 18 02:51:26 PM PDT 24 |
5176024341 ps |
| T172 |
/workspace/coverage/default/16.sram_ctrl_bijection.985217682 |
|
|
Apr 18 02:33:10 PM PDT 24 |
Apr 18 03:12:02 PM PDT 24 |
690279771225 ps |
| T173 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.692120434 |
|
|
Apr 18 02:38:27 PM PDT 24 |
Apr 18 02:43:21 PM PDT 24 |
4218140898 ps |
| T88 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1793564549 |
|
|
Apr 18 02:43:39 PM PDT 24 |
Apr 18 03:00:26 PM PDT 24 |
60835874112 ps |
| T174 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2561251415 |
|
|
Apr 18 02:32:05 PM PDT 24 |
Apr 18 02:32:35 PM PDT 24 |
17087799864 ps |
| T175 |
/workspace/coverage/default/20.sram_ctrl_bijection.1030464520 |
|
|
Apr 18 02:34:19 PM PDT 24 |
Apr 18 02:54:01 PM PDT 24 |
987952295825 ps |
| T176 |
/workspace/coverage/default/29.sram_ctrl_partial_access.4215776097 |
|
|
Apr 18 02:37:38 PM PDT 24 |
Apr 18 02:37:57 PM PDT 24 |
896838202 ps |
| T177 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2539975465 |
|
|
Apr 18 02:39:16 PM PDT 24 |
Apr 18 02:46:50 PM PDT 24 |
19071981741 ps |
| T108 |
/workspace/coverage/default/5.sram_ctrl_stress_all.1257846790 |
|
|
Apr 18 02:31:07 PM PDT 24 |
Apr 18 04:05:28 PM PDT 24 |
324102475020 ps |
| T178 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1726364544 |
|
|
Apr 18 02:39:40 PM PDT 24 |
Apr 18 02:47:59 PM PDT 24 |
26409957649 ps |
| T179 |
/workspace/coverage/default/13.sram_ctrl_executable.2311357268 |
|
|
Apr 18 02:32:34 PM PDT 24 |
Apr 18 02:51:56 PM PDT 24 |
133623188317 ps |
| T180 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.825115428 |
|
|
Apr 18 02:36:47 PM PDT 24 |
Apr 18 02:37:48 PM PDT 24 |
4157162214 ps |
| T181 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1194572746 |
|
|
Apr 18 02:43:32 PM PDT 24 |
Apr 18 02:46:51 PM PDT 24 |
4210371122 ps |
| T182 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2044576081 |
|
|
Apr 18 02:30:38 PM PDT 24 |
Apr 18 02:33:45 PM PDT 24 |
132780399006 ps |
| T183 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.2206541342 |
|
|
Apr 18 02:42:32 PM PDT 24 |
Apr 18 02:43:40 PM PDT 24 |
1460254108 ps |
| T184 |
/workspace/coverage/default/48.sram_ctrl_smoke.2709515098 |
|
|
Apr 18 02:45:14 PM PDT 24 |
Apr 18 02:45:23 PM PDT 24 |
1278516558 ps |
| T20 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1873544145 |
|
|
Apr 18 02:30:52 PM PDT 24 |
Apr 18 02:30:55 PM PDT 24 |
155512474 ps |
| T37 |
/workspace/coverage/default/17.sram_ctrl_partial_access.1929235928 |
|
|
Apr 18 02:33:31 PM PDT 24 |
Apr 18 02:33:38 PM PDT 24 |
3181165635 ps |
| T38 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3680614363 |
|
|
Apr 18 02:45:00 PM PDT 24 |
Apr 18 02:45:03 PM PDT 24 |
352753535 ps |
| T39 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.1747673004 |
|
|
Apr 18 02:37:03 PM PDT 24 |
Apr 18 02:37:16 PM PDT 24 |
691167054 ps |
| T40 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1737757427 |
|
|
Apr 18 02:31:21 PM PDT 24 |
Apr 18 02:32:28 PM PDT 24 |
14604932419 ps |
| T41 |
/workspace/coverage/default/23.sram_ctrl_executable.408560520 |
|
|
Apr 18 02:35:46 PM PDT 24 |
Apr 18 02:56:34 PM PDT 24 |
17549839841 ps |
| T42 |
/workspace/coverage/default/9.sram_ctrl_bijection.4063219377 |
|
|
Apr 18 02:31:30 PM PDT 24 |
Apr 18 02:53:35 PM PDT 24 |
250119887673 ps |
| T43 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.3546030699 |
|
|
Apr 18 02:33:36 PM PDT 24 |
Apr 18 02:34:50 PM PDT 24 |
2630509041 ps |
| T44 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.2944303052 |
|
|
Apr 18 02:41:57 PM PDT 24 |
Apr 18 02:42:08 PM PDT 24 |
695471514 ps |
| T45 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1021902357 |
|
|
Apr 18 02:32:36 PM PDT 24 |
Apr 18 02:32:49 PM PDT 24 |
1063314570 ps |
| T124 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1941304314 |
|
|
Apr 18 02:33:31 PM PDT 24 |
Apr 18 02:38:14 PM PDT 24 |
12174410342 ps |
| T185 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2600919853 |
|
|
Apr 18 02:33:00 PM PDT 24 |
Apr 18 02:38:54 PM PDT 24 |
17331487887 ps |
| T186 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.2910581136 |
|
|
Apr 18 02:40:46 PM PDT 24 |
Apr 18 02:42:56 PM PDT 24 |
3647912511 ps |
| T187 |
/workspace/coverage/default/36.sram_ctrl_smoke.1870615033 |
|
|
Apr 18 02:40:09 PM PDT 24 |
Apr 18 02:40:15 PM PDT 24 |
864182617 ps |
| T188 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.3750251327 |
|
|
Apr 18 02:33:08 PM PDT 24 |
Apr 18 02:35:12 PM PDT 24 |
2061146407 ps |
| T189 |
/workspace/coverage/default/26.sram_ctrl_regwen.3927690318 |
|
|
Apr 18 02:36:44 PM PDT 24 |
Apr 18 02:45:35 PM PDT 24 |
17164311602 ps |
| T190 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.850655361 |
|
|
Apr 18 02:31:20 PM PDT 24 |
Apr 18 02:31:24 PM PDT 24 |
1023107331 ps |
| T191 |
/workspace/coverage/default/41.sram_ctrl_smoke.3333510241 |
|
|
Apr 18 02:42:09 PM PDT 24 |
Apr 18 02:42:30 PM PDT 24 |
2483684541 ps |
| T192 |
/workspace/coverage/default/41.sram_ctrl_partial_access.704331799 |
|
|
Apr 18 02:42:13 PM PDT 24 |
Apr 18 02:42:36 PM PDT 24 |
1619453240 ps |
| T193 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.477462140 |
|
|
Apr 18 02:41:57 PM PDT 24 |
Apr 18 02:42:53 PM PDT 24 |
9068439321 ps |
| T194 |
/workspace/coverage/default/11.sram_ctrl_regwen.1424038591 |
|
|
Apr 18 02:32:03 PM PDT 24 |
Apr 18 02:38:08 PM PDT 24 |
5241410079 ps |
| T195 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.1908853936 |
|
|
Apr 18 02:33:37 PM PDT 24 |
Apr 18 02:37:38 PM PDT 24 |
4106812352 ps |
| T196 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3692994759 |
|
|
Apr 18 02:32:47 PM PDT 24 |
Apr 18 02:33:02 PM PDT 24 |
4358031817 ps |
| T197 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.3713194977 |
|
|
Apr 18 02:37:18 PM PDT 24 |
Apr 18 02:37:39 PM PDT 24 |
11647144336 ps |
| T198 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.349705893 |
|
|
Apr 18 02:44:17 PM PDT 24 |
Apr 18 02:52:26 PM PDT 24 |
202932676384 ps |
| T199 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1304569347 |
|
|
Apr 18 02:31:10 PM PDT 24 |
Apr 18 02:31:14 PM PDT 24 |
346752257 ps |
| T125 |
/workspace/coverage/default/14.sram_ctrl_stress_all.929272087 |
|
|
Apr 18 02:32:55 PM PDT 24 |
Apr 18 03:57:24 PM PDT 24 |
220720747479 ps |
| T200 |
/workspace/coverage/default/0.sram_ctrl_alert_test.4110443778 |
|
|
Apr 18 02:30:38 PM PDT 24 |
Apr 18 02:30:40 PM PDT 24 |
36634289 ps |
| T201 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1353052682 |
|
|
Apr 18 02:45:51 PM PDT 24 |
Apr 18 02:48:43 PM PDT 24 |
34426546499 ps |
| T202 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.2266320757 |
|
|
Apr 18 02:36:10 PM PDT 24 |
Apr 18 02:39:59 PM PDT 24 |
5917928395 ps |
| T203 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2422161597 |
|
|
Apr 18 02:31:34 PM PDT 24 |
Apr 18 02:32:15 PM PDT 24 |
3026112433 ps |
| T204 |
/workspace/coverage/default/6.sram_ctrl_smoke.3099528573 |
|
|
Apr 18 02:31:06 PM PDT 24 |
Apr 18 02:32:58 PM PDT 24 |
785384359 ps |
| T205 |
/workspace/coverage/default/44.sram_ctrl_regwen.3598657529 |
|
|
Apr 18 02:43:45 PM PDT 24 |
Apr 18 02:53:42 PM PDT 24 |
6710170511 ps |
| T206 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.407513955 |
|
|
Apr 18 02:31:06 PM PDT 24 |
Apr 18 02:33:55 PM PDT 24 |
3019050871 ps |
| T207 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2140143021 |
|
|
Apr 18 02:38:35 PM PDT 24 |
Apr 18 02:40:34 PM PDT 24 |
1618106724 ps |
| T208 |
/workspace/coverage/default/3.sram_ctrl_bijection.1431282906 |
|
|
Apr 18 02:30:52 PM PDT 24 |
Apr 18 02:49:30 PM PDT 24 |
51329666138 ps |
| T209 |
/workspace/coverage/default/10.sram_ctrl_alert_test.543506738 |
|
|
Apr 18 02:31:52 PM PDT 24 |
Apr 18 02:31:53 PM PDT 24 |
40791769 ps |
| T210 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3044600452 |
|
|
Apr 18 02:39:39 PM PDT 24 |
Apr 18 02:40:56 PM PDT 24 |
5096460627 ps |
| T211 |
/workspace/coverage/default/15.sram_ctrl_stress_all.1674616248 |
|
|
Apr 18 02:33:07 PM PDT 24 |
Apr 18 03:38:49 PM PDT 24 |
181520929970 ps |
| T212 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3631137634 |
|
|
Apr 18 02:41:07 PM PDT 24 |
Apr 18 02:46:15 PM PDT 24 |
23105019090 ps |
| T213 |
/workspace/coverage/default/34.sram_ctrl_partial_access.1181911795 |
|
|
Apr 18 02:39:40 PM PDT 24 |
Apr 18 02:40:24 PM PDT 24 |
901907891 ps |
| T214 |
/workspace/coverage/default/25.sram_ctrl_alert_test.2311505690 |
|
|
Apr 18 02:36:28 PM PDT 24 |
Apr 18 02:36:29 PM PDT 24 |
55995227 ps |
| T215 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.469386759 |
|
|
Apr 18 02:45:38 PM PDT 24 |
Apr 18 02:50:03 PM PDT 24 |
14514657355 ps |
| T216 |
/workspace/coverage/default/13.sram_ctrl_alert_test.3246284890 |
|
|
Apr 18 02:32:41 PM PDT 24 |
Apr 18 02:32:42 PM PDT 24 |
41718479 ps |
| T217 |
/workspace/coverage/default/36.sram_ctrl_partial_access.146605984 |
|
|
Apr 18 02:40:14 PM PDT 24 |
Apr 18 02:40:34 PM PDT 24 |
2369356722 ps |
| T218 |
/workspace/coverage/default/18.sram_ctrl_smoke.4188782317 |
|
|
Apr 18 02:33:39 PM PDT 24 |
Apr 18 02:34:26 PM PDT 24 |
1649969390 ps |
| T219 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.4058182215 |
|
|
Apr 18 02:31:51 PM PDT 24 |
Apr 18 02:32:22 PM PDT 24 |
1725208603 ps |
| T220 |
/workspace/coverage/default/2.sram_ctrl_bijection.2017705195 |
|
|
Apr 18 02:30:42 PM PDT 24 |
Apr 18 02:57:12 PM PDT 24 |
90489460283 ps |
| T221 |
/workspace/coverage/default/31.sram_ctrl_partial_access.685108390 |
|
|
Apr 18 02:38:27 PM PDT 24 |
Apr 18 02:38:36 PM PDT 24 |
1570419799 ps |
| T222 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2042809612 |
|
|
Apr 18 02:43:05 PM PDT 24 |
Apr 18 02:47:58 PM PDT 24 |
22977033487 ps |
| T223 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.43504637 |
|
|
Apr 18 02:39:30 PM PDT 24 |
Apr 18 02:59:47 PM PDT 24 |
32109355156 ps |
| T224 |
/workspace/coverage/default/29.sram_ctrl_stress_all.2918033167 |
|
|
Apr 18 02:37:51 PM PDT 24 |
Apr 18 03:06:31 PM PDT 24 |
77436070726 ps |
| T225 |
/workspace/coverage/default/14.sram_ctrl_alert_test.975633973 |
|
|
Apr 18 02:32:56 PM PDT 24 |
Apr 18 02:32:57 PM PDT 24 |
15060539 ps |
| T226 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1661915531 |
|
|
Apr 18 02:41:28 PM PDT 24 |
Apr 18 02:43:47 PM PDT 24 |
5742275088 ps |
| T227 |
/workspace/coverage/default/14.sram_ctrl_regwen.2275275431 |
|
|
Apr 18 02:32:49 PM PDT 24 |
Apr 18 02:44:45 PM PDT 24 |
2564385527 ps |
| T228 |
/workspace/coverage/default/4.sram_ctrl_partial_access.686521611 |
|
|
Apr 18 02:30:51 PM PDT 24 |
Apr 18 02:30:57 PM PDT 24 |
464068598 ps |
| T229 |
/workspace/coverage/default/10.sram_ctrl_bijection.2416202683 |
|
|
Apr 18 02:31:39 PM PDT 24 |
Apr 18 03:17:15 PM PDT 24 |
330736222251 ps |
| T230 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2041534095 |
|
|
Apr 18 02:31:10 PM PDT 24 |
Apr 18 02:31:44 PM PDT 24 |
20613962342 ps |
| T231 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2104473227 |
|
|
Apr 18 02:42:43 PM PDT 24 |
Apr 18 02:57:00 PM PDT 24 |
47378584849 ps |
| T123 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2948713383 |
|
|
Apr 18 02:31:10 PM PDT 24 |
Apr 18 02:31:44 PM PDT 24 |
5767423613 ps |
| T232 |
/workspace/coverage/default/10.sram_ctrl_smoke.592311662 |
|
|
Apr 18 02:31:40 PM PDT 24 |
Apr 18 02:31:47 PM PDT 24 |
702314904 ps |
| T233 |
/workspace/coverage/default/37.sram_ctrl_executable.3105441700 |
|
|
Apr 18 02:40:46 PM PDT 24 |
Apr 18 02:49:53 PM PDT 24 |
43082576250 ps |
| T234 |
/workspace/coverage/default/39.sram_ctrl_smoke.2322743712 |
|
|
Apr 18 02:41:27 PM PDT 24 |
Apr 18 02:42:29 PM PDT 24 |
4628834290 ps |
| T235 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.1099903325 |
|
|
Apr 18 02:31:30 PM PDT 24 |
Apr 18 02:33:49 PM PDT 24 |
12538857038 ps |
| T236 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.3077492159 |
|
|
Apr 18 02:36:12 PM PDT 24 |
Apr 18 02:43:25 PM PDT 24 |
38888718561 ps |
| T237 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.3426370372 |
|
|
Apr 18 02:33:21 PM PDT 24 |
Apr 18 02:33:25 PM PDT 24 |
347144952 ps |
| T238 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3545643591 |
|
|
Apr 18 02:32:51 PM PDT 24 |
Apr 18 02:33:16 PM PDT 24 |
2763677323 ps |
| T239 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.2872401059 |
|
|
Apr 18 02:38:56 PM PDT 24 |
Apr 18 02:39:00 PM PDT 24 |
353882396 ps |
| T240 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1753267670 |
|
|
Apr 18 02:38:36 PM PDT 24 |
Apr 18 02:38:40 PM PDT 24 |
680541651 ps |
| T241 |
/workspace/coverage/default/16.sram_ctrl_smoke.624277586 |
|
|
Apr 18 02:33:10 PM PDT 24 |
Apr 18 02:33:24 PM PDT 24 |
3166557174 ps |
| T242 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.6480932 |
|
|
Apr 18 02:33:09 PM PDT 24 |
Apr 18 02:35:36 PM PDT 24 |
8748465960 ps |
| T126 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3216256121 |
|
|
Apr 18 02:32:10 PM PDT 24 |
Apr 18 02:53:29 PM PDT 24 |
173424578558 ps |
| T243 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.3682619174 |
|
|
Apr 18 02:30:57 PM PDT 24 |
Apr 18 02:40:03 PM PDT 24 |
21652995319 ps |
| T244 |
/workspace/coverage/default/39.sram_ctrl_regwen.1392949402 |
|
|
Apr 18 02:41:43 PM PDT 24 |
Apr 18 02:59:28 PM PDT 24 |
5897678767 ps |
| T245 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.3263689803 |
|
|
Apr 18 02:33:21 PM PDT 24 |
Apr 18 02:35:12 PM PDT 24 |
3062263124 ps |
| T246 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3222714975 |
|
|
Apr 18 02:44:04 PM PDT 24 |
Apr 18 02:45:28 PM PDT 24 |
55783217647 ps |
| T247 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2386713772 |
|
|
Apr 18 02:32:33 PM PDT 24 |
Apr 18 02:34:20 PM PDT 24 |
57287123809 ps |
| T248 |
/workspace/coverage/default/48.sram_ctrl_alert_test.2139206307 |
|
|
Apr 18 02:45:38 PM PDT 24 |
Apr 18 02:45:39 PM PDT 24 |
17982939 ps |
| T249 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3510177914 |
|
|
Apr 18 02:36:32 PM PDT 24 |
Apr 18 02:38:43 PM PDT 24 |
22282426302 ps |
| T250 |
/workspace/coverage/default/48.sram_ctrl_stress_all.3862662455 |
|
|
Apr 18 02:45:44 PM PDT 24 |
Apr 18 03:29:27 PM PDT 24 |
87497035957 ps |
| T251 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1777809955 |
|
|
Apr 18 02:32:54 PM PDT 24 |
Apr 18 02:37:53 PM PDT 24 |
2355094146 ps |
| T252 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2683509742 |
|
|
Apr 18 02:40:02 PM PDT 24 |
Apr 18 02:41:43 PM PDT 24 |
798644513 ps |
| T253 |
/workspace/coverage/default/3.sram_ctrl_smoke.1309645478 |
|
|
Apr 18 02:30:50 PM PDT 24 |
Apr 18 02:32:27 PM PDT 24 |
1215584940 ps |
| T254 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3668098158 |
|
|
Apr 18 02:44:04 PM PDT 24 |
Apr 18 02:44:29 PM PDT 24 |
3549769884 ps |
| T255 |
/workspace/coverage/default/3.sram_ctrl_stress_all.2169762308 |
|
|
Apr 18 02:30:51 PM PDT 24 |
Apr 18 03:22:13 PM PDT 24 |
133179347902 ps |
| T256 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.968558331 |
|
|
Apr 18 02:37:43 PM PDT 24 |
Apr 18 02:38:32 PM PDT 24 |
1535331408 ps |
| T257 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3602999493 |
|
|
Apr 18 02:37:38 PM PDT 24 |
Apr 18 02:42:43 PM PDT 24 |
17935876055 ps |
| T258 |
/workspace/coverage/default/42.sram_ctrl_bijection.1029724525 |
|
|
Apr 18 02:42:34 PM PDT 24 |
Apr 18 02:54:54 PM PDT 24 |
49204063120 ps |
| T259 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.1543982467 |
|
|
Apr 18 02:41:27 PM PDT 24 |
Apr 18 03:03:35 PM PDT 24 |
21591674884 ps |
| T260 |
/workspace/coverage/default/8.sram_ctrl_executable.3861332816 |
|
|
Apr 18 02:31:27 PM PDT 24 |
Apr 18 02:43:43 PM PDT 24 |
32282537802 ps |
| T261 |
/workspace/coverage/default/46.sram_ctrl_smoke.2999882539 |
|
|
Apr 18 02:44:19 PM PDT 24 |
Apr 18 02:44:37 PM PDT 24 |
9747638771 ps |
| T262 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1456316785 |
|
|
Apr 18 02:45:25 PM PDT 24 |
Apr 18 02:59:08 PM PDT 24 |
97847272001 ps |
| T263 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3678571997 |
|
|
Apr 18 02:38:10 PM PDT 24 |
Apr 18 02:39:10 PM PDT 24 |
3690889327 ps |
| T264 |
/workspace/coverage/default/2.sram_ctrl_executable.4009121538 |
|
|
Apr 18 02:30:51 PM PDT 24 |
Apr 18 02:40:07 PM PDT 24 |
61248117186 ps |
| T265 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3095554541 |
|
|
Apr 18 02:31:25 PM PDT 24 |
Apr 18 02:36:12 PM PDT 24 |
10765662823 ps |
| T266 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.3039079958 |
|
|
Apr 18 02:37:01 PM PDT 24 |
Apr 18 02:39:13 PM PDT 24 |
21928837509 ps |
| T267 |
/workspace/coverage/default/5.sram_ctrl_bijection.2519689748 |
|
|
Apr 18 02:30:57 PM PDT 24 |
Apr 18 02:50:58 PM PDT 24 |
34757332342 ps |
| T268 |
/workspace/coverage/default/22.sram_ctrl_stress_all.1214149729 |
|
|
Apr 18 02:35:26 PM PDT 24 |
Apr 18 02:53:44 PM PDT 24 |
82190952372 ps |
| T269 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.1350601254 |
|
|
Apr 18 02:30:58 PM PDT 24 |
Apr 18 02:32:07 PM PDT 24 |
1888122425 ps |
| T270 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.1310977754 |
|
|
Apr 18 02:34:15 PM PDT 24 |
Apr 18 02:47:21 PM PDT 24 |
11622804062 ps |
| T271 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1752408044 |
|
|
Apr 18 02:32:40 PM PDT 24 |
Apr 18 02:32:47 PM PDT 24 |
6641269759 ps |
| T272 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.515464074 |
|
|
Apr 18 02:42:38 PM PDT 24 |
Apr 18 02:43:45 PM PDT 24 |
11657442408 ps |
| T273 |
/workspace/coverage/default/49.sram_ctrl_bijection.1722845436 |
|
|
Apr 18 02:45:39 PM PDT 24 |
Apr 18 03:23:37 PM PDT 24 |
137939461211 ps |
| T274 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.3358372553 |
|
|
Apr 18 02:41:35 PM PDT 24 |
Apr 18 02:42:36 PM PDT 24 |
48004473506 ps |
| T275 |
/workspace/coverage/default/34.sram_ctrl_smoke.4164075449 |
|
|
Apr 18 02:39:30 PM PDT 24 |
Apr 18 02:39:58 PM PDT 24 |
1849012376 ps |
| T276 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.3505264688 |
|
|
Apr 18 02:30:52 PM PDT 24 |
Apr 18 02:30:56 PM PDT 24 |
360527328 ps |
| T277 |
/workspace/coverage/default/32.sram_ctrl_smoke.1539279706 |
|
|
Apr 18 02:38:46 PM PDT 24 |
Apr 18 02:39:35 PM PDT 24 |
940142076 ps |
| T278 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.45914553 |
|
|
Apr 18 02:38:46 PM PDT 24 |
Apr 18 02:43:23 PM PDT 24 |
3728756781 ps |
| T279 |
/workspace/coverage/default/17.sram_ctrl_bijection.1614606380 |
|
|
Apr 18 02:33:31 PM PDT 24 |
Apr 18 03:01:55 PM PDT 24 |
374028239733 ps |
| T280 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.2710320521 |
|
|
Apr 18 02:42:26 PM PDT 24 |
Apr 18 02:42:30 PM PDT 24 |
1411797124 ps |
| T281 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.3821591000 |
|
|
Apr 18 02:31:09 PM PDT 24 |
Apr 18 02:36:12 PM PDT 24 |
20682686914 ps |
| T282 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.152234972 |
|
|
Apr 18 02:45:42 PM PDT 24 |
Apr 18 02:47:00 PM PDT 24 |
793719103 ps |
| T283 |
/workspace/coverage/default/48.sram_ctrl_bijection.3126393948 |
|
|
Apr 18 02:45:18 PM PDT 24 |
Apr 18 03:07:21 PM PDT 24 |
172629603269 ps |
| T284 |
/workspace/coverage/default/9.sram_ctrl_partial_access.570621967 |
|
|
Apr 18 02:31:37 PM PDT 24 |
Apr 18 02:32:01 PM PDT 24 |
1534090289 ps |
| T285 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1030835357 |
|
|
Apr 18 02:31:52 PM PDT 24 |
Apr 18 04:18:22 PM PDT 24 |
208504870772 ps |
| T286 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.1178088919 |
|
|
Apr 18 02:33:32 PM PDT 24 |
Apr 18 02:45:23 PM PDT 24 |
46830184714 ps |
| T287 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2061676206 |
|
|
Apr 18 02:44:02 PM PDT 24 |
Apr 18 02:48:23 PM PDT 24 |
9963070440 ps |
| T288 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3704658574 |
|
|
Apr 18 02:40:46 PM PDT 24 |
Apr 18 02:41:00 PM PDT 24 |
2799952970 ps |
| T289 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2017445455 |
|
|
Apr 18 02:31:06 PM PDT 24 |
Apr 18 02:36:36 PM PDT 24 |
2769989909 ps |
| T290 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.1771767258 |
|
|
Apr 18 02:33:05 PM PDT 24 |
Apr 18 02:33:08 PM PDT 24 |
353268288 ps |
| T291 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3654460779 |
|
|
Apr 18 02:36:18 PM PDT 24 |
Apr 18 02:41:30 PM PDT 24 |
13218016739 ps |
| T292 |
/workspace/coverage/default/46.sram_ctrl_regwen.731541808 |
|
|
Apr 18 02:44:37 PM PDT 24 |
Apr 18 03:05:20 PM PDT 24 |
12297596654 ps |
| T293 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1810299184 |
|
|
Apr 18 02:31:26 PM PDT 24 |
Apr 18 02:52:35 PM PDT 24 |
14001905605 ps |
| T294 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.567271625 |
|
|
Apr 18 02:40:01 PM PDT 24 |
Apr 18 02:40:05 PM PDT 24 |
355014863 ps |
| T295 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.4047950598 |
|
|
Apr 18 02:30:58 PM PDT 24 |
Apr 18 02:32:15 PM PDT 24 |
12534094175 ps |
| T296 |
/workspace/coverage/default/5.sram_ctrl_alert_test.488382292 |
|
|
Apr 18 02:31:06 PM PDT 24 |
Apr 18 02:31:07 PM PDT 24 |
121204920 ps |
| T297 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1287605031 |
|
|
Apr 18 02:30:58 PM PDT 24 |
Apr 18 02:31:14 PM PDT 24 |
900199221 ps |
| T298 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.34619049 |
|
|
Apr 18 02:43:09 PM PDT 24 |
Apr 18 02:43:13 PM PDT 24 |
1342709841 ps |
| T299 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1622364431 |
|
|
Apr 18 02:32:29 PM PDT 24 |
Apr 18 02:36:40 PM PDT 24 |
19939820643 ps |
| T129 |
/workspace/coverage/default/12.sram_ctrl_stress_all.616021924 |
|
|
Apr 18 02:32:24 PM PDT 24 |
Apr 18 02:53:59 PM PDT 24 |
67914271902 ps |
| T300 |
/workspace/coverage/default/24.sram_ctrl_stress_all.1859018775 |
|
|
Apr 18 02:36:12 PM PDT 24 |
Apr 18 04:19:07 PM PDT 24 |
306783435208 ps |
| T301 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.348054805 |
|
|
Apr 18 02:34:02 PM PDT 24 |
Apr 18 02:37:20 PM PDT 24 |
8801346765 ps |
| T302 |
/workspace/coverage/default/21.sram_ctrl_alert_test.2613691466 |
|
|
Apr 18 02:35:14 PM PDT 24 |
Apr 18 02:35:15 PM PDT 24 |
72936219 ps |
| T303 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3387681593 |
|
|
Apr 18 02:45:32 PM PDT 24 |
Apr 18 02:45:37 PM PDT 24 |
2815895916 ps |
| T304 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.189004846 |
|
|
Apr 18 02:30:57 PM PDT 24 |
Apr 18 02:31:10 PM PDT 24 |
759534585 ps |
| T305 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3655189954 |
|
|
Apr 18 02:31:30 PM PDT 24 |
Apr 18 02:32:26 PM PDT 24 |
8966460091 ps |