Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	145042320	1			T1	3215		T2	98303		T3	52858
triple_byte_access	2747536	1			T1	7224		T3	48078		T4	906
halfword_access	4219831	1			T1	13457		T3	71322		T4	1372
byte_access	5913574	1			T1	25202		T3	95935		T4	1760
zero_access	1802901	1			T1	15112		T3	23694		T4	485

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79774156

1

T1

32038

T2

32768

T3

145896

auto[1]

79952006

1

T1

32172

T2

65535

T3

145991

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	72287697	1			T1	290		T2	32768		T3	26335
auto[0]	triple_byte_access	1307530	1			T1	1370		T3	23776		T4	420
auto[0]	halfword_access	2060644	1			T1	4711		T3	35810		T4	706
auto[0]	byte_access	3034905	1			T1	13586		T3	48047		T4	881
auto[0]	zero_access	1083380	1			T1	12081		T3	11928		T4	249
auto[1]	word_access	72754623	1			T1	2925		T2	65535		T3	26523
auto[1]	triple_byte_access	1440006	1			T1	5854		T3	24302		T4	486
auto[1]	halfword_access	2159187	1			T1	8746		T3	35512		T4	666
auto[1]	byte_access	2878669	1			T1	11616		T3	47888		T4	879
auto[1]	zero_access	719521	1			T1	3031		T3	11766		T4	236