Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	348595886	1			T1	12798		T2	12828		T3	402960
instr_valid_dis	312569534	1			T1	12798		T2	12828		T3	258042
instr_en	25855732	1			T3	92786		T26	80460		T25	489624

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11637294	1			T3	95602		T12	45924		T26	56562
sram_ifetch_valid_disable	307578610	1			T1	12798		T2	12828		T3	102426
sram_ifetch_enable	29379982	1			T3	204932		T12	37198		T26	17330

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	348595886	1			T1	12798		T2	12828		T3	402960
hw_debug_en_valid_off	302919559	1			T1	12798		T2	12828		T3	150866
hw_debug_en_on	30244339	1			T3	125442		T12	111102		T26	38458

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	307578610	1			T1	12798		T2	12828		T3	102426
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	294745208	1			T1	12798		T2	12828		T3	29008
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8409116	1			T3	37310		T26	13880		T25	280676
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4674060	1			T3	15784		T26	49314		T25	12318
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1825178	1			T8	16766		T6	21360		T38	25602
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2105614	1			T3	15784		T26	49314		T25	12318
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5278292	1			T3	28582		T12	43712		T26	7248
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2668096	1			T3	16670		T26	7248		T6	88938
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1671044	1			T25	50986		T6	15738		T43	17112
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11189341	1			T3	41872		T12	30192		T26	13880
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6230148	1			T8	72920		T55	14994		T43	32216
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3260279	1			T3	37310		T26	13880		T25	76838

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13008576	1			T3	39692		T26	17266		T25	145644
lc_exec_en	13776706	1			T3	54988		T12	37198		T26	17330
valid_exec_dis	301900473	1			T1	12798		T2	12828		T3	221682
invalid_exec_dis	41017276	1			T3	300534		T12	83122		T26	73892