Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	144807499	1			T1	5766		T2	5232		T3	87715
triple_byte_access	2788236	1			T1	133		T2	234		T3	1752
halfword_access	4272357	1			T1	194		T2	347		T3	2666
byte_access	5972475	1			T1	248		T2	465		T3	3611
zero_access	1801466	1			T1	58		T2	136		T3	913

---

Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79546775

1

T1

3143

T2

3169

T3

53167

auto[1]

80095258

1

T1

3256

T2

3245

T3

43490

---

Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	71998335	1			T1	2837		T2	2585		T3	48218
auto[0]	triple_byte_access	1328398	1			T1	59		T2	112		T3	956
auto[0]	halfword_access	2087599	1			T1	102		T2	169		T3	1488
auto[0]	byte_access	3059902	1			T1	118		T2	232		T3	1997
auto[0]	zero_access	1072541	1			T1	27		T2	71		T3	508
auto[1]	word_access	72809164	1			T1	2929		T2	2647		T3	39497
auto[1]	triple_byte_access	1459838	1			T1	74		T2	122		T3	796
auto[1]	halfword_access	2184758	1			T1	92		T2	178		T3	1178
auto[1]	byte_access	2912573	1			T1	130		T2	233		T3	1614
auto[1]	zero_access	728925	1			T1	31		T2	65		T3	405