| T794 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2870252328 |
|
|
Apr 21 02:42:42 PM PDT 24 |
Apr 21 02:48:03 PM PDT 24 |
26607658448 ps |
| T795 |
/workspace/coverage/default/38.sram_ctrl_bijection.1945372367 |
|
|
Apr 21 02:46:09 PM PDT 24 |
Apr 21 03:31:41 PM PDT 24 |
460350543279 ps |
| T796 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.249144142 |
|
|
Apr 21 02:46:08 PM PDT 24 |
Apr 21 02:46:19 PM PDT 24 |
733472943 ps |
| T797 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2172824720 |
|
|
Apr 21 02:45:06 PM PDT 24 |
Apr 21 02:47:28 PM PDT 24 |
1635515997 ps |
| T798 |
/workspace/coverage/default/26.sram_ctrl_executable.1475749991 |
|
|
Apr 21 02:43:31 PM PDT 24 |
Apr 21 02:51:23 PM PDT 24 |
26126245669 ps |
| T799 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1565773192 |
|
|
Apr 21 02:45:31 PM PDT 24 |
Apr 21 02:47:02 PM PDT 24 |
878267263 ps |
| T800 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3434367117 |
|
|
Apr 21 02:41:00 PM PDT 24 |
Apr 21 02:45:49 PM PDT 24 |
12259739970 ps |
| T801 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3886400446 |
|
|
Apr 21 02:40:36 PM PDT 24 |
Apr 21 02:42:41 PM PDT 24 |
14829097338 ps |
| T802 |
/workspace/coverage/default/11.sram_ctrl_regwen.3582074287 |
|
|
Apr 21 02:39:48 PM PDT 24 |
Apr 21 03:11:54 PM PDT 24 |
3981586430 ps |
| T803 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3260020592 |
|
|
Apr 21 02:40:23 PM PDT 24 |
Apr 21 02:40:51 PM PDT 24 |
4030024267 ps |
| T804 |
/workspace/coverage/default/4.sram_ctrl_smoke.1258640041 |
|
|
Apr 21 02:37:39 PM PDT 24 |
Apr 21 02:40:05 PM PDT 24 |
4306779412 ps |
| T805 |
/workspace/coverage/default/37.sram_ctrl_alert_test.1858368114 |
|
|
Apr 21 02:46:11 PM PDT 24 |
Apr 21 02:46:12 PM PDT 24 |
129258135 ps |
| T806 |
/workspace/coverage/default/33.sram_ctrl_bijection.790458123 |
|
|
Apr 21 02:45:03 PM PDT 24 |
Apr 21 02:57:20 PM PDT 24 |
135322250951 ps |
| T807 |
/workspace/coverage/default/45.sram_ctrl_alert_test.165324087 |
|
|
Apr 21 02:47:59 PM PDT 24 |
Apr 21 02:48:00 PM PDT 24 |
12531988 ps |
| T808 |
/workspace/coverage/default/28.sram_ctrl_executable.1180237457 |
|
|
Apr 21 02:43:57 PM PDT 24 |
Apr 21 02:55:26 PM PDT 24 |
9123762935 ps |
| T809 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.3430083203 |
|
|
Apr 21 02:47:01 PM PDT 24 |
Apr 21 02:58:15 PM PDT 24 |
39704188260 ps |
| T810 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3302910268 |
|
|
Apr 21 02:48:02 PM PDT 24 |
Apr 21 02:49:30 PM PDT 24 |
18511255196 ps |
| T811 |
/workspace/coverage/default/33.sram_ctrl_partial_access.1372177031 |
|
|
Apr 21 02:45:06 PM PDT 24 |
Apr 21 02:46:56 PM PDT 24 |
1236856882 ps |
| T812 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.800741681 |
|
|
Apr 21 02:42:38 PM PDT 24 |
Apr 21 02:43:58 PM PDT 24 |
48573908023 ps |
| T813 |
/workspace/coverage/default/46.sram_ctrl_regwen.1759005806 |
|
|
Apr 21 02:48:08 PM PDT 24 |
Apr 21 02:49:25 PM PDT 24 |
1647271285 ps |
| T814 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.242932524 |
|
|
Apr 21 02:42:51 PM PDT 24 |
Apr 21 02:45:47 PM PDT 24 |
8371715565 ps |
| T815 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.144669755 |
|
|
Apr 21 02:46:46 PM PDT 24 |
Apr 21 02:51:53 PM PDT 24 |
20037728223 ps |
| T816 |
/workspace/coverage/default/33.sram_ctrl_regwen.2999312697 |
|
|
Apr 21 02:45:11 PM PDT 24 |
Apr 21 03:14:49 PM PDT 24 |
142681614442 ps |
| T817 |
/workspace/coverage/default/34.sram_ctrl_regwen.102144063 |
|
|
Apr 21 02:45:21 PM PDT 24 |
Apr 21 03:07:24 PM PDT 24 |
57158696949 ps |
| T818 |
/workspace/coverage/default/42.sram_ctrl_regwen.1109629706 |
|
|
Apr 21 02:47:12 PM PDT 24 |
Apr 21 02:58:56 PM PDT 24 |
32798504192 ps |
| T819 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.3869584798 |
|
|
Apr 21 02:42:36 PM PDT 24 |
Apr 21 02:45:29 PM PDT 24 |
21552898680 ps |
| T820 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.3736843622 |
|
|
Apr 21 02:41:36 PM PDT 24 |
Apr 21 02:42:44 PM PDT 24 |
5306939287 ps |
| T821 |
/workspace/coverage/default/10.sram_ctrl_executable.3221985069 |
|
|
Apr 21 02:39:29 PM PDT 24 |
Apr 21 03:14:35 PM PDT 24 |
27409133776 ps |
| T822 |
/workspace/coverage/default/27.sram_ctrl_partial_access.717353597 |
|
|
Apr 21 02:43:39 PM PDT 24 |
Apr 21 02:44:34 PM PDT 24 |
4051716725 ps |
| T823 |
/workspace/coverage/default/1.sram_ctrl_regwen.1046296199 |
|
|
Apr 21 02:36:56 PM PDT 24 |
Apr 21 02:46:52 PM PDT 24 |
63250164617 ps |
| T824 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.923987403 |
|
|
Apr 21 02:38:08 PM PDT 24 |
Apr 21 02:40:15 PM PDT 24 |
2021444328 ps |
| T825 |
/workspace/coverage/default/18.sram_ctrl_stress_all.3086958014 |
|
|
Apr 21 02:41:43 PM PDT 24 |
Apr 21 03:52:31 PM PDT 24 |
165341750315 ps |
| T826 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.1610431807 |
|
|
Apr 21 02:40:59 PM PDT 24 |
Apr 21 02:41:05 PM PDT 24 |
4179423172 ps |
| T827 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1509189156 |
|
|
Apr 21 02:43:44 PM PDT 24 |
Apr 21 02:45:31 PM PDT 24 |
6891683118 ps |
| T828 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1790336429 |
|
|
Apr 21 02:44:28 PM PDT 24 |
Apr 21 02:44:40 PM PDT 24 |
659002509 ps |
| T829 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.575093076 |
|
|
Apr 21 02:45:19 PM PDT 24 |
Apr 21 02:46:08 PM PDT 24 |
7754121428 ps |
| T830 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.3942838474 |
|
|
Apr 21 02:47:00 PM PDT 24 |
Apr 21 02:47:03 PM PDT 24 |
663802370 ps |
| T831 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1342608275 |
|
|
Apr 21 02:36:58 PM PDT 24 |
Apr 21 02:37:02 PM PDT 24 |
1412993851 ps |
| T832 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1428259793 |
|
|
Apr 21 02:46:19 PM PDT 24 |
Apr 21 03:02:37 PM PDT 24 |
56574496119 ps |
| T833 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.2169532966 |
|
|
Apr 21 02:48:37 PM PDT 24 |
Apr 21 02:52:50 PM PDT 24 |
4430429632 ps |
| T834 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3445455211 |
|
|
Apr 21 02:47:50 PM PDT 24 |
Apr 21 02:48:18 PM PDT 24 |
5777586581 ps |
| T835 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1484103474 |
|
|
Apr 21 02:38:29 PM PDT 24 |
Apr 21 02:43:19 PM PDT 24 |
17943892791 ps |
| T836 |
/workspace/coverage/default/45.sram_ctrl_regwen.3284786882 |
|
|
Apr 21 02:47:56 PM PDT 24 |
Apr 21 03:06:35 PM PDT 24 |
69768583745 ps |
| T837 |
/workspace/coverage/default/45.sram_ctrl_executable.154352637 |
|
|
Apr 21 02:47:50 PM PDT 24 |
Apr 21 02:57:12 PM PDT 24 |
52240339456 ps |
| T838 |
/workspace/coverage/default/11.sram_ctrl_executable.2660751566 |
|
|
Apr 21 02:39:47 PM PDT 24 |
Apr 21 02:52:07 PM PDT 24 |
89906799624 ps |
| T839 |
/workspace/coverage/default/15.sram_ctrl_partial_access.3766185852 |
|
|
Apr 21 02:40:46 PM PDT 24 |
Apr 21 02:41:04 PM PDT 24 |
2651568191 ps |
| T840 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3634791641 |
|
|
Apr 21 02:47:35 PM PDT 24 |
Apr 21 02:55:55 PM PDT 24 |
36332714195 ps |
| T841 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.947073269 |
|
|
Apr 21 02:37:32 PM PDT 24 |
Apr 21 02:40:01 PM PDT 24 |
10571555950 ps |
| T842 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.2209348730 |
|
|
Apr 21 02:41:39 PM PDT 24 |
Apr 21 02:41:43 PM PDT 24 |
1464471502 ps |
| T843 |
/workspace/coverage/default/0.sram_ctrl_smoke.536883866 |
|
|
Apr 21 02:36:30 PM PDT 24 |
Apr 21 02:36:50 PM PDT 24 |
2370935606 ps |
| T844 |
/workspace/coverage/default/4.sram_ctrl_alert_test.3899025255 |
|
|
Apr 21 02:37:55 PM PDT 24 |
Apr 21 02:37:56 PM PDT 24 |
20213050 ps |
| T845 |
/workspace/coverage/default/25.sram_ctrl_partial_access.2608586891 |
|
|
Apr 21 02:43:11 PM PDT 24 |
Apr 21 02:43:30 PM PDT 24 |
1160313447 ps |
| T846 |
/workspace/coverage/default/31.sram_ctrl_bijection.2501614029 |
|
|
Apr 21 02:44:37 PM PDT 24 |
Apr 21 03:02:33 PM PDT 24 |
59028979980 ps |
| T847 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.207551697 |
|
|
Apr 21 02:40:00 PM PDT 24 |
Apr 21 02:45:07 PM PDT 24 |
48264752598 ps |
| T848 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.3909660827 |
|
|
Apr 21 02:42:58 PM PDT 24 |
Apr 21 02:44:09 PM PDT 24 |
9658388053 ps |
| T849 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.4159359073 |
|
|
Apr 21 02:36:51 PM PDT 24 |
Apr 21 02:43:10 PM PDT 24 |
21673884459 ps |
| T850 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2684487210 |
|
|
Apr 21 02:44:20 PM PDT 24 |
Apr 21 02:45:55 PM PDT 24 |
1549173743 ps |
| T851 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3558222723 |
|
|
Apr 21 02:36:33 PM PDT 24 |
Apr 21 02:37:44 PM PDT 24 |
1210311188 ps |
| T852 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.2397602603 |
|
|
Apr 21 02:46:23 PM PDT 24 |
Apr 21 02:48:56 PM PDT 24 |
27484419461 ps |
| T853 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1502496932 |
|
|
Apr 21 02:43:07 PM PDT 24 |
Apr 21 02:43:46 PM PDT 24 |
1332981499 ps |
| T854 |
/workspace/coverage/default/17.sram_ctrl_executable.1231962780 |
|
|
Apr 21 02:41:24 PM PDT 24 |
Apr 21 02:47:42 PM PDT 24 |
7419971243 ps |
| T855 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.1847472109 |
|
|
Apr 21 02:37:47 PM PDT 24 |
Apr 21 02:38:52 PM PDT 24 |
1512837440 ps |
| T856 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.1132530995 |
|
|
Apr 21 02:44:58 PM PDT 24 |
Apr 21 02:47:00 PM PDT 24 |
2744204847 ps |
| T857 |
/workspace/coverage/default/14.sram_ctrl_alert_test.698484856 |
|
|
Apr 21 02:40:40 PM PDT 24 |
Apr 21 02:40:41 PM PDT 24 |
92204655 ps |
| T858 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3371698401 |
|
|
Apr 21 02:44:09 PM PDT 24 |
Apr 21 02:45:33 PM PDT 24 |
41965946781 ps |
| T859 |
/workspace/coverage/default/34.sram_ctrl_partial_access.176567357 |
|
|
Apr 21 02:45:17 PM PDT 24 |
Apr 21 02:47:39 PM PDT 24 |
1849006807 ps |
| T860 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2844235165 |
|
|
Apr 21 02:41:18 PM PDT 24 |
Apr 21 02:47:41 PM PDT 24 |
18398078866 ps |
| T861 |
/workspace/coverage/default/40.sram_ctrl_alert_test.2447093552 |
|
|
Apr 21 02:46:53 PM PDT 24 |
Apr 21 02:46:54 PM PDT 24 |
14869493 ps |
| T862 |
/workspace/coverage/default/14.sram_ctrl_executable.1304123043 |
|
|
Apr 21 02:40:33 PM PDT 24 |
Apr 21 02:50:03 PM PDT 24 |
13357453497 ps |
| T863 |
/workspace/coverage/default/17.sram_ctrl_partial_access.1788904945 |
|
|
Apr 21 02:41:19 PM PDT 24 |
Apr 21 02:41:37 PM PDT 24 |
1086761199 ps |
| T864 |
/workspace/coverage/default/13.sram_ctrl_smoke.2888753946 |
|
|
Apr 21 02:40:06 PM PDT 24 |
Apr 21 02:40:52 PM PDT 24 |
1065737231 ps |
| T865 |
/workspace/coverage/default/30.sram_ctrl_smoke.447759361 |
|
|
Apr 21 02:44:15 PM PDT 24 |
Apr 21 02:45:31 PM PDT 24 |
1321122684 ps |
| T866 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.3981920290 |
|
|
Apr 21 02:42:15 PM PDT 24 |
Apr 21 02:43:05 PM PDT 24 |
3363092997 ps |
| T867 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.4286535105 |
|
|
Apr 21 02:42:14 PM PDT 24 |
Apr 21 02:44:36 PM PDT 24 |
11740758853 ps |
| T868 |
/workspace/coverage/default/0.sram_ctrl_regwen.355618068 |
|
|
Apr 21 02:36:42 PM PDT 24 |
Apr 21 02:42:10 PM PDT 24 |
19361474820 ps |
| T869 |
/workspace/coverage/default/36.sram_ctrl_partial_access.1516168486 |
|
|
Apr 21 02:45:49 PM PDT 24 |
Apr 21 02:45:59 PM PDT 24 |
2487353566 ps |
| T870 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3641507074 |
|
|
Apr 21 02:44:57 PM PDT 24 |
Apr 21 02:45:35 PM PDT 24 |
1023540237 ps |
| T871 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.4284812923 |
|
|
Apr 21 02:41:47 PM PDT 24 |
Apr 21 02:42:48 PM PDT 24 |
5190825501 ps |
| T872 |
/workspace/coverage/default/19.sram_ctrl_regwen.3783816920 |
|
|
Apr 21 02:41:50 PM PDT 24 |
Apr 21 02:54:03 PM PDT 24 |
11518184678 ps |
| T873 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.1227258711 |
|
|
Apr 21 02:40:25 PM PDT 24 |
Apr 21 03:03:22 PM PDT 24 |
21853480044 ps |
| T874 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2001537412 |
|
|
Apr 21 02:43:16 PM PDT 24 |
Apr 21 03:07:57 PM PDT 24 |
15444907453 ps |
| T875 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.2045500024 |
|
|
Apr 21 02:46:53 PM PDT 24 |
Apr 21 03:28:16 PM PDT 24 |
104168196763 ps |
| T876 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3539927229 |
|
|
Apr 21 02:46:59 PM PDT 24 |
Apr 21 02:47:08 PM PDT 24 |
772267735 ps |
| T877 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3893907734 |
|
|
Apr 21 02:36:35 PM PDT 24 |
Apr 21 02:38:20 PM PDT 24 |
1604210424 ps |
| T878 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.2976787188 |
|
|
Apr 21 02:39:41 PM PDT 24 |
Apr 21 02:40:02 PM PDT 24 |
6330827932 ps |
| T879 |
/workspace/coverage/default/35.sram_ctrl_regwen.896186963 |
|
|
Apr 21 02:45:33 PM PDT 24 |
Apr 21 03:11:18 PM PDT 24 |
39521641585 ps |
| T880 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.1860480858 |
|
|
Apr 21 02:41:15 PM PDT 24 |
Apr 21 02:45:43 PM PDT 24 |
15765627859 ps |
| T881 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.2519933562 |
|
|
Apr 21 02:45:36 PM PDT 24 |
Apr 21 02:47:05 PM PDT 24 |
14544340388 ps |
| T882 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2883659165 |
|
|
Apr 21 02:37:15 PM PDT 24 |
Apr 21 02:37:31 PM PDT 24 |
1705523126 ps |
| T883 |
/workspace/coverage/default/7.sram_ctrl_regwen.3007349258 |
|
|
Apr 21 02:38:33 PM PDT 24 |
Apr 21 02:54:12 PM PDT 24 |
3086307876 ps |
| T884 |
/workspace/coverage/default/27.sram_ctrl_stress_all.1538446302 |
|
|
Apr 21 02:43:48 PM PDT 24 |
Apr 21 04:44:44 PM PDT 24 |
471092177158 ps |
| T885 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.376132599 |
|
|
Apr 21 02:42:42 PM PDT 24 |
Apr 21 02:43:03 PM PDT 24 |
709164720 ps |
| T886 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2560837620 |
|
|
Apr 21 02:47:32 PM PDT 24 |
Apr 21 02:47:33 PM PDT 24 |
40198887 ps |
| T887 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2028124986 |
|
|
Apr 21 02:42:45 PM PDT 24 |
Apr 21 02:43:04 PM PDT 24 |
693587301 ps |
| T888 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.2479267785 |
|
|
Apr 21 02:37:23 PM PDT 24 |
Apr 21 02:39:22 PM PDT 24 |
1579319812 ps |
| T889 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.3377164672 |
|
|
Apr 21 02:39:12 PM PDT 24 |
Apr 21 02:43:22 PM PDT 24 |
4066935882 ps |
| T890 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.3473609940 |
|
|
Apr 21 02:41:23 PM PDT 24 |
Apr 21 03:00:01 PM PDT 24 |
57523573807 ps |
| T891 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2604662821 |
|
|
Apr 21 02:47:18 PM PDT 24 |
Apr 21 02:47:46 PM PDT 24 |
3947233080 ps |
| T892 |
/workspace/coverage/default/37.sram_ctrl_partial_access.1961367452 |
|
|
Apr 21 02:46:00 PM PDT 24 |
Apr 21 02:46:30 PM PDT 24 |
910427118 ps |
| T893 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.170550180 |
|
|
Apr 21 02:38:20 PM PDT 24 |
Apr 21 02:43:11 PM PDT 24 |
28712210067 ps |
| T894 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3071456899 |
|
|
Apr 21 02:40:15 PM PDT 24 |
Apr 21 03:04:38 PM PDT 24 |
54225424192 ps |
| T895 |
/workspace/coverage/default/33.sram_ctrl_alert_test.3644149876 |
|
|
Apr 21 02:45:14 PM PDT 24 |
Apr 21 02:45:15 PM PDT 24 |
153805754 ps |
| T896 |
/workspace/coverage/default/27.sram_ctrl_regwen.3068301004 |
|
|
Apr 21 02:43:42 PM PDT 24 |
Apr 21 03:03:02 PM PDT 24 |
29236544448 ps |
| T897 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.1281948232 |
|
|
Apr 21 02:47:46 PM PDT 24 |
Apr 21 02:49:39 PM PDT 24 |
803186046 ps |
| T898 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2324383857 |
|
|
Apr 21 02:40:09 PM PDT 24 |
Apr 21 02:43:29 PM PDT 24 |
4824960697 ps |
| T899 |
/workspace/coverage/default/24.sram_ctrl_stress_all.2640210857 |
|
|
Apr 21 02:43:08 PM PDT 24 |
Apr 21 04:05:21 PM PDT 24 |
406200830945 ps |
| T900 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.2334695208 |
|
|
Apr 21 02:48:06 PM PDT 24 |
Apr 21 02:50:32 PM PDT 24 |
1148344524 ps |
| T901 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.822937976 |
|
|
Apr 21 02:46:04 PM PDT 24 |
Apr 21 03:11:10 PM PDT 24 |
69892811672 ps |
| T902 |
/workspace/coverage/default/40.sram_ctrl_executable.3315569135 |
|
|
Apr 21 02:46:42 PM PDT 24 |
Apr 21 03:11:27 PM PDT 24 |
28339901505 ps |
| T903 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3208547557 |
|
|
Apr 21 02:36:43 PM PDT 24 |
Apr 21 03:06:10 PM PDT 24 |
61411162847 ps |
| T904 |
/workspace/coverage/default/29.sram_ctrl_regwen.2939877218 |
|
|
Apr 21 02:44:10 PM PDT 24 |
Apr 21 02:46:31 PM PDT 24 |
3223802506 ps |
| T905 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.446879755 |
|
|
Apr 21 02:47:13 PM PDT 24 |
Apr 21 02:49:31 PM PDT 24 |
21913669843 ps |
| T906 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3188576256 |
|
|
Apr 21 02:39:26 PM PDT 24 |
Apr 21 02:41:07 PM PDT 24 |
16276846972 ps |
| T907 |
/workspace/coverage/default/39.sram_ctrl_regwen.4157064136 |
|
|
Apr 21 02:46:30 PM PDT 24 |
Apr 21 02:47:57 PM PDT 24 |
3087425833 ps |
| T908 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1543670060 |
|
|
Apr 21 02:45:13 PM PDT 24 |
Apr 21 02:47:14 PM PDT 24 |
7040099818 ps |
| T909 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1611557408 |
|
|
Apr 21 02:48:11 PM PDT 24 |
Apr 21 02:48:51 PM PDT 24 |
1159662623 ps |
| T910 |
/workspace/coverage/default/11.sram_ctrl_smoke.3569025784 |
|
|
Apr 21 02:39:33 PM PDT 24 |
Apr 21 02:39:55 PM PDT 24 |
9096870063 ps |
| T911 |
/workspace/coverage/default/47.sram_ctrl_smoke.871283649 |
|
|
Apr 21 02:48:14 PM PDT 24 |
Apr 21 02:48:23 PM PDT 24 |
1481410572 ps |
| T912 |
/workspace/coverage/default/39.sram_ctrl_stress_all.4042770408 |
|
|
Apr 21 02:46:40 PM PDT 24 |
Apr 21 04:38:01 PM PDT 24 |
44526433496 ps |
| T913 |
/workspace/coverage/default/46.sram_ctrl_stress_all.3369854975 |
|
|
Apr 21 02:48:11 PM PDT 24 |
Apr 21 05:23:29 PM PDT 24 |
109776529380 ps |
| T914 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2812361980 |
|
|
Apr 21 02:47:36 PM PDT 24 |
Apr 21 02:51:03 PM PDT 24 |
42307397452 ps |
| T915 |
/workspace/coverage/default/15.sram_ctrl_stress_all.2948718821 |
|
|
Apr 21 02:40:55 PM PDT 24 |
Apr 21 05:00:11 PM PDT 24 |
45933110478 ps |
| T916 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.2902754870 |
|
|
Apr 21 02:37:53 PM PDT 24 |
Apr 21 02:41:12 PM PDT 24 |
11199702521 ps |
| T917 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2131732735 |
|
|
Apr 21 02:38:55 PM PDT 24 |
Apr 21 02:41:20 PM PDT 24 |
4527124851 ps |
| T918 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.1398861972 |
|
|
Apr 21 02:43:03 PM PDT 24 |
Apr 21 02:45:43 PM PDT 24 |
41383316350 ps |
| T919 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.2713164372 |
|
|
Apr 21 02:45:11 PM PDT 24 |
Apr 21 02:49:26 PM PDT 24 |
3947142487 ps |
| T920 |
/workspace/coverage/default/1.sram_ctrl_smoke.1379949246 |
|
|
Apr 21 02:36:52 PM PDT 24 |
Apr 21 02:37:15 PM PDT 24 |
3058906942 ps |
| T921 |
/workspace/coverage/default/38.sram_ctrl_partial_access.2594607312 |
|
|
Apr 21 02:46:13 PM PDT 24 |
Apr 21 02:46:29 PM PDT 24 |
558946801 ps |
| T922 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.1118506441 |
|
|
Apr 21 02:43:41 PM PDT 24 |
Apr 21 02:44:55 PM PDT 24 |
11485294135 ps |
| T923 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2863751755 |
|
|
Apr 21 02:43:20 PM PDT 24 |
Apr 21 02:59:07 PM PDT 24 |
50063513828 ps |
| T924 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.356197293 |
|
|
Apr 21 02:40:51 PM PDT 24 |
Apr 21 02:41:52 PM PDT 24 |
736988808 ps |
| T925 |
/workspace/coverage/default/41.sram_ctrl_bijection.1180206273 |
|
|
Apr 21 02:46:54 PM PDT 24 |
Apr 21 02:54:19 PM PDT 24 |
6923576920 ps |
| T926 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.2509405640 |
|
|
Apr 21 02:37:47 PM PDT 24 |
Apr 21 02:38:42 PM PDT 24 |
52210488238 ps |
| T927 |
/workspace/coverage/default/22.sram_ctrl_regwen.363719629 |
|
|
Apr 21 02:42:35 PM PDT 24 |
Apr 21 03:02:59 PM PDT 24 |
60564413840 ps |
| T928 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3467253469 |
|
|
Apr 21 02:42:18 PM PDT 24 |
Apr 21 02:43:20 PM PDT 24 |
1565556245 ps |
| T929 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.2896861158 |
|
|
Apr 21 02:43:14 PM PDT 24 |
Apr 21 02:44:45 PM PDT 24 |
10570289996 ps |
| T930 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.1251187796 |
|
|
Apr 21 02:44:02 PM PDT 24 |
Apr 21 02:51:28 PM PDT 24 |
7938396806 ps |
| T931 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.944473871 |
|
|
Apr 21 02:39:11 PM PDT 24 |
Apr 21 02:39:15 PM PDT 24 |
344377001 ps |
| T932 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.1450726319 |
|
|
Apr 21 02:44:45 PM PDT 24 |
Apr 21 02:49:22 PM PDT 24 |
14058451876 ps |
| T933 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.2849992194 |
|
|
Apr 21 02:45:31 PM PDT 24 |
Apr 21 02:46:31 PM PDT 24 |
747105262 ps |
| T934 |
/workspace/coverage/default/20.sram_ctrl_executable.1761346659 |
|
|
Apr 21 02:42:07 PM PDT 24 |
Apr 21 02:53:41 PM PDT 24 |
5503281803 ps |
| T935 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.316468852 |
|
|
Apr 21 02:41:36 PM PDT 24 |
Apr 21 02:42:36 PM PDT 24 |
78307679212 ps |
| T936 |
/workspace/coverage/default/21.sram_ctrl_smoke.1177386342 |
|
|
Apr 21 02:42:10 PM PDT 24 |
Apr 21 02:42:30 PM PDT 24 |
1741401222 ps |
| T937 |
/workspace/coverage/default/9.sram_ctrl_executable.148593131 |
|
|
Apr 21 02:39:12 PM PDT 24 |
Apr 21 03:29:44 PM PDT 24 |
91563722040 ps |
| T938 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3139039053 |
|
|
Apr 21 02:38:33 PM PDT 24 |
Apr 21 02:39:31 PM PDT 24 |
47785114434 ps |
| T939 |
/workspace/coverage/default/42.sram_ctrl_alert_test.3239671068 |
|
|
Apr 21 02:47:17 PM PDT 24 |
Apr 21 02:47:18 PM PDT 24 |
52509885 ps |
| T940 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.3245772272 |
|
|
Apr 21 02:37:22 PM PDT 24 |
Apr 21 02:39:55 PM PDT 24 |
16351064164 ps |
| T941 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.875751817 |
|
|
Apr 21 02:48:04 PM PDT 24 |
Apr 21 02:53:06 PM PDT 24 |
23459710153 ps |
| T942 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4053180568 |
|
|
Apr 21 02:40:50 PM PDT 24 |
Apr 21 02:42:46 PM PDT 24 |
768933893 ps |
| T943 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.2466650973 |
|
|
Apr 21 02:46:04 PM PDT 24 |
Apr 21 02:46:31 PM PDT 24 |
4636513477 ps |
| T944 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.379705753 |
|
|
Apr 21 01:01:29 PM PDT 24 |
Apr 21 01:01:34 PM PDT 24 |
426504194 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3203959610 |
|
|
Apr 21 01:01:21 PM PDT 24 |
Apr 21 01:01:23 PM PDT 24 |
249614436 ps |
| T57 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2501673871 |
|
|
Apr 21 01:01:36 PM PDT 24 |
Apr 21 01:02:30 PM PDT 24 |
14669165007 ps |
| T945 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2670413982 |
|
|
Apr 21 01:01:35 PM PDT 24 |
Apr 21 01:01:39 PM PDT 24 |
358910881 ps |
| T98 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.789536671 |
|
|
Apr 21 01:01:28 PM PDT 24 |
Apr 21 01:01:31 PM PDT 24 |
221453707 ps |
| T946 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.95701016 |
|
|
Apr 21 01:01:44 PM PDT 24 |
Apr 21 01:01:48 PM PDT 24 |
707339399 ps |
| T58 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.181752874 |
|
|
Apr 21 01:01:32 PM PDT 24 |
Apr 21 01:02:20 PM PDT 24 |
7209185927 ps |
| T99 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2724961539 |
|
|
Apr 21 01:01:30 PM PDT 24 |
Apr 21 01:01:33 PM PDT 24 |
275020006 ps |
| T59 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.458050792 |
|
|
Apr 21 01:01:22 PM PDT 24 |
Apr 21 01:01:23 PM PDT 24 |
46401749 ps |
| T60 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.729562956 |
|
|
Apr 21 01:01:30 PM PDT 24 |
Apr 21 01:01:32 PM PDT 24 |
16107385 ps |
| T947 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3909161699 |
|
|
Apr 21 01:01:24 PM PDT 24 |
Apr 21 01:01:27 PM PDT 24 |
278645712 ps |
| T948 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2342775816 |
|
|
Apr 21 01:01:29 PM PDT 24 |
Apr 21 01:01:33 PM PDT 24 |
454075934 ps |
| T100 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2163181081 |
|
|
Apr 21 01:01:42 PM PDT 24 |
Apr 21 01:01:45 PM PDT 24 |
317668950 ps |
| T61 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.86797658 |
|
|
Apr 21 01:01:32 PM PDT 24 |
Apr 21 01:02:30 PM PDT 24 |
50583157981 ps |
| T62 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1160282349 |
|
|
Apr 21 01:01:24 PM PDT 24 |
Apr 21 01:01:25 PM PDT 24 |
198672011 ps |
| T949 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1090260101 |
|
|
Apr 21 01:01:31 PM PDT 24 |
Apr 21 01:01:34 PM PDT 24 |
85170860 ps |
| T87 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3522426690 |
|
|
Apr 21 01:01:33 PM PDT 24 |
Apr 21 01:01:35 PM PDT 24 |
51825610 ps |
| T950 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3473797297 |
|
|
Apr 21 01:01:32 PM PDT 24 |
Apr 21 01:01:37 PM PDT 24 |
362547676 ps |
| T951 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3677494069 |
|
|
Apr 21 01:01:48 PM PDT 24 |
Apr 21 01:01:52 PM PDT 24 |
70341067 ps |
| T63 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3297381869 |
|
|
Apr 21 01:01:30 PM PDT 24 |
Apr 21 01:01:32 PM PDT 24 |
18590541 ps |
| T952 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1257129395 |
|
|
Apr 21 01:01:28 PM PDT 24 |
Apr 21 01:01:32 PM PDT 24 |
717941164 ps |
| T124 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3858046484 |
|
|
Apr 21 01:01:37 PM PDT 24 |
Apr 21 01:01:39 PM PDT 24 |
292729547 ps |
| T97 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.90717479 |
|
|
Apr 21 01:01:28 PM PDT 24 |
Apr 21 01:01:29 PM PDT 24 |
18214719 ps |
| T64 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2940394177 |
|
|
Apr 21 01:01:31 PM PDT 24 |
Apr 21 01:01:32 PM PDT 24 |
13355922 ps |
| T88 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1657020895 |
|
|
Apr 21 01:01:39 PM PDT 24 |
Apr 21 01:01:40 PM PDT 24 |
16666857 ps |
| T953 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.651075991 |
|
|
Apr 21 01:01:40 PM PDT 24 |
Apr 21 01:01:41 PM PDT 24 |
45990218 ps |
| T120 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1079621276 |
|
|
Apr 21 01:01:20 PM PDT 24 |
Apr 21 01:01:22 PM PDT 24 |
193969018 ps |
| T65 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2627964634 |
|
|
Apr 21 01:01:22 PM PDT 24 |
Apr 21 01:01:24 PM PDT 24 |
363663269 ps |
| T66 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.158256658 |
|
|
Apr 21 01:01:24 PM PDT 24 |
Apr 21 01:01:25 PM PDT 24 |
39718969 ps |
| T954 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1223193802 |
|
|
Apr 21 01:01:21 PM PDT 24 |
Apr 21 01:01:22 PM PDT 24 |
76587061 ps |
| T119 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3641377913 |
|
|
Apr 21 01:01:37 PM PDT 24 |
Apr 21 01:01:39 PM PDT 24 |
241611715 ps |
| T89 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2043995441 |
|
|
Apr 21 01:01:29 PM PDT 24 |
Apr 21 01:01:30 PM PDT 24 |
14474593 ps |
| T955 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2109165546 |
|
|
Apr 21 01:01:34 PM PDT 24 |
Apr 21 01:01:37 PM PDT 24 |
272140233 ps |
| T125 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1544001044 |
|
|
Apr 21 01:01:37 PM PDT 24 |
Apr 21 01:01:39 PM PDT 24 |
669720469 ps |
| T956 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3494502274 |
|
|
Apr 21 01:01:23 PM PDT 24 |
Apr 21 01:01:24 PM PDT 24 |
143490932 ps |
| T67 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2407444462 |
|
|
Apr 21 01:01:29 PM PDT 24 |
Apr 21 01:02:09 PM PDT 24 |
73839499091 ps |
| T957 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2484886117 |
|
|
Apr 21 01:01:23 PM PDT 24 |
Apr 21 01:01:27 PM PDT 24 |
600829553 ps |
| T68 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1914623921 |
|
|
Apr 21 01:01:33 PM PDT 24 |
Apr 21 01:01:34 PM PDT 24 |
14064417 ps |
| T121 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3307135219 |
|
|
Apr 21 01:01:24 PM PDT 24 |
Apr 21 01:01:27 PM PDT 24 |
638524597 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.503186477 |
|
|
Apr 21 01:01:23 PM PDT 24 |
Apr 21 01:01:28 PM PDT 24 |
462334112 ps |
| T69 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.910695683 |
|
|
Apr 21 01:01:33 PM PDT 24 |
Apr 21 01:02:26 PM PDT 24 |
7335616437 ps |
| T959 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.597690353 |
|
|
Apr 21 01:01:28 PM PDT 24 |
Apr 21 01:01:29 PM PDT 24 |
14554642 ps |
| T960 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3683281273 |
|
|
Apr 21 01:01:34 PM PDT 24 |
Apr 21 01:01:37 PM PDT 24 |
187274304 ps |
| T961 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.202656836 |
|
|
Apr 21 01:01:30 PM PDT 24 |
Apr 21 01:01:32 PM PDT 24 |
29565512 ps |
| T962 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3086388572 |
|
|
Apr 21 01:01:38 PM PDT 24 |
Apr 21 01:01:40 PM PDT 24 |
41517223 ps |
| T963 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2265574452 |
|
|
Apr 21 01:01:24 PM PDT 24 |
Apr 21 01:01:25 PM PDT 24 |
37765248 ps |
| T964 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.615888614 |
|
|
Apr 21 01:01:30 PM PDT 24 |
Apr 21 01:01:31 PM PDT 24 |
39132727 ps |
| T965 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1683614326 |
|
|
Apr 21 01:01:28 PM PDT 24 |
Apr 21 01:01:29 PM PDT 24 |
56976854 ps |
| T70 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.760057313 |
|
|
Apr 21 01:01:40 PM PDT 24 |
Apr 21 01:02:06 PM PDT 24 |
7473240970 ps |
| T966 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1099490584 |
|
|
Apr 21 01:01:25 PM PDT 24 |
Apr 21 01:01:29 PM PDT 24 |
364347086 ps |
| T967 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.716421806 |
|
|
Apr 21 01:01:25 PM PDT 24 |
Apr 21 01:01:29 PM PDT 24 |
39927959 ps |
| T968 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1004673379 |
|
|
Apr 21 01:01:30 PM PDT 24 |
Apr 21 01:01:34 PM PDT 24 |
376977949 ps |
| T969 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1181711325 |
|
|
Apr 21 01:01:40 PM PDT 24 |
Apr 21 01:01:44 PM PDT 24 |
160466195 ps |
| T970 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3304674680 |
|
|
Apr 21 01:01:35 PM PDT 24 |
Apr 21 01:01:39 PM PDT 24 |
364946914 ps |
| T71 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1117811331 |
|
|
Apr 21 01:01:24 PM PDT 24 |
Apr 21 01:01:25 PM PDT 24 |
81487118 ps |
| T971 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3453258887 |
|
|
Apr 21 01:01:38 PM PDT 24 |
Apr 21 01:01:39 PM PDT 24 |
35936577 ps |
| T972 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.219146700 |
|
|
Apr 21 01:01:25 PM PDT 24 |
Apr 21 01:01:29 PM PDT 24 |
1407754548 ps |
| T129 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2336193999 |
|
|
Apr 21 01:01:26 PM PDT 24 |
Apr 21 01:01:29 PM PDT 24 |
218624074 ps |
| T72 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2946458906 |
|
|
Apr 21 01:01:16 PM PDT 24 |
Apr 21 01:01:43 PM PDT 24 |
15535045308 ps |
| T973 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.914696334 |
|
|
Apr 21 01:01:25 PM PDT 24 |
Apr 21 01:01:30 PM PDT 24 |
127425942 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1563697882 |
|
|
Apr 21 01:01:25 PM PDT 24 |
Apr 21 01:01:29 PM PDT 24 |
1486624620 ps |
| T975 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3948115286 |
|
|
Apr 21 01:01:34 PM PDT 24 |
Apr 21 01:01:38 PM PDT 24 |
727398052 ps |
| T78 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.20921822 |
|
|
Apr 21 01:01:34 PM PDT 24 |
Apr 21 01:02:27 PM PDT 24 |
7050025828 ps |
| T976 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3565975440 |
|
|
Apr 21 01:01:21 PM PDT 24 |
Apr 21 01:01:22 PM PDT 24 |
22605253 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3475746258 |
|
|
Apr 21 01:01:24 PM PDT 24 |
Apr 21 01:01:25 PM PDT 24 |
28036581 ps |
| T978 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2040828163 |
|
|
Apr 21 01:01:33 PM PDT 24 |
Apr 21 01:01:35 PM PDT 24 |
30300765 ps |
| T979 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.909722289 |
|
|
Apr 21 01:01:27 PM PDT 24 |
Apr 21 01:01:29 PM PDT 24 |
68765742 ps |
| T980 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.713495651 |
|
|
Apr 21 01:01:34 PM PDT 24 |
Apr 21 01:01:35 PM PDT 24 |
54693394 ps |
| T981 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1591479952 |
|
|
Apr 21 01:01:29 PM PDT 24 |
Apr 21 01:01:31 PM PDT 24 |
47488655 ps |
| T982 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1379278101 |
|
|
Apr 21 01:01:35 PM PDT 24 |
Apr 21 01:01:37 PM PDT 24 |
11715490 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2396806007 |
|
|
Apr 21 01:01:43 PM PDT 24 |
Apr 21 01:01:44 PM PDT 24 |
29442643 ps |
| T984 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1188969482 |
|
|
Apr 21 01:01:23 PM PDT 24 |
Apr 21 01:01:26 PM PDT 24 |
359442680 ps |
| T985 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1800097615 |
|
|
Apr 21 01:01:33 PM PDT 24 |
Apr 21 01:01:38 PM PDT 24 |
1427476456 ps |
| T986 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1084766308 |
|
|
Apr 21 01:01:32 PM PDT 24 |
Apr 21 01:01:37 PM PDT 24 |
103057986 ps |
| T987 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.807472590 |
|
|
Apr 21 01:01:29 PM PDT 24 |
Apr 21 01:01:33 PM PDT 24 |
1892484727 ps |
| T988 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2217825181 |
|
|
Apr 21 01:01:25 PM PDT 24 |
Apr 21 01:01:26 PM PDT 24 |
96015398 ps |
| T122 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2601639414 |
|
|
Apr 21 01:01:34 PM PDT 24 |
Apr 21 01:01:36 PM PDT 24 |
132745963 ps |
| T79 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1802860487 |
|
|
Apr 21 01:01:35 PM PDT 24 |
Apr 21 01:02:02 PM PDT 24 |
3784773592 ps |
| T989 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3992002891 |
|
|
Apr 21 01:01:29 PM PDT 24 |
Apr 21 01:01:33 PM PDT 24 |
711752812 ps |
| T990 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2755855518 |
|
|
Apr 21 01:01:35 PM PDT 24 |
Apr 21 01:02:34 PM PDT 24 |
29403086676 ps |
| T128 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3990712402 |
|
|
Apr 21 01:01:35 PM PDT 24 |
Apr 21 01:01:38 PM PDT 24 |
673042568 ps |
| T991 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.944047624 |
|
|
Apr 21 01:01:36 PM PDT 24 |
Apr 21 01:01:37 PM PDT 24 |
12151037 ps |
| T992 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.547331667 |
|
|
Apr 21 01:01:27 PM PDT 24 |
Apr 21 01:01:31 PM PDT 24 |
97214309 ps |
| T993 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4164509725 |
|
|
Apr 21 01:01:32 PM PDT 24 |
Apr 21 01:01:37 PM PDT 24 |
143544529 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3607128585 |
|
|
Apr 21 01:01:15 PM PDT 24 |
Apr 21 01:01:16 PM PDT 24 |
15428254 ps |
| T995 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.875085129 |
|
|
Apr 21 01:01:23 PM PDT 24 |
Apr 21 01:01:25 PM PDT 24 |
1570696958 ps |
| T996 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.674664322 |
|
|
Apr 21 01:01:31 PM PDT 24 |
Apr 21 01:01:35 PM PDT 24 |
445164940 ps |
| T80 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2004411223 |
|
|
Apr 21 01:01:21 PM PDT 24 |
Apr 21 01:02:15 PM PDT 24 |
7428280550 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4248142794 |
|
|
Apr 21 01:01:31 PM PDT 24 |
Apr 21 01:02:00 PM PDT 24 |
6835947078 ps |
| T998 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2490410713 |
|
|
Apr 21 01:01:36 PM PDT 24 |
Apr 21 01:01:37 PM PDT 24 |
55620134 ps |
| T81 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4059506673 |
|
|
Apr 21 01:01:35 PM PDT 24 |
Apr 21 01:02:12 PM PDT 24 |
73670323492 ps |
| T82 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1025175752 |
|
|
Apr 21 01:01:29 PM PDT 24 |
Apr 21 01:01:57 PM PDT 24 |
3746260918 ps |
| T83 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.303399970 |
|
|
Apr 21 01:01:28 PM PDT 24 |
Apr 21 01:02:19 PM PDT 24 |
29342101957 ps |
| T999 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2581392852 |
|
|
Apr 21 01:01:36 PM PDT 24 |
Apr 21 01:01:37 PM PDT 24 |
19090543 ps |
| T126 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2489620280 |
|
|
Apr 21 01:01:31 PM PDT 24 |
Apr 21 01:01:34 PM PDT 24 |
266786457 ps |
| T1000 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2108969012 |
|
|
Apr 21 01:01:36 PM PDT 24 |
Apr 21 01:01:37 PM PDT 24 |
17314375 ps |
| T84 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2582091534 |
|
|
Apr 21 01:01:23 PM PDT 24 |
Apr 21 01:01:24 PM PDT 24 |
60309553 ps |
| T1001 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3441052453 |
|
|
Apr 21 01:01:32 PM PDT 24 |
Apr 21 01:01:34 PM PDT 24 |
22342106 ps |
| T1002 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3445795419 |
|
|
Apr 21 01:01:30 PM PDT 24 |
Apr 21 01:02:02 PM PDT 24 |
15360578350 ps |
| T1003 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1454302509 |
|
|
Apr 21 01:01:35 PM PDT 24 |
Apr 21 01:01:40 PM PDT 24 |
1431659445 ps |