Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	362948442	1			T1	125352		T2	14284		T3	6390
instr_valid_dis	328998006	1			T1	125352		T2	14284		T3	6390
instr_en	23753923	1			T24	634058		T25	369664		T110	186380

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9717249	1			T24	36028		T25	47698		T26	97856
sram_ifetch_valid_disable	328547097	1			T1	125352		T2	14284		T3	6390
sram_ifetch_enable	24684096	1			T13	95042		T24	687430		T25	134032

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	362948442	1			T1	125352		T2	14284		T3	6390
hw_debug_en_valid_off	324269727	1			T1	125352		T2	14284		T3	6390
hw_debug_en_on	24514689	1			T13	95042		T24	89288		T25	212772

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	328547097	1			T1	125352		T2	14284		T3	6390
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	314889944	1			T1	125352		T2	14284		T3	6390
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8899804	1			T24	48718		T25	187934		T110	71206
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3655703	1			T24	19382		T25	24248		T26	33826
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1652286	1			T24	19382		T26	33826		T8	71500
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1418149	1			T25	24248		T110	1712		T127	37240
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3953830	1			T24	16646		T25	11980		T26	22742
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1147634	1			T24	5372		T26	22742		T8	10426
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2167656	1			T24	11274		T25	11980		T110	47606
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8274461	1			T24	54416		T25	67038		T26	28014
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3505431	1			T24	25698		T26	28014		T8	84332
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3400760	1			T24	28718		T25	67038		T127	43214

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10463364	1			T24	574066		T25	134032		T110	65856
lc_exec_en	12286398	1			T13	95042		T24	18226		T25	133754
valid_exec_dis	323289002	1			T1	125352		T2	14284		T3	6390
invalid_exec_dis	34401345	1			T13	95042		T24	723458		T25	181730