Name |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3769877092 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.466050771 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3543739188 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2013856192 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2470839122 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.587140034 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2994676580 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3031750689 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3672022726 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2935525290 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3878393965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.51845467 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1287938869 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.730930181 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.484584555 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.631032105 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4216577044 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2156170854 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.355546350 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1175161907 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1391523203 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.401715619 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.159872447 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1642878068 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1123968833 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4028112663 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4105603571 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.677313250 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2410722889 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3507333288 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4025743279 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.332817024 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.180295454 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2440139434 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.360018512 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.997922210 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1622583855 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3766121672 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2003523906 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.332318874 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2841322356 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3924169009 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2221161084 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3974532094 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2522547573 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.299509156 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2250606336 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1435874965 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2924162203 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3893211540 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1163837496 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.872514698 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3944643464 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.481551605 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.544921973 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4096184926 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.638948765 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3405198026 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.896622747 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3992827138 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2262491585 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1118330721 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1738800244 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1041133672 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3757925409 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2693996209 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1774975334 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3160784637 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4104164626 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2594671083 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3328653957 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3806829957 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4223270529 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.574939409 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2213884467 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4205095561 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2972243643 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3698948333 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3605980772 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3469476520 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4224784871 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2699936280 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.900141131 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1304908369 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2704260877 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2616311617 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3224076188 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3392339718 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2841365041 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1609129392 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2966362775 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1391548263 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1696046580 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1703460517 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.780049915 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3096998977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4011959103 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.859795366 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1010668465 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1656048498 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3343126109 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3000677120 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3170144864 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1200351806 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.305756421 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.480511476 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3184774276 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3611850921 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.901608570 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3991190003 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.88940804 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1100580304 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3763514862 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1851982811 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1511119100 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2515498280 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2688890278 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1483494477 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1047479108 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.850253708 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2741669599 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2852417428 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.535059580 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1161867017 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.55900767 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1026543772 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4086842572 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3081255449 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.868182469 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3338160776 |
/workspace/coverage/default/0.sram_ctrl_alert_test.1427879448 |
/workspace/coverage/default/0.sram_ctrl_bijection.3020310078 |
/workspace/coverage/default/0.sram_ctrl_executable.2355327382 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.892580499 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.648662184 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1123332747 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.260118442 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.351329558 |
/workspace/coverage/default/0.sram_ctrl_partial_access.1836626897 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1879780199 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.340653194 |
/workspace/coverage/default/0.sram_ctrl_regwen.1963072536 |
/workspace/coverage/default/0.sram_ctrl_smoke.297686754 |
/workspace/coverage/default/0.sram_ctrl_stress_all.820453386 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.929137280 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2349687093 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.812495035 |
/workspace/coverage/default/1.sram_ctrl_alert_test.920728235 |
/workspace/coverage/default/1.sram_ctrl_bijection.2769201392 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2983175200 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.3836909603 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1644568125 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.2600427486 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3549180852 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1135974008 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1057302335 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.4185980258 |
/workspace/coverage/default/1.sram_ctrl_regwen.2023954738 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.1158884076 |
/workspace/coverage/default/1.sram_ctrl_smoke.3961694951 |
/workspace/coverage/default/1.sram_ctrl_stress_all.2377357775 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1255024910 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2294930070 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3140406930 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3131129573 |
/workspace/coverage/default/10.sram_ctrl_alert_test.2335693153 |
/workspace/coverage/default/10.sram_ctrl_bijection.3312948901 |
/workspace/coverage/default/10.sram_ctrl_executable.431707842 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.4258279233 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3133219233 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2741403027 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.129327018 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.467375344 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2948149228 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1160759210 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.220312695 |
/workspace/coverage/default/10.sram_ctrl_regwen.3967683900 |
/workspace/coverage/default/10.sram_ctrl_smoke.2768991385 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1251326428 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1909471497 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2549384783 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2087985908 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2780607088 |
/workspace/coverage/default/11.sram_ctrl_alert_test.454620795 |
/workspace/coverage/default/11.sram_ctrl_bijection.4287034961 |
/workspace/coverage/default/11.sram_ctrl_executable.1672909523 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.418678571 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.2874533694 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.309713953 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.1945197772 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1343312547 |
/workspace/coverage/default/11.sram_ctrl_partial_access.1759659897 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1482175409 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2011140393 |
/workspace/coverage/default/11.sram_ctrl_regwen.878632535 |
/workspace/coverage/default/11.sram_ctrl_smoke.2192995567 |
/workspace/coverage/default/11.sram_ctrl_stress_all.491257688 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2662555596 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2457169141 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2729616352 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.713597354 |
/workspace/coverage/default/12.sram_ctrl_alert_test.2626377588 |
/workspace/coverage/default/12.sram_ctrl_bijection.1932364080 |
/workspace/coverage/default/12.sram_ctrl_executable.1658568439 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1997186022 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.364165142 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.625049777 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3177622361 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3282028916 |
/workspace/coverage/default/12.sram_ctrl_partial_access.147973235 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3587052538 |
/workspace/coverage/default/12.sram_ctrl_regwen.3092439104 |
/workspace/coverage/default/12.sram_ctrl_smoke.981578198 |
/workspace/coverage/default/12.sram_ctrl_stress_all.4074923626 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2744247672 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3388890350 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2571116029 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.150534457 |
/workspace/coverage/default/13.sram_ctrl_alert_test.2993468353 |
/workspace/coverage/default/13.sram_ctrl_bijection.860400860 |
/workspace/coverage/default/13.sram_ctrl_executable.3633322401 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.1039821990 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.1597854336 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.169964942 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.2930340781 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.660831552 |
/workspace/coverage/default/13.sram_ctrl_partial_access.2257744416 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1052608595 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1164630971 |
/workspace/coverage/default/13.sram_ctrl_regwen.56156674 |
/workspace/coverage/default/13.sram_ctrl_smoke.3056011755 |
/workspace/coverage/default/13.sram_ctrl_stress_all.2896183612 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.318392295 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.264427317 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1710622847 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.1941459849 |
/workspace/coverage/default/14.sram_ctrl_alert_test.1021420915 |
/workspace/coverage/default/14.sram_ctrl_bijection.2212760278 |
/workspace/coverage/default/14.sram_ctrl_executable.658160841 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.2128196164 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.2034676602 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1999879386 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3123375707 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.4070455532 |
/workspace/coverage/default/14.sram_ctrl_partial_access.1201256806 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3205769166 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2210814248 |
/workspace/coverage/default/14.sram_ctrl_regwen.2412402664 |
/workspace/coverage/default/14.sram_ctrl_smoke.176389792 |
/workspace/coverage/default/14.sram_ctrl_stress_all.4214976303 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1179233268 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.210442699 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2963454594 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.3287074401 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1686583370 |
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/workspace/coverage/default/44.sram_ctrl_multiple_keys.2016514593 |
/workspace/coverage/default/44.sram_ctrl_partial_access.1267454357 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1756533970 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3520748711 |
/workspace/coverage/default/44.sram_ctrl_regwen.533218413 |
/workspace/coverage/default/44.sram_ctrl_smoke.2172084966 |
/workspace/coverage/default/44.sram_ctrl_stress_all.628116982 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.125615436 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1568907776 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.259209236 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3700970080 |
/workspace/coverage/default/45.sram_ctrl_alert_test.107121598 |
/workspace/coverage/default/45.sram_ctrl_bijection.1566844959 |
/workspace/coverage/default/45.sram_ctrl_executable.2319511934 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.358984088 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.486822170 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2952740998 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.2161135051 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3244176288 |
/workspace/coverage/default/45.sram_ctrl_partial_access.1041123794 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3984749428 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1128939352 |
/workspace/coverage/default/45.sram_ctrl_regwen.4033486140 |
/workspace/coverage/default/45.sram_ctrl_smoke.4069346338 |
/workspace/coverage/default/45.sram_ctrl_stress_all.1100174555 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.1936973632 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1438073609 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1527329016 |
/workspace/coverage/default/46.sram_ctrl_alert_test.1711368857 |
/workspace/coverage/default/46.sram_ctrl_bijection.3918815829 |
/workspace/coverage/default/46.sram_ctrl_executable.4144340168 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.374108639 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.1861655545 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1392135897 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.2081323819 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1518686845 |
/workspace/coverage/default/46.sram_ctrl_partial_access.1838132102 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1653406843 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2078752277 |
/workspace/coverage/default/46.sram_ctrl_regwen.2703161331 |
/workspace/coverage/default/46.sram_ctrl_smoke.3601867981 |
/workspace/coverage/default/46.sram_ctrl_stress_all.1842122892 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2782439883 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2581170861 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3328374539 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3103460930 |
/workspace/coverage/default/47.sram_ctrl_alert_test.317640817 |
/workspace/coverage/default/47.sram_ctrl_bijection.447936686 |
/workspace/coverage/default/47.sram_ctrl_executable.413840889 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1635587715 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.1061981793 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.4060771143 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.1241211807 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2490884695 |
/workspace/coverage/default/47.sram_ctrl_partial_access.3174078901 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2898020668 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2951159743 |
/workspace/coverage/default/47.sram_ctrl_regwen.2742213915 |
/workspace/coverage/default/47.sram_ctrl_smoke.881068759 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3158662104 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1429793361 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3656642087 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.93216353 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2629878905 |
/workspace/coverage/default/48.sram_ctrl_alert_test.212878334 |
/workspace/coverage/default/48.sram_ctrl_bijection.3002372794 |
/workspace/coverage/default/48.sram_ctrl_executable.698831928 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2498624562 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3136977251 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.251068439 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.1706495813 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1085151422 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2758314390 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4281034564 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.4253430906 |
/workspace/coverage/default/48.sram_ctrl_regwen.508109908 |
/workspace/coverage/default/48.sram_ctrl_smoke.2588517244 |
/workspace/coverage/default/48.sram_ctrl_stress_all.1042819404 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.570413242 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.4227352344 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3069568786 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.822275315 |
/workspace/coverage/default/49.sram_ctrl_alert_test.3975645205 |
/workspace/coverage/default/49.sram_ctrl_bijection.237596304 |
/workspace/coverage/default/49.sram_ctrl_executable.3680495295 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2974332482 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.3430197802 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1932782256 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1455038520 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.538393221 |
/workspace/coverage/default/49.sram_ctrl_partial_access.91877213 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1625359364 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2334612526 |
/workspace/coverage/default/49.sram_ctrl_regwen.2829459883 |
/workspace/coverage/default/49.sram_ctrl_smoke.1856159101 |
/workspace/coverage/default/49.sram_ctrl_stress_all.2307494805 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.153426189 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2339636214 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.690716927 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2128341094 |
/workspace/coverage/default/5.sram_ctrl_alert_test.997712905 |
/workspace/coverage/default/5.sram_ctrl_bijection.884333567 |
/workspace/coverage/default/5.sram_ctrl_executable.1263782939 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.502965793 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.1246001851 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1859190931 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.990692897 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.4191284739 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1732887992 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1071554206 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1956288890 |
/workspace/coverage/default/5.sram_ctrl_regwen.3304778157 |
/workspace/coverage/default/5.sram_ctrl_smoke.1535183785 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3580333057 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1261971652 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1346534852 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3909770534 |
/workspace/coverage/default/6.sram_ctrl_alert_test.4054882829 |
/workspace/coverage/default/6.sram_ctrl_bijection.3524016734 |
/workspace/coverage/default/6.sram_ctrl_executable.2551577244 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2200240682 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.3446361883 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2418468151 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.1643596129 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.466067738 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1746294641 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1126162428 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2618001549 |
/workspace/coverage/default/6.sram_ctrl_regwen.3793093220 |
/workspace/coverage/default/6.sram_ctrl_smoke.2471072626 |
/workspace/coverage/default/6.sram_ctrl_stress_all.419344726 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2307333377 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2883573472 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3761663585 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1422407088 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2424333834 |
/workspace/coverage/default/7.sram_ctrl_bijection.2234886546 |
/workspace/coverage/default/7.sram_ctrl_executable.2047138464 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2862422002 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.3494836480 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.326202297 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3256013001 |
/workspace/coverage/default/7.sram_ctrl_partial_access.2678631637 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2008813651 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2361890707 |
/workspace/coverage/default/7.sram_ctrl_regwen.2951456916 |
/workspace/coverage/default/7.sram_ctrl_smoke.3491984393 |
/workspace/coverage/default/7.sram_ctrl_stress_all.3596742503 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2175914071 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3561534423 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3332465556 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1881373819 |
/workspace/coverage/default/8.sram_ctrl_alert_test.2787954718 |
/workspace/coverage/default/8.sram_ctrl_bijection.881903756 |
/workspace/coverage/default/8.sram_ctrl_executable.2930860715 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.4161045406 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.1151797713 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3030681756 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.942045076 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3839739696 |
/workspace/coverage/default/8.sram_ctrl_partial_access.2786758155 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.45968420 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3191745872 |
/workspace/coverage/default/8.sram_ctrl_regwen.766002339 |
/workspace/coverage/default/8.sram_ctrl_smoke.1839417120 |
/workspace/coverage/default/8.sram_ctrl_stress_all.4022390674 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2230621992 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.807007642 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.459314528 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3316476170 |
/workspace/coverage/default/9.sram_ctrl_alert_test.2453772873 |
/workspace/coverage/default/9.sram_ctrl_bijection.1332868635 |
/workspace/coverage/default/9.sram_ctrl_executable.3549304542 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3608478523 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.4066776176 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2906447229 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.2309562257 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2685819106 |
/workspace/coverage/default/9.sram_ctrl_partial_access.451581619 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.4103492797 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3020748853 |
/workspace/coverage/default/9.sram_ctrl_regwen.3053244314 |
/workspace/coverage/default/9.sram_ctrl_smoke.3838908844 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1357251231 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3075011571 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2725529309 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1260084994 |
TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
T1 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.588793645 |
|
|
Apr 23 12:52:18 PM PDT 24 |
Apr 23 12:54:40 PM PDT 24 |
1615144144 ps |
T2 |
/workspace/coverage/default/28.sram_ctrl_partial_access.222365749 |
|
|
Apr 23 12:58:13 PM PDT 24 |
Apr 23 12:58:28 PM PDT 24 |
1104391427 ps |
T3 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.236465719 |
|
|
Apr 23 01:00:55 PM PDT 24 |
Apr 23 01:02:04 PM PDT 24 |
22612611187 ps |
T4 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.942045076 |
|
|
Apr 23 12:52:33 PM PDT 24 |
Apr 23 12:55:18 PM PDT 24 |
20733375537 ps |
T6 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.3987449396 |
|
|
Apr 23 12:59:39 PM PDT 24 |
Apr 23 01:00:45 PM PDT 24 |
958431804 ps |
T9 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3790440292 |
|
|
Apr 23 01:01:22 PM PDT 24 |
Apr 23 01:03:03 PM PDT 24 |
1555328064 ps |
T10 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1041920920 |
|
|
Apr 23 12:57:44 PM PDT 24 |
Apr 23 12:58:11 PM PDT 24 |
4592304650 ps |
T5 |
/workspace/coverage/default/40.sram_ctrl_smoke.1572907536 |
|
|
Apr 23 01:02:40 PM PDT 24 |
Apr 23 01:03:14 PM PDT 24 |
3506964448 ps |
T11 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.288148442 |
|
|
Apr 23 12:58:53 PM PDT 24 |
Apr 23 12:59:08 PM PDT 24 |
1414338709 ps |
T12 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.690716927 |
|
|
Apr 23 01:06:14 PM PDT 24 |
Apr 23 01:06:59 PM PDT 24 |
731873812 ps |
T15 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.414428981 |
|
|
Apr 23 12:59:05 PM PDT 24 |
Apr 23 12:59:40 PM PDT 24 |
1485662805 ps |
T16 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3282028916 |
|
|
Apr 23 12:53:19 PM PDT 24 |
Apr 23 01:04:50 PM PDT 24 |
8359685210 ps |
T7 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.826983251 |
|
|
Apr 23 12:56:20 PM PDT 24 |
Apr 23 12:57:10 PM PDT 24 |
29426165157 ps |
T13 |
/workspace/coverage/default/0.sram_ctrl_regwen.1963072536 |
|
|
Apr 23 12:50:39 PM PDT 24 |
Apr 23 12:54:50 PM PDT 24 |
37119618658 ps |
T53 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2087985908 |
|
|
Apr 23 12:52:55 PM PDT 24 |
Apr 23 12:54:31 PM PDT 24 |
3051236685 ps |
T54 |
/workspace/coverage/default/3.sram_ctrl_smoke.2039087602 |
|
|
Apr 23 12:51:17 PM PDT 24 |
Apr 23 12:53:32 PM PDT 24 |
1422946019 ps |
T20 |
/workspace/coverage/default/27.sram_ctrl_alert_test.2833213629 |
|
|
Apr 23 12:58:06 PM PDT 24 |
Apr 23 12:58:07 PM PDT 24 |
20597681 ps |
T42 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1099103424 |
|
|
Apr 23 12:54:14 PM PDT 24 |
Apr 23 12:59:42 PM PDT 24 |
22093669333 ps |
T41 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.4013186486 |
|
|
Apr 23 01:03:14 PM PDT 24 |
Apr 23 01:26:55 PM PDT 24 |
93849745827 ps |
T95 |
/workspace/coverage/default/8.sram_ctrl_bijection.881903756 |
|
|
Apr 23 12:52:22 PM PDT 24 |
Apr 23 01:36:41 PM PDT 24 |
606576316160 ps |
T67 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1220210924 |
|
|
Apr 23 01:04:08 PM PDT 24 |
Apr 23 01:05:16 PM PDT 24 |
955550689 ps |
T114 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.1463663503 |
|
|
Apr 23 12:51:30 PM PDT 24 |
Apr 23 12:56:46 PM PDT 24 |
74666867404 ps |
T68 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.3687430797 |
|
|
Apr 23 12:59:44 PM PDT 24 |
Apr 23 01:03:09 PM PDT 24 |
38586832036 ps |
T14 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.955785653 |
|
|
Apr 23 01:05:03 PM PDT 24 |
Apr 23 01:05:27 PM PDT 24 |
3279481038 ps |
T24 |
/workspace/coverage/default/21.sram_ctrl_stress_all.3994565015 |
|
|
Apr 23 12:56:06 PM PDT 24 |
Apr 23 01:55:44 PM PDT 24 |
165586532289 ps |
T69 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.783525935 |
|
|
Apr 23 01:01:12 PM PDT 24 |
Apr 23 01:04:33 PM PDT 24 |
16107896290 ps |
T90 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2837174030 |
|
|
Apr 23 12:59:33 PM PDT 24 |
Apr 23 01:01:47 PM PDT 24 |
6306146086 ps |
T109 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.1151264558 |
|
|
Apr 23 12:54:29 PM PDT 24 |
Apr 23 12:54:52 PM PDT 24 |
2919007911 ps |
T27 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2023617169 |
|
|
Apr 23 12:53:34 PM PDT 24 |
Apr 23 12:53:38 PM PDT 24 |
1403759841 ps |
T25 |
/workspace/coverage/default/37.sram_ctrl_regwen.964190281 |
|
|
Apr 23 01:01:42 PM PDT 24 |
Apr 23 01:17:23 PM PDT 24 |
15972698081 ps |
T26 |
/workspace/coverage/default/12.sram_ctrl_regwen.3092439104 |
|
|
Apr 23 12:53:32 PM PDT 24 |
Apr 23 01:09:01 PM PDT 24 |
5773856142 ps |
T110 |
/workspace/coverage/default/45.sram_ctrl_executable.2319511934 |
|
|
Apr 23 01:04:58 PM PDT 24 |
Apr 23 01:35:51 PM PDT 24 |
20465843739 ps |
T111 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.606983543 |
|
|
Apr 23 12:54:10 PM PDT 24 |
Apr 23 01:16:37 PM PDT 24 |
55467445033 ps |
T8 |
/workspace/coverage/default/44.sram_ctrl_stress_all.628116982 |
|
|
Apr 23 01:04:39 PM PDT 24 |
Apr 23 01:18:50 PM PDT 24 |
17618225823 ps |
T127 |
/workspace/coverage/default/32.sram_ctrl_executable.459791218 |
|
|
Apr 23 12:59:55 PM PDT 24 |
Apr 23 01:16:46 PM PDT 24 |
50631181610 ps |
T140 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.1973439878 |
|
|
Apr 23 12:57:40 PM PDT 24 |
Apr 23 12:59:43 PM PDT 24 |
11622431683 ps |
T141 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.2930340781 |
|
|
Apr 23 12:53:49 PM PDT 24 |
Apr 23 12:56:14 PM PDT 24 |
10407057484 ps |
T74 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.4060771143 |
|
|
Apr 23 01:05:42 PM PDT 24 |
Apr 23 01:06:45 PM PDT 24 |
954937170 ps |
T91 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.4103492797 |
|
|
Apr 23 12:52:41 PM PDT 24 |
Apr 23 12:58:31 PM PDT 24 |
22150855443 ps |
T142 |
/workspace/coverage/default/19.sram_ctrl_smoke.2716504159 |
|
|
Apr 23 12:55:09 PM PDT 24 |
Apr 23 12:55:31 PM PDT 24 |
907405275 ps |
T75 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1859190931 |
|
|
Apr 23 12:51:56 PM PDT 24 |
Apr 23 12:54:09 PM PDT 24 |
3189521064 ps |
T143 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.2301871465 |
|
|
Apr 23 12:59:43 PM PDT 24 |
Apr 23 01:01:07 PM PDT 24 |
33288317109 ps |
T144 |
/workspace/coverage/default/22.sram_ctrl_smoke.1191274022 |
|
|
Apr 23 12:56:10 PM PDT 24 |
Apr 23 12:56:15 PM PDT 24 |
801434886 ps |
T21 |
/workspace/coverage/default/5.sram_ctrl_alert_test.997712905 |
|
|
Apr 23 12:51:57 PM PDT 24 |
Apr 23 12:51:58 PM PDT 24 |
16897685 ps |
T28 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2186568684 |
|
|
Apr 23 01:00:17 PM PDT 24 |
Apr 23 01:00:21 PM PDT 24 |
1406368539 ps |
T145 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.990692897 |
|
|
Apr 23 12:51:55 PM PDT 24 |
Apr 23 12:54:00 PM PDT 24 |
7895969209 ps |
T132 |
/workspace/coverage/default/29.sram_ctrl_partial_access.1026647057 |
|
|
Apr 23 12:58:39 PM PDT 24 |
Apr 23 12:58:57 PM PDT 24 |
4590337652 ps |
T55 |
/workspace/coverage/default/40.sram_ctrl_stress_all.2881412317 |
|
|
Apr 23 01:03:04 PM PDT 24 |
Apr 23 02:35:11 PM PDT 24 |
659664333928 ps |
T92 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.2229889296 |
|
|
Apr 23 12:59:00 PM PDT 24 |
Apr 23 01:04:24 PM PDT 24 |
10935353745 ps |
T146 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3123375707 |
|
|
Apr 23 12:54:08 PM PDT 24 |
Apr 23 12:56:51 PM PDT 24 |
38925360731 ps |
T147 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1518686845 |
|
|
Apr 23 01:05:03 PM PDT 24 |
Apr 23 01:27:09 PM PDT 24 |
34067427103 ps |
T148 |
/workspace/coverage/default/37.sram_ctrl_bijection.3141223581 |
|
|
Apr 23 01:01:36 PM PDT 24 |
Apr 23 01:24:34 PM PDT 24 |
20858840669 ps |
T76 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.3749882069 |
|
|
Apr 23 12:54:32 PM PDT 24 |
Apr 23 12:55:38 PM PDT 24 |
3927732808 ps |
T149 |
/workspace/coverage/default/31.sram_ctrl_bijection.2549059785 |
|
|
Apr 23 12:59:28 PM PDT 24 |
Apr 23 01:22:51 PM PDT 24 |
266930451234 ps |
T23 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.1018073530 |
|
|
Apr 23 12:56:44 PM PDT 24 |
Apr 23 12:57:48 PM PDT 24 |
158534455854 ps |
T150 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3816905567 |
|
|
Apr 23 12:55:57 PM PDT 24 |
Apr 23 12:57:37 PM PDT 24 |
1581505293 ps |
T22 |
/workspace/coverage/default/13.sram_ctrl_alert_test.2993468353 |
|
|
Apr 23 12:53:49 PM PDT 24 |
Apr 23 12:53:50 PM PDT 24 |
18126113 ps |
T151 |
/workspace/coverage/default/39.sram_ctrl_bijection.654681526 |
|
|
Apr 23 01:02:19 PM PDT 24 |
Apr 23 01:12:39 PM PDT 24 |
9747578870 ps |
T152 |
/workspace/coverage/default/46.sram_ctrl_partial_access.1838132102 |
|
|
Apr 23 01:05:07 PM PDT 24 |
Apr 23 01:05:31 PM PDT 24 |
1579595378 ps |
T56 |
/workspace/coverage/default/33.sram_ctrl_stress_all.1676631440 |
|
|
Apr 23 01:00:19 PM PDT 24 |
Apr 23 02:00:36 PM PDT 24 |
335801333577 ps |
T153 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.834898071 |
|
|
Apr 23 12:55:34 PM PDT 24 |
Apr 23 01:01:22 PM PDT 24 |
27994513668 ps |
T154 |
/workspace/coverage/default/21.sram_ctrl_smoke.2807655943 |
|
|
Apr 23 12:55:48 PM PDT 24 |
Apr 23 12:55:53 PM PDT 24 |
1512554656 ps |
T133 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.717862551 |
|
|
Apr 23 12:56:10 PM PDT 24 |
Apr 23 12:59:46 PM PDT 24 |
8120834838 ps |
T46 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1429793361 |
|
|
Apr 23 01:05:41 PM PDT 24 |
Apr 23 01:08:23 PM PDT 24 |
5907456843 ps |
T43 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2128341094 |
|
|
Apr 23 12:51:53 PM PDT 24 |
Apr 23 01:08:02 PM PDT 24 |
10744336481 ps |
T155 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2424059912 |
|
|
Apr 23 12:55:35 PM PDT 24 |
Apr 23 12:59:03 PM PDT 24 |
3711086799 ps |
T156 |
/workspace/coverage/default/1.sram_ctrl_alert_test.920728235 |
|
|
Apr 23 12:51:00 PM PDT 24 |
Apr 23 12:51:01 PM PDT 24 |
42447289 ps |
T157 |
/workspace/coverage/default/7.sram_ctrl_partial_access.2678631637 |
|
|
Apr 23 12:52:16 PM PDT 24 |
Apr 23 12:52:37 PM PDT 24 |
7031239862 ps |
T158 |
/workspace/coverage/default/4.sram_ctrl_alert_test.1701003559 |
|
|
Apr 23 12:51:45 PM PDT 24 |
Apr 23 12:51:46 PM PDT 24 |
45940822 ps |
T47 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1663034566 |
|
|
Apr 23 01:00:42 PM PDT 24 |
Apr 23 01:01:40 PM PDT 24 |
4559092537 ps |
T29 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3191745872 |
|
|
Apr 23 12:52:33 PM PDT 24 |
Apr 23 12:52:37 PM PDT 24 |
1400874192 ps |
T159 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3044434387 |
|
|
Apr 23 12:51:11 PM PDT 24 |
Apr 23 12:51:38 PM PDT 24 |
3146069309 ps |
T160 |
/workspace/coverage/default/26.sram_ctrl_alert_test.2352264961 |
|
|
Apr 23 12:57:47 PM PDT 24 |
Apr 23 12:57:48 PM PDT 24 |
15234246 ps |
T161 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2963454594 |
|
|
Apr 23 12:53:59 PM PDT 24 |
Apr 23 12:55:17 PM PDT 24 |
1488084144 ps |
T162 |
/workspace/coverage/default/1.sram_ctrl_executable.227679902 |
|
|
Apr 23 12:50:56 PM PDT 24 |
Apr 23 01:20:59 PM PDT 24 |
41865819321 ps |
T48 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3580333057 |
|
|
Apr 23 12:51:55 PM PDT 24 |
Apr 23 12:52:12 PM PDT 24 |
382333170 ps |
T163 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.215745372 |
|
|
Apr 23 12:51:00 PM PDT 24 |
Apr 23 01:15:10 PM PDT 24 |
67870374872 ps |
T164 |
/workspace/coverage/default/16.sram_ctrl_bijection.1695863874 |
|
|
Apr 23 12:54:27 PM PDT 24 |
Apr 23 01:04:43 PM PDT 24 |
27918860669 ps |
T165 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.1576134411 |
|
|
Apr 23 12:56:34 PM PDT 24 |
Apr 23 12:59:19 PM PDT 24 |
11114928917 ps |
T166 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2758314390 |
|
|
Apr 23 01:05:51 PM PDT 24 |
Apr 23 01:06:12 PM PDT 24 |
3455981319 ps |
T167 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.352533850 |
|
|
Apr 23 12:54:20 PM PDT 24 |
Apr 23 12:54:24 PM PDT 24 |
1529305025 ps |
T168 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.377288858 |
|
|
Apr 23 12:54:42 PM PDT 24 |
Apr 23 12:59:06 PM PDT 24 |
7644067824 ps |
T49 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3075011571 |
|
|
Apr 23 12:52:52 PM PDT 24 |
Apr 23 12:53:01 PM PDT 24 |
1087495841 ps |
T169 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.4091398413 |
|
|
Apr 23 01:01:58 PM PDT 24 |
Apr 23 01:03:20 PM PDT 24 |
1482206489 ps |
T170 |
/workspace/coverage/default/29.sram_ctrl_regwen.3444594624 |
|
|
Apr 23 12:58:46 PM PDT 24 |
Apr 23 01:11:37 PM PDT 24 |
13318550381 ps |
T44 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.1941459849 |
|
|
Apr 23 12:54:01 PM PDT 24 |
Apr 23 01:18:23 PM PDT 24 |
19044738313 ps |
T171 |
/workspace/coverage/default/27.sram_ctrl_smoke.2402230564 |
|
|
Apr 23 12:57:46 PM PDT 24 |
Apr 23 12:57:52 PM PDT 24 |
1249580423 ps |
T172 |
/workspace/coverage/default/44.sram_ctrl_bijection.264761296 |
|
|
Apr 23 01:04:20 PM PDT 24 |
Apr 23 01:41:05 PM PDT 24 |
31852623445 ps |
T173 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.486822170 |
|
|
Apr 23 01:04:49 PM PDT 24 |
Apr 23 01:04:55 PM PDT 24 |
1277153087 ps |
T174 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2685819106 |
|
|
Apr 23 12:52:40 PM PDT 24 |
Apr 23 01:00:10 PM PDT 24 |
14979255604 ps |
T175 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3984749428 |
|
|
Apr 23 01:04:48 PM PDT 24 |
Apr 23 01:10:56 PM PDT 24 |
31318717206 ps |
T139 |
/workspace/coverage/default/37.sram_ctrl_stress_all.1688128349 |
|
|
Apr 23 01:01:46 PM PDT 24 |
Apr 23 02:09:51 PM PDT 24 |
86894099577 ps |
T176 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.3351458738 |
|
|
Apr 23 01:01:41 PM PDT 24 |
Apr 23 01:04:07 PM PDT 24 |
10336316983 ps |
T177 |
/workspace/coverage/default/5.sram_ctrl_bijection.884333567 |
|
|
Apr 23 12:51:49 PM PDT 24 |
Apr 23 01:19:33 PM PDT 24 |
49864279099 ps |
T45 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2637280898 |
|
|
Apr 23 12:51:58 PM PDT 24 |
Apr 23 02:55:12 PM PDT 24 |
490905733449 ps |
T112 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.2323502078 |
|
|
Apr 23 12:51:40 PM PDT 24 |
Apr 23 12:54:43 PM PDT 24 |
290048858627 ps |
T178 |
/workspace/coverage/default/41.sram_ctrl_smoke.1193940368 |
|
|
Apr 23 01:03:00 PM PDT 24 |
Apr 23 01:03:20 PM PDT 24 |
779433434 ps |
T179 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.1790104707 |
|
|
Apr 23 12:57:23 PM PDT 24 |
Apr 23 01:32:54 PM PDT 24 |
31032385954 ps |
T180 |
/workspace/coverage/default/38.sram_ctrl_bijection.2095647504 |
|
|
Apr 23 01:01:54 PM PDT 24 |
Apr 23 01:38:00 PM PDT 24 |
133809843700 ps |
T181 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.736468197 |
|
|
Apr 23 12:57:39 PM PDT 24 |
Apr 23 12:57:43 PM PDT 24 |
410567022 ps |
T182 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2399024184 |
|
|
Apr 23 01:00:28 PM PDT 24 |
Apr 23 01:02:17 PM PDT 24 |
8137317116 ps |
T183 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2361890707 |
|
|
Apr 23 12:52:22 PM PDT 24 |
Apr 23 12:52:25 PM PDT 24 |
361772462 ps |
T184 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.2030150995 |
|
|
Apr 23 12:58:19 PM PDT 24 |
Apr 23 01:00:00 PM PDT 24 |
3099317292 ps |
T185 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.45968420 |
|
|
Apr 23 12:52:27 PM PDT 24 |
Apr 23 12:56:56 PM PDT 24 |
18939633670 ps |
T113 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2862422002 |
|
|
Apr 23 12:52:22 PM PDT 24 |
Apr 23 12:53:47 PM PDT 24 |
14623777490 ps |
T186 |
/workspace/coverage/default/3.sram_ctrl_partial_access.3550119049 |
|
|
Apr 23 12:51:19 PM PDT 24 |
Apr 23 12:52:39 PM PDT 24 |
1070293268 ps |
T187 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2334612526 |
|
|
Apr 23 01:06:30 PM PDT 24 |
Apr 23 01:06:34 PM PDT 24 |
1348159723 ps |
T188 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3140406930 |
|
|
Apr 23 12:50:55 PM PDT 24 |
Apr 23 12:51:06 PM PDT 24 |
2738582030 ps |
T50 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2996780690 |
|
|
Apr 23 12:50:43 PM PDT 24 |
Apr 23 12:50:58 PM PDT 24 |
720842810 ps |
T51 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.155527300 |
|
|
Apr 23 12:56:51 PM PDT 24 |
Apr 23 12:57:54 PM PDT 24 |
2811098550 ps |
T189 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3069568786 |
|
|
Apr 23 01:05:55 PM PDT 24 |
Apr 23 01:06:37 PM PDT 24 |
766716663 ps |
T190 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.264427317 |
|
|
Apr 23 12:53:40 PM PDT 24 |
Apr 23 12:56:51 PM PDT 24 |
6942419101 ps |
T134 |
/workspace/coverage/default/40.sram_ctrl_executable.2318326308 |
|
|
Apr 23 01:02:54 PM PDT 24 |
Apr 23 01:14:07 PM PDT 24 |
24228699956 ps |
T77 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.1133189974 |
|
|
Apr 23 12:57:23 PM PDT 24 |
Apr 23 12:59:58 PM PDT 24 |
21207987688 ps |
T191 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.3918310613 |
|
|
Apr 23 12:57:29 PM PDT 24 |
Apr 23 01:06:28 PM PDT 24 |
22704174429 ps |
T192 |
/workspace/coverage/default/23.sram_ctrl_partial_access.1028643793 |
|
|
Apr 23 12:56:37 PM PDT 24 |
Apr 23 12:57:55 PM PDT 24 |
1079271400 ps |
T193 |
/workspace/coverage/default/20.sram_ctrl_smoke.3364740464 |
|
|
Apr 23 12:55:28 PM PDT 24 |
Apr 23 12:55:40 PM PDT 24 |
1064044322 ps |
T194 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2549384783 |
|
|
Apr 23 12:52:53 PM PDT 24 |
Apr 23 12:59:20 PM PDT 24 |
5628813793 ps |
T195 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.3494836480 |
|
|
Apr 23 12:52:16 PM PDT 24 |
Apr 23 12:52:22 PM PDT 24 |
672375965 ps |
T196 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.1367559451 |
|
|
Apr 23 01:03:18 PM PDT 24 |
Apr 23 01:03:22 PM PDT 24 |
1341947721 ps |
T197 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3761663585 |
|
|
Apr 23 12:52:08 PM PDT 24 |
Apr 23 12:53:14 PM PDT 24 |
2975886543 ps |
T198 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.3087603240 |
|
|
Apr 23 12:51:32 PM PDT 24 |
Apr 23 01:17:38 PM PDT 24 |
80569404601 ps |
T199 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.4008463048 |
|
|
Apr 23 01:04:03 PM PDT 24 |
Apr 23 01:08:00 PM PDT 24 |
16855335863 ps |
T130 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.4274456986 |
|
|
Apr 23 01:02:00 PM PDT 24 |
Apr 23 01:07:54 PM PDT 24 |
63794896394 ps |
T200 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.2052945007 |
|
|
Apr 23 12:54:46 PM PDT 24 |
Apr 23 12:55:08 PM PDT 24 |
3839417953 ps |
T201 |
/workspace/coverage/default/7.sram_ctrl_bijection.2234886546 |
|
|
Apr 23 12:52:17 PM PDT 24 |
Apr 23 01:17:41 PM PDT 24 |
67280370545 ps |
T85 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1932782256 |
|
|
Apr 23 01:06:29 PM PDT 24 |
Apr 23 01:07:37 PM PDT 24 |
3925700598 ps |
T202 |
/workspace/coverage/default/41.sram_ctrl_stress_all.2557967207 |
|
|
Apr 23 01:03:26 PM PDT 24 |
Apr 23 02:18:23 PM PDT 24 |
138022720364 ps |
T203 |
/workspace/coverage/default/3.sram_ctrl_executable.300194651 |
|
|
Apr 23 12:51:25 PM PDT 24 |
Apr 23 12:55:43 PM PDT 24 |
1510117718 ps |
T204 |
/workspace/coverage/default/41.sram_ctrl_alert_test.1478029074 |
|
|
Apr 23 01:03:32 PM PDT 24 |
Apr 23 01:03:34 PM PDT 24 |
19502554 ps |
T205 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2078752277 |
|
|
Apr 23 01:05:14 PM PDT 24 |
Apr 23 01:05:18 PM PDT 24 |
1867109830 ps |
T206 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3874590733 |
|
|
Apr 23 12:55:41 PM PDT 24 |
Apr 23 12:56:44 PM PDT 24 |
3997034650 ps |
T52 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.745342344 |
|
|
Apr 23 12:54:34 PM PDT 24 |
Apr 23 12:55:03 PM PDT 24 |
5775187219 ps |
T207 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.2652978166 |
|
|
Apr 23 01:00:53 PM PDT 24 |
Apr 23 01:30:40 PM PDT 24 |
11978969508 ps |
T208 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2249846490 |
|
|
Apr 23 12:56:26 PM PDT 24 |
Apr 23 12:58:33 PM PDT 24 |
1760732734 ps |
T209 |
/workspace/coverage/default/18.sram_ctrl_regwen.3008756221 |
|
|
Apr 23 12:55:04 PM PDT 24 |
Apr 23 01:09:49 PM PDT 24 |
36489773054 ps |
T210 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.1177288256 |
|
|
Apr 23 01:01:54 PM PDT 24 |
Apr 23 01:07:24 PM PDT 24 |
5483193135 ps |
T211 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.2215244228 |
|
|
Apr 23 01:01:35 PM PDT 24 |
Apr 23 01:13:14 PM PDT 24 |
8487827995 ps |
T212 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1756533970 |
|
|
Apr 23 01:04:19 PM PDT 24 |
Apr 23 01:10:14 PM PDT 24 |
39057491056 ps |
T213 |
/workspace/coverage/default/45.sram_ctrl_alert_test.107121598 |
|
|
Apr 23 01:05:03 PM PDT 24 |
Apr 23 01:05:04 PM PDT 24 |
34921849 ps |
T214 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.4184158824 |
|
|
Apr 23 01:02:47 PM PDT 24 |
Apr 23 01:05:38 PM PDT 24 |
9719251319 ps |
T215 |
/workspace/coverage/default/47.sram_ctrl_partial_access.3174078901 |
|
|
Apr 23 01:05:27 PM PDT 24 |
Apr 23 01:05:36 PM PDT 24 |
913617442 ps |
T216 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2725529309 |
|
|
Apr 23 12:52:41 PM PDT 24 |
Apr 23 12:58:22 PM PDT 24 |
11103167190 ps |
T217 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1746294641 |
|
|
Apr 23 12:52:04 PM PDT 24 |
Apr 23 12:52:16 PM PDT 24 |
882728103 ps |
T218 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.1246001851 |
|
|
Apr 23 12:51:51 PM PDT 24 |
Apr 23 12:52:18 PM PDT 24 |
1439211923 ps |
T219 |
/workspace/coverage/default/28.sram_ctrl_regwen.1920234639 |
|
|
Apr 23 12:58:21 PM PDT 24 |
Apr 23 01:04:22 PM PDT 24 |
4059482086 ps |
T220 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.1940648181 |
|
|
Apr 23 01:03:20 PM PDT 24 |
Apr 23 01:04:30 PM PDT 24 |
4826589886 ps |
T131 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1644568125 |
|
|
Apr 23 12:50:57 PM PDT 24 |
Apr 23 12:53:44 PM PDT 24 |
9954252082 ps |
T221 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2490884695 |
|
|
Apr 23 01:05:22 PM PDT 24 |
Apr 23 01:25:16 PM PDT 24 |
19436729741 ps |
T222 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3393667145 |
|
|
Apr 23 12:55:17 PM PDT 24 |
Apr 23 01:01:36 PM PDT 24 |
23387678354 ps |
T223 |
/workspace/coverage/default/17.sram_ctrl_partial_access.2070894724 |
|
|
Apr 23 12:54:40 PM PDT 24 |
Apr 23 12:56:52 PM PDT 24 |
872745768 ps |
T224 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2951159743 |
|
|
Apr 23 01:05:37 PM PDT 24 |
Apr 23 01:05:41 PM PDT 24 |
347897717 ps |
T225 |
/workspace/coverage/default/13.sram_ctrl_regwen.56156674 |
|
|
Apr 23 12:53:47 PM PDT 24 |
Apr 23 01:02:18 PM PDT 24 |
2374388155 ps |
T226 |
/workspace/coverage/default/0.sram_ctrl_bijection.3020310078 |
|
|
Apr 23 12:50:39 PM PDT 24 |
Apr 23 01:01:43 PM PDT 24 |
9516492187 ps |
T227 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.329773803 |
|
|
Apr 23 12:54:33 PM PDT 24 |
Apr 23 12:58:47 PM PDT 24 |
8214830277 ps |
T228 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.3024728519 |
|
|
Apr 23 01:03:41 PM PDT 24 |
Apr 23 01:04:14 PM PDT 24 |
1500451786 ps |
T229 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.4066666089 |
|
|
Apr 23 12:51:36 PM PDT 24 |
Apr 23 12:56:13 PM PDT 24 |
23622691119 ps |
T230 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.2918394311 |
|
|
Apr 23 12:55:06 PM PDT 24 |
Apr 23 12:57:14 PM PDT 24 |
7888669836 ps |
T231 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.108452819 |
|
|
Apr 23 01:04:08 PM PDT 24 |
Apr 23 01:06:42 PM PDT 24 |
2550200617 ps |
T232 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.1168444120 |
|
|
Apr 23 12:56:45 PM PDT 24 |
Apr 23 12:56:49 PM PDT 24 |
365471752 ps |
T233 |
/workspace/coverage/default/44.sram_ctrl_alert_test.1085627038 |
|
|
Apr 23 01:04:46 PM PDT 24 |
Apr 23 01:04:47 PM PDT 24 |
35938506 ps |
T234 |
/workspace/coverage/default/41.sram_ctrl_partial_access.1742986229 |
|
|
Apr 23 01:03:04 PM PDT 24 |
Apr 23 01:03:18 PM PDT 24 |
1970989784 ps |
T235 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.4096649881 |
|
|
Apr 23 12:59:06 PM PDT 24 |
Apr 23 01:01:58 PM PDT 24 |
3360563163 ps |
T236 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1216751592 |
|
|
Apr 23 01:00:34 PM PDT 24 |
Apr 23 01:00:41 PM PDT 24 |
2797278547 ps |
T237 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.3299138399 |
|
|
Apr 23 01:02:45 PM PDT 24 |
Apr 23 01:02:52 PM PDT 24 |
1634483990 ps |
T238 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.544933465 |
|
|
Apr 23 12:54:56 PM PDT 24 |
Apr 23 01:06:35 PM PDT 24 |
16554079079 ps |
T239 |
/workspace/coverage/default/44.sram_ctrl_smoke.2172084966 |
|
|
Apr 23 01:04:14 PM PDT 24 |
Apr 23 01:05:07 PM PDT 24 |
777622450 ps |
T240 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.1107126102 |
|
|
Apr 23 12:54:40 PM PDT 24 |
Apr 23 12:56:09 PM PDT 24 |
1712095350 ps |
T241 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3923315214 |
|
|
Apr 23 12:57:24 PM PDT 24 |
Apr 23 12:57:34 PM PDT 24 |
664320907 ps |
T242 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1909471497 |
|
|
Apr 23 12:53:01 PM PDT 24 |
Apr 23 12:53:19 PM PDT 24 |
1414998765 ps |
T243 |
/workspace/coverage/default/14.sram_ctrl_alert_test.1021420915 |
|
|
Apr 23 12:54:09 PM PDT 24 |
Apr 23 12:54:10 PM PDT 24 |
16182125 ps |
T244 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.4282679040 |
|
|
Apr 23 12:51:29 PM PDT 24 |
Apr 23 12:54:01 PM PDT 24 |
4511885493 ps |
T245 |
/workspace/coverage/default/12.sram_ctrl_bijection.1932364080 |
|
|
Apr 23 12:53:17 PM PDT 24 |
Apr 23 01:01:17 PM PDT 24 |
14381687629 ps |
T246 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2629878905 |
|
|
Apr 23 01:05:55 PM PDT 24 |
Apr 23 01:21:46 PM PDT 24 |
15383035096 ps |
T247 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.210442699 |
|
|
Apr 23 12:54:00 PM PDT 24 |
Apr 23 12:58:32 PM PDT 24 |
4993263441 ps |
T248 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1686583370 |
|
|
Apr 23 12:54:22 PM PDT 24 |
Apr 23 12:54:23 PM PDT 24 |
112832834 ps |
T249 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1732887992 |
|
|
Apr 23 12:51:52 PM PDT 24 |
Apr 23 12:52:01 PM PDT 24 |
2907517525 ps |
T250 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.2307192456 |
|
|
Apr 23 12:51:37 PM PDT 24 |
Apr 23 12:54:41 PM PDT 24 |
14948112997 ps |
T251 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.309713953 |
|
|
Apr 23 12:53:14 PM PDT 24 |
Apr 23 12:55:39 PM PDT 24 |
11065309253 ps |
T252 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.2600427486 |
|
|
Apr 23 12:50:56 PM PDT 24 |
Apr 23 12:53:55 PM PDT 24 |
89552813631 ps |
T253 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.2927153344 |
|
|
Apr 23 01:00:16 PM PDT 24 |
Apr 23 01:01:54 PM PDT 24 |
1592043203 ps |
T254 |
/workspace/coverage/default/13.sram_ctrl_bijection.860400860 |
|
|
Apr 23 12:53:41 PM PDT 24 |
Apr 23 01:28:26 PM PDT 24 |
126855056050 ps |
T255 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.4291023154 |
|
|
Apr 23 12:58:26 PM PDT 24 |
Apr 23 01:04:03 PM PDT 24 |
21515650050 ps |
T256 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3133219233 |
|
|
Apr 23 12:52:56 PM PDT 24 |
Apr 23 12:54:49 PM PDT 24 |
4650137536 ps |
T257 |
/workspace/coverage/default/14.sram_ctrl_partial_access.1201256806 |
|
|
Apr 23 12:53:57 PM PDT 24 |
Apr 23 12:56:38 PM PDT 24 |
7237684587 ps |
T258 |
/workspace/coverage/default/14.sram_ctrl_smoke.176389792 |
|
|
Apr 23 12:53:49 PM PDT 24 |
Apr 23 12:56:37 PM PDT 24 |
6144980188 ps |
T259 |
/workspace/coverage/default/35.sram_ctrl_bijection.3515246463 |
|
|
Apr 23 01:00:54 PM PDT 24 |
Apr 23 01:40:51 PM PDT 24 |
106992374976 ps |
T260 |
/workspace/coverage/default/17.sram_ctrl_bijection.4019840998 |
|
|
Apr 23 12:54:41 PM PDT 24 |
Apr 23 01:06:32 PM PDT 24 |
143413531506 ps |
T261 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.4066776176 |
|
|
Apr 23 12:52:45 PM PDT 24 |
Apr 23 12:53:25 PM PDT 24 |
2873653320 ps |
T128 |
/workspace/coverage/default/22.sram_ctrl_stress_all.525615031 |
|
|
Apr 23 12:56:28 PM PDT 24 |
Apr 23 02:14:13 PM PDT 24 |
339103925625 ps |
T262 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.3758062221 |
|
|
Apr 23 12:55:15 PM PDT 24 |
Apr 23 12:56:42 PM PDT 24 |
3103327918 ps |
T263 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2245663240 |
|
|
Apr 23 12:59:41 PM PDT 24 |
Apr 23 12:59:42 PM PDT 24 |
44328868 ps |
T264 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.216922725 |
|
|
Apr 23 01:02:26 PM PDT 24 |
Apr 23 01:06:00 PM PDT 24 |
4141749506 ps |
T265 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.818928686 |
|
|
Apr 23 12:51:10 PM PDT 24 |
Apr 23 12:51:14 PM PDT 24 |
434685064 ps |
T266 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.2271834230 |
|
|
Apr 23 12:54:46 PM PDT 24 |
Apr 23 01:13:04 PM PDT 24 |
16823762163 ps |
T267 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.2090092344 |
|
|
Apr 23 01:02:58 PM PDT 24 |
Apr 23 01:13:02 PM PDT 24 |
4160407684 ps |
T268 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.3045238253 |
|
|
Apr 23 12:57:51 PM PDT 24 |
Apr 23 01:06:46 PM PDT 24 |
23536458716 ps |
T269 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.4094299309 |
|
|
Apr 23 01:02:18 PM PDT 24 |
Apr 23 01:07:03 PM PDT 24 |
19931056984 ps |
T270 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.1812904643 |
|
|
Apr 23 01:00:12 PM PDT 24 |
Apr 23 01:04:15 PM PDT 24 |
4473267260 ps |
T271 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.2975767978 |
|
|
Apr 23 12:51:07 PM PDT 24 |
Apr 23 12:52:23 PM PDT 24 |
1546022580 ps |
T272 |
/workspace/coverage/default/2.sram_ctrl_executable.2398938485 |
|
|
Apr 23 12:51:05 PM PDT 24 |
Apr 23 01:04:42 PM PDT 24 |
10483852535 ps |
T273 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2127392360 |
|
|
Apr 23 12:55:40 PM PDT 24 |
Apr 23 01:01:04 PM PDT 24 |
4961751371 ps |
T274 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.2345456787 |
|
|
Apr 23 12:54:58 PM PDT 24 |
Apr 23 12:55:18 PM PDT 24 |
4073294253 ps |
T275 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3561534423 |
|
|
Apr 23 12:52:17 PM PDT 24 |
Apr 23 12:56:33 PM PDT 24 |
4056354423 ps |
T276 |
/workspace/coverage/default/41.sram_ctrl_bijection.996180848 |
|
|
Apr 23 01:03:03 PM PDT 24 |
Apr 23 01:41:03 PM PDT 24 |
32467014101 ps |
T277 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.4227352344 |
|
|
Apr 23 01:05:50 PM PDT 24 |
Apr 23 01:09:35 PM PDT 24 |
4081317555 ps |
T278 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.1221523716 |
|
|
Apr 23 12:58:30 PM PDT 24 |
Apr 23 01:12:11 PM PDT 24 |
21959598643 ps |
T279 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.850796281 |
|
|
Apr 23 12:51:12 PM PDT 24 |
Apr 23 12:51:20 PM PDT 24 |
198854249 ps |
T280 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1468721827 |
|
|
Apr 23 12:55:25 PM PDT 24 |
Apr 23 12:55:39 PM PDT 24 |
371246506 ps |
T281 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2480974191 |
|
|
Apr 23 01:01:37 PM PDT 24 |
Apr 23 01:07:39 PM PDT 24 |
6666247269 ps |
T282 |
/workspace/coverage/default/48.sram_ctrl_alert_test.212878334 |
|
|
Apr 23 01:06:05 PM PDT 24 |
Apr 23 01:06:06 PM PDT 24 |
14040953 ps |
T283 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.3978484900 |
|
|
Apr 23 12:55:31 PM PDT 24 |
Apr 23 01:17:55 PM PDT 24 |
79550094027 ps |
T284 |
/workspace/coverage/default/2.sram_ctrl_bijection.4229406487 |
|
|
Apr 23 12:51:03 PM PDT 24 |
Apr 23 01:26:49 PM PDT 24 |
243103996309 ps |
T285 |
/workspace/coverage/default/2.sram_ctrl_stress_all.662843710 |
|
|
Apr 23 12:51:16 PM PDT 24 |
Apr 23 01:21:31 PM PDT 24 |
88836958916 ps |
T286 |
/workspace/coverage/default/14.sram_ctrl_executable.658160841 |
|
|
Apr 23 12:54:02 PM PDT 24 |
Apr 23 01:15:02 PM PDT 24 |
61746587685 ps |
T287 |
/workspace/coverage/default/9.sram_ctrl_regwen.3053244314 |
|
|
Apr 23 12:52:49 PM PDT 24 |
Apr 23 12:53:12 PM PDT 24 |
1239953611 ps |
T288 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.2128196164 |
|
|
Apr 23 12:54:01 PM PDT 24 |
Apr 23 12:55:07 PM PDT 24 |
10257443939 ps |
T289 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.1234106182 |
|
|
Apr 23 01:00:19 PM PDT 24 |
Apr 23 01:05:21 PM PDT 24 |
105966637634 ps |
T290 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.401032235 |
|
|
Apr 23 01:03:50 PM PDT 24 |
Apr 23 01:04:38 PM PDT 24 |
32494038683 ps |
T291 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.1290277598 |
|
|
Apr 23 01:02:12 PM PDT 24 |
Apr 23 01:06:19 PM PDT 24 |
3983857401 ps |
T292 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3388890350 |
|
|
Apr 23 12:53:18 PM PDT 24 |
Apr 23 12:57:30 PM PDT 24 |
13191679507 ps |
T293 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1527329016 |
|
|
Apr 23 01:05:13 PM PDT 24 |
Apr 23 01:16:31 PM PDT 24 |
16700133623 ps |
T294 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1392135897 |
|
|
Apr 23 01:05:15 PM PDT 24 |
Apr 23 01:06:36 PM PDT 24 |
10881498797 ps |
T295 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.351329558 |
|
|
Apr 23 12:50:35 PM PDT 24 |
Apr 23 12:51:50 PM PDT 24 |
3770166864 ps |
T296 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2307333377 |
|
|
Apr 23 12:52:12 PM PDT 24 |
Apr 23 12:52:21 PM PDT 24 |
286570959 ps |
T297 |
/workspace/coverage/default/12.sram_ctrl_alert_test.2626377588 |
|
|
Apr 23 12:53:40 PM PDT 24 |
Apr 23 12:53:40 PM PDT 24 |
14875010 ps |
T298 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.3446361883 |
|
|
Apr 23 12:52:02 PM PDT 24 |
Apr 23 12:53:43 PM PDT 24 |
2993121739 ps |
T299 |
/workspace/coverage/default/30.sram_ctrl_bijection.2985323102 |
|
|
Apr 23 12:59:00 PM PDT 24 |
Apr 23 01:25:30 PM PDT 24 |
280843896266 ps |
T300 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.936705218 |
|
|
Apr 23 12:59:04 PM PDT 24 |
Apr 23 01:00:47 PM PDT 24 |
1528877854 ps |
T301 |
/workspace/coverage/default/24.sram_ctrl_regwen.1233866588 |
|
|
Apr 23 12:57:00 PM PDT 24 |
Apr 23 01:04:41 PM PDT 24 |
11573397801 ps |
T302 |
/workspace/coverage/default/10.sram_ctrl_smoke.2768991385 |
|
|
Apr 23 12:52:50 PM PDT 24 |
Apr 23 12:53:10 PM PDT 24 |
6464749795 ps |
T303 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2732179227 |
|
|
Apr 23 01:00:15 PM PDT 24 |
Apr 23 01:02:21 PM PDT 24 |
777993122 ps |
T100 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1560808431 |
|
|
Apr 23 01:00:20 PM PDT 24 |
Apr 23 01:00:41 PM PDT 24 |
1269773694 ps |
T304 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.730209981 |
|
|
Apr 23 12:54:14 PM PDT 24 |
Apr 23 12:59:45 PM PDT 24 |
5490117118 ps |
T305 |
/workspace/coverage/default/33.sram_ctrl_executable.1178589472 |
|
|
Apr 23 01:00:15 PM PDT 24 |
Apr 23 01:28:20 PM PDT 24 |
27594459899 ps |
T306 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.248577474 |
|
|
Apr 23 12:57:55 PM PDT 24 |
Apr 23 01:02:10 PM PDT 24 |
11354704890 ps |
T307 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3244176288 |
|
|
Apr 23 01:04:43 PM PDT 24 |
Apr 23 01:11:57 PM PDT 24 |
12966288295 ps |
T308 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.1106185854 |
|
|
Apr 23 01:00:14 PM PDT 24 |
Apr 23 01:01:48 PM PDT 24 |
15512469716 ps |
T309 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.3152369566 |
|
|
Apr 23 12:55:49 PM PDT 24 |
Apr 23 01:11:17 PM PDT 24 |
22896439402 ps |
T310 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3131129573 |
|
|
Apr 23 12:52:58 PM PDT 24 |
Apr 23 01:14:19 PM PDT 24 |
72236325325 ps |
T136 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.3113128394 |
|
|
Apr 23 12:54:52 PM PDT 24 |
Apr 23 12:57:29 PM PDT 24 |
17775169669 ps |
T311 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3513446635 |
|
|
Apr 23 01:03:09 PM PDT 24 |
Apr 23 01:04:09 PM PDT 24 |
805792191 ps |
T312 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.4127204967 |
|
|
Apr 23 12:57:13 PM PDT 24 |
Apr 23 01:10:17 PM PDT 24 |
9310264032 ps |
T313 |
/workspace/coverage/default/40.sram_ctrl_regwen.2886633939 |
|
|
Apr 23 01:02:52 PM PDT 24 |
Apr 23 01:21:56 PM PDT 24 |
14733005302 ps |
T314 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.241415985 |
|
|
Apr 23 12:55:41 PM PDT 24 |
Apr 23 12:55:44 PM PDT 24 |
2115598743 ps |
T315 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.1501800929 |
|
|
Apr 23 01:00:31 PM PDT 24 |
Apr 23 01:00:42 PM PDT 24 |
692040947 ps |
T316 |
/workspace/coverage/default/16.sram_ctrl_smoke.1677418695 |
|
|
Apr 23 12:54:23 PM PDT 24 |
Apr 23 12:55:27 PM PDT 24 |
1086296532 ps |
T317 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.2994508535 |
|
|
Apr 23 12:55:06 PM PDT 24 |
Apr 23 12:55:10 PM PDT 24 |
350393991 ps |
T318 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.1232388042 |
|
|
Apr 23 12:56:27 PM PDT 24 |
Apr 23 12:59:01 PM PDT 24 |
9290449330 ps |
T319 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.819956962 |
|
|
Apr 23 12:56:59 PM PDT 24 |
Apr 23 12:57:39 PM PDT 24 |
2887254130 ps |