Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	153224031	1			T1	3143		T2	1275		T3	177
triple_byte_access	2701688	1			T1	6919		T2	1245		T3	1
halfword_access	4155271	1			T1	13026		T2	1702		T3	6
byte_access	5828886	1			T1	24918		T2	2342		T3	3
zero_access	1786373	1			T1	14670		T2	578		T3	4

---

Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83597431

1

T1

31456

T2

3576

T3

90

auto[1]

84098818

1

T1

31220

T2

3566

T3

101

---

Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	76229057	1			T1	283		T2	673		T3	84
auto[0]	triple_byte_access	1281434	1			T1	1291		T2	611		T3	1
auto[0]	halfword_access	2024092	1			T1	4555		T2	841		T3	2
auto[0]	byte_access	2986398	1			T1	13485		T2	1161		T3	2
auto[0]	zero_access	1076450	1			T1	11842		T2	290		T3	1
auto[1]	word_access	76994974	1			T1	2860		T2	602		T3	93
auto[1]	triple_byte_access	1420254	1			T1	5628		T2	634		T6	2922
auto[1]	halfword_access	2131179	1			T1	8471		T2	861		T3	4
auto[1]	byte_access	2842488	1			T1	11433		T2	1181		T3	1
auto[1]	zero_access	709923	1			T1	2828		T2	288		T3	3