| T794 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.4149277753 |
|
|
Apr 23 01:03:27 PM PDT 24 |
Apr 23 01:15:53 PM PDT 24 |
9659327819 ps |
| T795 |
/workspace/coverage/default/46.sram_ctrl_smoke.3601867981 |
|
|
Apr 23 01:05:03 PM PDT 24 |
Apr 23 01:05:17 PM PDT 24 |
6967367139 ps |
| T796 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.416922301 |
|
|
Apr 23 12:57:27 PM PDT 24 |
Apr 23 12:58:59 PM PDT 24 |
1552919421 ps |
| T797 |
/workspace/coverage/default/48.sram_ctrl_bijection.3002372794 |
|
|
Apr 23 01:05:50 PM PDT 24 |
Apr 23 01:43:12 PM PDT 24 |
67747882411 ps |
| T798 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3417945214 |
|
|
Apr 23 12:55:50 PM PDT 24 |
Apr 23 01:00:50 PM PDT 24 |
61031671688 ps |
| T799 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.3961650949 |
|
|
Apr 23 12:55:34 PM PDT 24 |
Apr 23 12:55:49 PM PDT 24 |
735872149 ps |
| T800 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.1540115373 |
|
|
Apr 23 12:51:06 PM PDT 24 |
Apr 23 12:52:19 PM PDT 24 |
12605901973 ps |
| T801 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.845374215 |
|
|
Apr 23 01:02:55 PM PDT 24 |
Apr 23 01:03:05 PM PDT 24 |
261832956 ps |
| T802 |
/workspace/coverage/default/28.sram_ctrl_alert_test.1365405039 |
|
|
Apr 23 12:58:31 PM PDT 24 |
Apr 23 12:58:32 PM PDT 24 |
27595164 ps |
| T803 |
/workspace/coverage/default/3.sram_ctrl_stress_all.2953825190 |
|
|
Apr 23 12:51:32 PM PDT 24 |
Apr 23 01:42:30 PM PDT 24 |
38984907058 ps |
| T804 |
/workspace/coverage/default/17.sram_ctrl_executable.3132954958 |
|
|
Apr 23 12:54:48 PM PDT 24 |
Apr 23 01:09:25 PM PDT 24 |
32985009592 ps |
| T805 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2741403027 |
|
|
Apr 23 12:53:01 PM PDT 24 |
Apr 23 12:55:53 PM PDT 24 |
8904730990 ps |
| T806 |
/workspace/coverage/default/33.sram_ctrl_bijection.1601138588 |
|
|
Apr 23 01:00:11 PM PDT 24 |
Apr 23 01:28:55 PM PDT 24 |
386933965203 ps |
| T807 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3591781717 |
|
|
Apr 23 01:03:47 PM PDT 24 |
Apr 23 01:04:06 PM PDT 24 |
723117218 ps |
| T808 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1820681871 |
|
|
Apr 23 01:00:57 PM PDT 24 |
Apr 23 01:17:27 PM PDT 24 |
47485531826 ps |
| T809 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.2034676602 |
|
|
Apr 23 12:53:56 PM PDT 24 |
Apr 23 12:56:39 PM PDT 24 |
1532284964 ps |
| T810 |
/workspace/coverage/default/20.sram_ctrl_stress_all.2555127304 |
|
|
Apr 23 12:55:46 PM PDT 24 |
Apr 23 02:14:18 PM PDT 24 |
59020623800 ps |
| T811 |
/workspace/coverage/default/34.sram_ctrl_stress_all.2999849366 |
|
|
Apr 23 01:00:45 PM PDT 24 |
Apr 23 02:26:52 PM PDT 24 |
163473836347 ps |
| T812 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2729616352 |
|
|
Apr 23 12:53:05 PM PDT 24 |
Apr 23 12:53:56 PM PDT 24 |
3009368939 ps |
| T813 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.1151797713 |
|
|
Apr 23 12:52:27 PM PDT 24 |
Apr 23 12:53:32 PM PDT 24 |
727004192 ps |
| T814 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.1061981793 |
|
|
Apr 23 01:05:27 PM PDT 24 |
Apr 23 01:06:51 PM PDT 24 |
752330759 ps |
| T815 |
/workspace/coverage/default/27.sram_ctrl_regwen.2362931487 |
|
|
Apr 23 12:57:58 PM PDT 24 |
Apr 23 01:01:01 PM PDT 24 |
8555461457 ps |
| T816 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1816469552 |
|
|
Apr 23 12:58:37 PM PDT 24 |
Apr 23 12:59:45 PM PDT 24 |
759871969 ps |
| T817 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2952740998 |
|
|
Apr 23 01:05:00 PM PDT 24 |
Apr 23 01:07:22 PM PDT 24 |
12053584028 ps |
| T818 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2453286882 |
|
|
Apr 23 01:02:16 PM PDT 24 |
Apr 23 01:04:24 PM PDT 24 |
6777310375 ps |
| T819 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.2625861521 |
|
|
Apr 23 12:56:19 PM PDT 24 |
Apr 23 12:56:26 PM PDT 24 |
673565175 ps |
| T820 |
/workspace/coverage/default/15.sram_ctrl_stress_all.2624223720 |
|
|
Apr 23 12:54:23 PM PDT 24 |
Apr 23 01:57:44 PM PDT 24 |
104379284455 ps |
| T821 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1832068651 |
|
|
Apr 23 01:01:19 PM PDT 24 |
Apr 23 01:08:37 PM PDT 24 |
160063326441 ps |
| T822 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.4133075723 |
|
|
Apr 23 12:57:02 PM PDT 24 |
Apr 23 12:58:27 PM PDT 24 |
2778540851 ps |
| T823 |
/workspace/coverage/default/35.sram_ctrl_partial_access.983162266 |
|
|
Apr 23 01:00:52 PM PDT 24 |
Apr 23 01:01:04 PM PDT 24 |
805669595 ps |
| T824 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.895176398 |
|
|
Apr 23 01:02:30 PM PDT 24 |
Apr 23 01:02:34 PM PDT 24 |
1401519014 ps |
| T825 |
/workspace/coverage/default/19.sram_ctrl_partial_access.61577961 |
|
|
Apr 23 12:55:12 PM PDT 24 |
Apr 23 12:55:26 PM PDT 24 |
6379918132 ps |
| T826 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.2688955774 |
|
|
Apr 23 12:59:20 PM PDT 24 |
Apr 23 01:01:33 PM PDT 24 |
2062297827 ps |
| T827 |
/workspace/coverage/default/6.sram_ctrl_alert_test.4054882829 |
|
|
Apr 23 12:52:11 PM PDT 24 |
Apr 23 12:52:12 PM PDT 24 |
31707493 ps |
| T828 |
/workspace/coverage/default/46.sram_ctrl_alert_test.1711368857 |
|
|
Apr 23 01:05:23 PM PDT 24 |
Apr 23 01:05:24 PM PDT 24 |
32817512 ps |
| T829 |
/workspace/coverage/default/8.sram_ctrl_smoke.1839417120 |
|
|
Apr 23 12:52:23 PM PDT 24 |
Apr 23 12:52:44 PM PDT 24 |
1337345365 ps |
| T830 |
/workspace/coverage/default/34.sram_ctrl_executable.1122399321 |
|
|
Apr 23 01:00:33 PM PDT 24 |
Apr 23 01:27:26 PM PDT 24 |
106879550498 ps |
| T831 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3104003183 |
|
|
Apr 23 12:54:26 PM PDT 24 |
Apr 23 12:54:35 PM PDT 24 |
3652999055 ps |
| T832 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2200240682 |
|
|
Apr 23 12:52:13 PM PDT 24 |
Apr 23 12:52:49 PM PDT 24 |
33525499542 ps |
| T833 |
/workspace/coverage/default/38.sram_ctrl_executable.2096452547 |
|
|
Apr 23 01:02:09 PM PDT 24 |
Apr 23 01:13:53 PM PDT 24 |
12352526225 ps |
| T834 |
/workspace/coverage/default/49.sram_ctrl_partial_access.91877213 |
|
|
Apr 23 01:06:14 PM PDT 24 |
Apr 23 01:06:22 PM PDT 24 |
2763425910 ps |
| T835 |
/workspace/coverage/default/6.sram_ctrl_executable.2551577244 |
|
|
Apr 23 12:52:10 PM PDT 24 |
Apr 23 01:08:26 PM PDT 24 |
69910972892 ps |
| T836 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1653406843 |
|
|
Apr 23 01:05:07 PM PDT 24 |
Apr 23 01:13:08 PM PDT 24 |
20844440265 ps |
| T837 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.1572075622 |
|
|
Apr 23 12:58:38 PM PDT 24 |
Apr 23 01:01:03 PM PDT 24 |
3167372857 ps |
| T31 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.3454920511 |
|
|
Apr 23 12:51:17 PM PDT 24 |
Apr 23 12:51:21 PM PDT 24 |
307647267 ps |
| T838 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3287624901 |
|
|
Apr 23 01:02:22 PM PDT 24 |
Apr 23 01:02:28 PM PDT 24 |
2786160199 ps |
| T839 |
/workspace/coverage/default/19.sram_ctrl_executable.2158629667 |
|
|
Apr 23 12:55:23 PM PDT 24 |
Apr 23 01:09:33 PM PDT 24 |
11694208565 ps |
| T840 |
/workspace/coverage/default/28.sram_ctrl_executable.3615739232 |
|
|
Apr 23 12:58:25 PM PDT 24 |
Apr 23 01:07:09 PM PDT 24 |
31228714290 ps |
| T841 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.259209236 |
|
|
Apr 23 01:04:25 PM PDT 24 |
Apr 23 01:04:33 PM PDT 24 |
6633889665 ps |
| T842 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.648662184 |
|
|
Apr 23 12:50:36 PM PDT 24 |
Apr 23 12:50:47 PM PDT 24 |
7475895733 ps |
| T843 |
/workspace/coverage/default/2.sram_ctrl_smoke.1402138941 |
|
|
Apr 23 12:50:58 PM PDT 24 |
Apr 23 12:51:07 PM PDT 24 |
2083579476 ps |
| T844 |
/workspace/coverage/default/18.sram_ctrl_smoke.916097162 |
|
|
Apr 23 12:54:55 PM PDT 24 |
Apr 23 12:55:06 PM PDT 24 |
469579369 ps |
| T845 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.1812223094 |
|
|
Apr 23 12:55:12 PM PDT 24 |
Apr 23 12:57:11 PM PDT 24 |
2536222145 ps |
| T846 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.694537240 |
|
|
Apr 23 01:02:43 PM PDT 24 |
Apr 23 01:03:28 PM PDT 24 |
759757931 ps |
| T847 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1128939352 |
|
|
Apr 23 01:04:59 PM PDT 24 |
Apr 23 01:05:03 PM PDT 24 |
704981975 ps |
| T848 |
/workspace/coverage/default/7.sram_ctrl_smoke.3491984393 |
|
|
Apr 23 12:52:15 PM PDT 24 |
Apr 23 12:52:38 PM PDT 24 |
3917945199 ps |
| T849 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2581170861 |
|
|
Apr 23 01:05:07 PM PDT 24 |
Apr 23 01:10:10 PM PDT 24 |
5715382894 ps |
| T850 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.125615436 |
|
|
Apr 23 01:04:39 PM PDT 24 |
Apr 23 01:05:53 PM PDT 24 |
1473023012 ps |
| T851 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.3435164322 |
|
|
Apr 23 12:58:43 PM PDT 24 |
Apr 23 01:28:50 PM PDT 24 |
83968901300 ps |
| T852 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.1487897983 |
|
|
Apr 23 01:01:08 PM PDT 24 |
Apr 23 01:01:12 PM PDT 24 |
374232157 ps |
| T853 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2744247672 |
|
|
Apr 23 12:53:39 PM PDT 24 |
Apr 23 12:54:32 PM PDT 24 |
17524645188 ps |
| T854 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4281034564 |
|
|
Apr 23 01:05:50 PM PDT 24 |
Apr 23 01:10:02 PM PDT 24 |
10765647365 ps |
| T855 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.3538566903 |
|
|
Apr 23 12:59:58 PM PDT 24 |
Apr 23 01:00:01 PM PDT 24 |
351868387 ps |
| T856 |
/workspace/coverage/default/5.sram_ctrl_smoke.1535183785 |
|
|
Apr 23 12:51:48 PM PDT 24 |
Apr 23 12:52:26 PM PDT 24 |
3326594336 ps |
| T857 |
/workspace/coverage/default/22.sram_ctrl_bijection.576623961 |
|
|
Apr 23 12:56:12 PM PDT 24 |
Apr 23 01:28:29 PM PDT 24 |
239415527858 ps |
| T858 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1144296324 |
|
|
Apr 23 01:03:56 PM PDT 24 |
Apr 23 01:08:00 PM PDT 24 |
7261366343 ps |
| T859 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.1236224077 |
|
|
Apr 23 12:57:12 PM PDT 24 |
Apr 23 12:58:09 PM PDT 24 |
47919631615 ps |
| T860 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3177622361 |
|
|
Apr 23 12:53:35 PM PDT 24 |
Apr 23 12:55:56 PM PDT 24 |
14052301560 ps |
| T861 |
/workspace/coverage/default/21.sram_ctrl_executable.2811455072 |
|
|
Apr 23 12:55:57 PM PDT 24 |
Apr 23 01:09:35 PM PDT 24 |
23202937856 ps |
| T862 |
/workspace/coverage/default/36.sram_ctrl_alert_test.582423459 |
|
|
Apr 23 01:01:32 PM PDT 24 |
Apr 23 01:01:33 PM PDT 24 |
34459965 ps |
| T863 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1343312547 |
|
|
Apr 23 12:53:07 PM PDT 24 |
Apr 23 01:06:10 PM PDT 24 |
127237512256 ps |
| T864 |
/workspace/coverage/default/13.sram_ctrl_stress_all.2896183612 |
|
|
Apr 23 12:53:50 PM PDT 24 |
Apr 23 02:26:14 PM PDT 24 |
300127816014 ps |
| T865 |
/workspace/coverage/default/32.sram_ctrl_stress_all.4047733284 |
|
|
Apr 23 01:00:05 PM PDT 24 |
Apr 23 01:46:09 PM PDT 24 |
182924864664 ps |
| T866 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1997186022 |
|
|
Apr 23 12:53:31 PM PDT 24 |
Apr 23 12:54:04 PM PDT 24 |
60099633010 ps |
| T867 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.2320996464 |
|
|
Apr 23 01:00:33 PM PDT 24 |
Apr 23 01:16:20 PM PDT 24 |
152331085118 ps |
| T868 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2983175200 |
|
|
Apr 23 12:50:52 PM PDT 24 |
Apr 23 12:51:43 PM PDT 24 |
34339795004 ps |
| T869 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.823871817 |
|
|
Apr 23 12:56:16 PM PDT 24 |
Apr 23 01:01:01 PM PDT 24 |
5615777360 ps |
| T870 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.251068439 |
|
|
Apr 23 01:06:01 PM PDT 24 |
Apr 23 01:08:42 PM PDT 24 |
9953179447 ps |
| T871 |
/workspace/coverage/default/9.sram_ctrl_bijection.1332868635 |
|
|
Apr 23 12:52:39 PM PDT 24 |
Apr 23 01:25:19 PM PDT 24 |
56902407711 ps |
| T872 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1869288042 |
|
|
Apr 23 12:51:11 PM PDT 24 |
Apr 23 12:56:47 PM PDT 24 |
54585166413 ps |
| T873 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3656642087 |
|
|
Apr 23 01:05:26 PM PDT 24 |
Apr 23 01:09:28 PM PDT 24 |
7629184545 ps |
| T874 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.1723930342 |
|
|
Apr 23 12:54:37 PM PDT 24 |
Apr 23 01:06:19 PM PDT 24 |
11785450499 ps |
| T875 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.2637109043 |
|
|
Apr 23 12:59:37 PM PDT 24 |
Apr 23 01:00:23 PM PDT 24 |
14663782763 ps |
| T876 |
/workspace/coverage/default/44.sram_ctrl_executable.346548900 |
|
|
Apr 23 01:04:25 PM PDT 24 |
Apr 23 01:18:28 PM PDT 24 |
19986305222 ps |
| T877 |
/workspace/coverage/default/2.sram_ctrl_partial_access.1388912833 |
|
|
Apr 23 12:51:02 PM PDT 24 |
Apr 23 12:51:26 PM PDT 24 |
1514555638 ps |
| T878 |
/workspace/coverage/default/19.sram_ctrl_alert_test.1381335863 |
|
|
Apr 23 12:55:27 PM PDT 24 |
Apr 23 12:55:28 PM PDT 24 |
22283610 ps |
| T879 |
/workspace/coverage/default/1.sram_ctrl_stress_all.2377357775 |
|
|
Apr 23 12:50:57 PM PDT 24 |
Apr 23 02:12:12 PM PDT 24 |
127184396084 ps |
| T880 |
/workspace/coverage/default/0.sram_ctrl_executable.2355327382 |
|
|
Apr 23 12:50:40 PM PDT 24 |
Apr 23 01:18:17 PM PDT 24 |
49301762637 ps |
| T881 |
/workspace/coverage/default/47.sram_ctrl_bijection.447936686 |
|
|
Apr 23 01:05:23 PM PDT 24 |
Apr 23 01:52:15 PM PDT 24 |
374778065822 ps |
| T882 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3213087666 |
|
|
Apr 23 01:00:01 PM PDT 24 |
Apr 23 01:02:25 PM PDT 24 |
8750574322 ps |
| T883 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3158662104 |
|
|
Apr 23 01:05:42 PM PDT 24 |
Apr 23 02:16:01 PM PDT 24 |
516543063628 ps |
| T884 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2659679774 |
|
|
Apr 23 12:55:40 PM PDT 24 |
Apr 23 12:56:43 PM PDT 24 |
795437831 ps |
| T885 |
/workspace/coverage/default/39.sram_ctrl_stress_all.4238672227 |
|
|
Apr 23 01:02:33 PM PDT 24 |
Apr 23 02:47:48 PM PDT 24 |
1215777228537 ps |
| T886 |
/workspace/coverage/default/34.sram_ctrl_smoke.2023682206 |
|
|
Apr 23 01:00:25 PM PDT 24 |
Apr 23 01:00:36 PM PDT 24 |
1062893538 ps |
| T887 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1057302335 |
|
|
Apr 23 12:50:52 PM PDT 24 |
Apr 23 12:55:05 PM PDT 24 |
10418726531 ps |
| T888 |
/workspace/coverage/default/1.sram_ctrl_bijection.2769201392 |
|
|
Apr 23 12:50:50 PM PDT 24 |
Apr 23 01:19:25 PM PDT 24 |
295101824217 ps |
| T889 |
/workspace/coverage/default/22.sram_ctrl_regwen.2828672794 |
|
|
Apr 23 12:56:23 PM PDT 24 |
Apr 23 01:13:09 PM PDT 24 |
6169046092 ps |
| T890 |
/workspace/coverage/default/32.sram_ctrl_regwen.2499396691 |
|
|
Apr 23 12:59:59 PM PDT 24 |
Apr 23 01:33:13 PM PDT 24 |
24807148321 ps |
| T891 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2339636214 |
|
|
Apr 23 01:06:09 PM PDT 24 |
Apr 23 01:10:27 PM PDT 24 |
3249858271 ps |
| T892 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.321577888 |
|
|
Apr 23 12:58:23 PM PDT 24 |
Apr 23 12:58:28 PM PDT 24 |
1459622703 ps |
| T893 |
/workspace/coverage/default/17.sram_ctrl_smoke.1927352272 |
|
|
Apr 23 12:54:38 PM PDT 24 |
Apr 23 12:56:53 PM PDT 24 |
1198577585 ps |
| T894 |
/workspace/coverage/default/13.sram_ctrl_smoke.3056011755 |
|
|
Apr 23 12:53:39 PM PDT 24 |
Apr 23 12:53:54 PM PDT 24 |
3327710766 ps |
| T895 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3256013001 |
|
|
Apr 23 12:52:17 PM PDT 24 |
Apr 23 12:58:53 PM PDT 24 |
7498829993 ps |
| T896 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.2743780078 |
|
|
Apr 23 01:01:09 PM PDT 24 |
Apr 23 01:03:35 PM PDT 24 |
7261510545 ps |
| T897 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.309521757 |
|
|
Apr 23 01:02:55 PM PDT 24 |
Apr 23 01:05:43 PM PDT 24 |
22256322126 ps |
| T898 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3118720619 |
|
|
Apr 23 01:02:20 PM PDT 24 |
Apr 23 01:02:39 PM PDT 24 |
1313444212 ps |
| T899 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.1597854336 |
|
|
Apr 23 12:53:44 PM PDT 24 |
Apr 23 12:56:13 PM PDT 24 |
806819965 ps |
| T900 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1071554206 |
|
|
Apr 23 12:51:52 PM PDT 24 |
Apr 23 12:59:22 PM PDT 24 |
133792216327 ps |
| T901 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3107852962 |
|
|
Apr 23 01:02:22 PM PDT 24 |
Apr 23 01:14:33 PM PDT 24 |
42246421497 ps |
| T902 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3338160776 |
|
|
Apr 23 12:50:40 PM PDT 24 |
Apr 23 01:13:13 PM PDT 24 |
154701732013 ps |
| T903 |
/workspace/coverage/default/22.sram_ctrl_partial_access.1250734456 |
|
|
Apr 23 12:56:13 PM PDT 24 |
Apr 23 12:56:27 PM PDT 24 |
3790620375 ps |
| T904 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2768069719 |
|
|
Apr 23 12:54:42 PM PDT 24 |
Apr 23 01:00:28 PM PDT 24 |
14586566522 ps |
| T905 |
/workspace/coverage/default/0.sram_ctrl_smoke.297686754 |
|
|
Apr 23 12:50:35 PM PDT 24 |
Apr 23 12:50:53 PM PDT 24 |
1207502511 ps |
| T906 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2727288129 |
|
|
Apr 23 01:04:12 PM PDT 24 |
Apr 23 01:04:13 PM PDT 24 |
11465294 ps |
| T907 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.1347063338 |
|
|
Apr 23 12:51:19 PM PDT 24 |
Apr 23 12:52:35 PM PDT 24 |
3057240399 ps |
| T908 |
/workspace/coverage/default/32.sram_ctrl_partial_access.3682587720 |
|
|
Apr 23 12:59:46 PM PDT 24 |
Apr 23 01:00:08 PM PDT 24 |
6058407773 ps |
| T909 |
/workspace/coverage/default/16.sram_ctrl_regwen.1714796711 |
|
|
Apr 23 12:54:31 PM PDT 24 |
Apr 23 01:05:53 PM PDT 24 |
19828611914 ps |
| T910 |
/workspace/coverage/default/41.sram_ctrl_regwen.591240713 |
|
|
Apr 23 01:03:18 PM PDT 24 |
Apr 23 01:16:16 PM PDT 24 |
8849114691 ps |
| T911 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.220312695 |
|
|
Apr 23 12:53:02 PM PDT 24 |
Apr 23 12:53:06 PM PDT 24 |
963104570 ps |
| T912 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.1772463717 |
|
|
Apr 23 12:59:00 PM PDT 24 |
Apr 23 01:25:35 PM PDT 24 |
64157501769 ps |
| T913 |
/workspace/coverage/default/28.sram_ctrl_bijection.85109545 |
|
|
Apr 23 12:58:09 PM PDT 24 |
Apr 23 01:18:40 PM PDT 24 |
288278231717 ps |
| T914 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.499636605 |
|
|
Apr 23 01:00:57 PM PDT 24 |
Apr 23 01:03:23 PM PDT 24 |
3257586455 ps |
| T915 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3839739696 |
|
|
Apr 23 12:52:25 PM PDT 24 |
Apr 23 01:01:37 PM PDT 24 |
61951246537 ps |
| T916 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3844001730 |
|
|
Apr 23 01:01:58 PM PDT 24 |
Apr 23 01:02:30 PM PDT 24 |
758475866 ps |
| T917 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3318961535 |
|
|
Apr 23 12:59:50 PM PDT 24 |
Apr 23 01:04:30 PM PDT 24 |
44266394368 ps |
| T918 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1030362684 |
|
|
Apr 23 12:54:41 PM PDT 24 |
Apr 23 12:56:31 PM PDT 24 |
775700607 ps |
| T919 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2883573472 |
|
|
Apr 23 12:52:02 PM PDT 24 |
Apr 23 12:57:27 PM PDT 24 |
4652516424 ps |
| T920 |
/workspace/coverage/default/39.sram_ctrl_executable.3387939620 |
|
|
Apr 23 01:02:23 PM PDT 24 |
Apr 23 01:05:20 PM PDT 24 |
7897034778 ps |
| T921 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2090902693 |
|
|
Apr 23 12:54:16 PM PDT 24 |
Apr 23 12:56:12 PM PDT 24 |
3163241131 ps |
| T922 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.318392295 |
|
|
Apr 23 12:53:48 PM PDT 24 |
Apr 23 12:54:10 PM PDT 24 |
1206860802 ps |
| T923 |
/workspace/coverage/default/49.sram_ctrl_bijection.237596304 |
|
|
Apr 23 01:06:10 PM PDT 24 |
Apr 23 01:20:49 PM PDT 24 |
148369727185 ps |
| T924 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3608478523 |
|
|
Apr 23 12:52:45 PM PDT 24 |
Apr 23 12:53:39 PM PDT 24 |
80100240939 ps |
| T925 |
/workspace/coverage/default/23.sram_ctrl_executable.3086931896 |
|
|
Apr 23 12:56:43 PM PDT 24 |
Apr 23 01:20:10 PM PDT 24 |
89870030451 ps |
| T926 |
/workspace/coverage/default/19.sram_ctrl_regwen.833970991 |
|
|
Apr 23 12:55:22 PM PDT 24 |
Apr 23 01:16:09 PM PDT 24 |
4531665892 ps |
| T927 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1617510758 |
|
|
Apr 23 01:01:41 PM PDT 24 |
Apr 23 01:33:50 PM PDT 24 |
87082447288 ps |
| T928 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.4253430906 |
|
|
Apr 23 01:06:00 PM PDT 24 |
Apr 23 01:06:04 PM PDT 24 |
1364121779 ps |
| T929 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.3783212807 |
|
|
Apr 23 01:00:14 PM PDT 24 |
Apr 23 01:11:36 PM PDT 24 |
23400378705 ps |
| T930 |
/workspace/coverage/default/16.sram_ctrl_executable.3477186097 |
|
|
Apr 23 12:54:30 PM PDT 24 |
Apr 23 01:03:59 PM PDT 24 |
23087793203 ps |
| T931 |
/workspace/coverage/default/27.sram_ctrl_executable.431938044 |
|
|
Apr 23 12:57:59 PM PDT 24 |
Apr 23 01:28:36 PM PDT 24 |
43609765420 ps |
| T932 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.577672933 |
|
|
Apr 23 01:03:03 PM PDT 24 |
Apr 23 01:07:50 PM PDT 24 |
5362837461 ps |
| T933 |
/workspace/coverage/default/32.sram_ctrl_alert_test.763123314 |
|
|
Apr 23 01:00:09 PM PDT 24 |
Apr 23 01:00:10 PM PDT 24 |
14537006 ps |
| T934 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.1372792879 |
|
|
Apr 23 01:01:41 PM PDT 24 |
Apr 23 01:03:02 PM PDT 24 |
24475108844 ps |
| T935 |
/workspace/coverage/default/39.sram_ctrl_smoke.4066838591 |
|
|
Apr 23 01:02:20 PM PDT 24 |
Apr 23 01:03:31 PM PDT 24 |
4460687847 ps |
| T936 |
/workspace/coverage/default/26.sram_ctrl_smoke.4194800197 |
|
|
Apr 23 12:57:19 PM PDT 24 |
Apr 23 12:57:35 PM PDT 24 |
1918077036 ps |
| T937 |
/workspace/coverage/default/8.sram_ctrl_executable.2930860715 |
|
|
Apr 23 12:52:30 PM PDT 24 |
Apr 23 01:01:47 PM PDT 24 |
40681094060 ps |
| T938 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1999879386 |
|
|
Apr 23 12:54:07 PM PDT 24 |
Apr 23 12:56:36 PM PDT 24 |
4603797196 ps |
| T939 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.527751056 |
|
|
Apr 23 01:01:51 PM PDT 24 |
Apr 23 01:23:35 PM PDT 24 |
24765671805 ps |
| T940 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3998206274 |
|
|
Apr 23 12:58:46 PM PDT 24 |
Apr 23 12:58:50 PM PDT 24 |
352234465 ps |
| T941 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2187024665 |
|
|
Apr 23 01:03:44 PM PDT 24 |
Apr 23 01:05:02 PM PDT 24 |
2998555858 ps |
| T942 |
/workspace/coverage/default/15.sram_ctrl_executable.2392284292 |
|
|
Apr 23 12:54:20 PM PDT 24 |
Apr 23 12:56:39 PM PDT 24 |
4296604495 ps |
| T943 |
/workspace/coverage/default/21.sram_ctrl_alert_test.3989595619 |
|
|
Apr 23 12:56:11 PM PDT 24 |
Apr 23 12:56:12 PM PDT 24 |
40142533 ps |
| T944 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.2128622400 |
|
|
Apr 23 01:03:05 PM PDT 24 |
Apr 23 01:24:27 PM PDT 24 |
17193020370 ps |
| T945 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.88940804 |
|
|
Apr 23 12:44:45 PM PDT 24 |
Apr 23 12:44:51 PM PDT 24 |
146357724 ps |
| T946 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3184774276 |
|
|
Apr 23 12:44:41 PM PDT 24 |
Apr 23 12:44:52 PM PDT 24 |
356480621 ps |
| T86 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.587140034 |
|
|
Apr 23 12:45:21 PM PDT 24 |
Apr 23 12:45:22 PM PDT 24 |
63225074 ps |
| T99 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1703460517 |
|
|
Apr 23 12:44:46 PM PDT 24 |
Apr 23 12:44:50 PM PDT 24 |
39845479 ps |
| T947 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.332817024 |
|
|
Apr 23 12:45:13 PM PDT 24 |
Apr 23 12:45:18 PM PDT 24 |
170875008 ps |
| T57 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2470839122 |
|
|
Apr 23 12:44:41 PM PDT 24 |
Apr 23 12:44:44 PM PDT 24 |
21396738 ps |
| T948 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3160784637 |
|
|
Apr 23 12:44:58 PM PDT 24 |
Apr 23 12:45:03 PM PDT 24 |
3762291165 ps |
| T93 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.332318874 |
|
|
Apr 23 12:44:44 PM PDT 24 |
Apr 23 12:44:49 PM PDT 24 |
33081939 ps |
| T126 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4104164626 |
|
|
Apr 23 12:45:04 PM PDT 24 |
Apr 23 12:45:06 PM PDT 24 |
47371956 ps |
| T949 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3763514862 |
|
|
Apr 23 12:44:58 PM PDT 24 |
Apr 23 12:45:03 PM PDT 24 |
1020107525 ps |
| T87 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3924169009 |
|
|
Apr 23 12:45:13 PM PDT 24 |
Apr 23 12:45:16 PM PDT 24 |
89979289 ps |
| T96 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3766121672 |
|
|
Apr 23 12:44:50 PM PDT 24 |
Apr 23 12:44:55 PM PDT 24 |
181045028 ps |
| T950 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1161867017 |
|
|
Apr 23 12:45:06 PM PDT 24 |
Apr 23 12:45:10 PM PDT 24 |
383666965 ps |
| T58 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3507333288 |
|
|
Apr 23 12:45:08 PM PDT 24 |
Apr 23 12:46:19 PM PDT 24 |
58794394695 ps |
| T951 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3992827138 |
|
|
Apr 23 12:45:00 PM PDT 24 |
Apr 23 12:45:04 PM PDT 24 |
169198236 ps |
| T952 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.780049915 |
|
|
Apr 23 12:44:41 PM PDT 24 |
Apr 23 12:44:52 PM PDT 24 |
351703554 ps |
| T97 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4098279247 |
|
|
Apr 23 12:44:41 PM PDT 24 |
Apr 23 12:44:44 PM PDT 24 |
303249592 ps |
| T94 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2213884467 |
|
|
Apr 23 12:44:55 PM PDT 24 |
Apr 23 12:44:59 PM PDT 24 |
169792333 ps |
| T88 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1200351806 |
|
|
Apr 23 12:44:41 PM PDT 24 |
Apr 23 12:44:44 PM PDT 24 |
19666203 ps |
| T59 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3944643464 |
|
|
Apr 23 12:44:48 PM PDT 24 |
Apr 23 12:44:52 PM PDT 24 |
12701612 ps |
| T60 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1963267771 |
|
|
Apr 23 12:44:50 PM PDT 24 |
Apr 23 12:45:48 PM PDT 24 |
7082166615 ps |
| T953 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3806829957 |
|
|
Apr 23 12:45:22 PM PDT 24 |
Apr 23 12:45:25 PM PDT 24 |
151209362 ps |
| T98 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3060440644 |
|
|
Apr 23 12:44:42 PM PDT 24 |
Apr 23 12:44:46 PM PDT 24 |
136953895 ps |
| T61 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2594671083 |
|
|
Apr 23 12:45:15 PM PDT 24 |
Apr 23 12:46:06 PM PDT 24 |
64311331344 ps |
| T954 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2013856192 |
|
|
Apr 23 12:44:52 PM PDT 24 |
Apr 23 12:44:59 PM PDT 24 |
1666632019 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2704260877 |
|
|
Apr 23 12:44:53 PM PDT 24 |
Apr 23 12:44:56 PM PDT 24 |
48079489 ps |
| T62 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.180544384 |
|
|
Apr 23 12:45:03 PM PDT 24 |
Apr 23 12:45:04 PM PDT 24 |
24991287 ps |
| T116 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.535059580 |
|
|
Apr 23 12:44:59 PM PDT 24 |
Apr 23 12:45:02 PM PDT 24 |
141582429 ps |
| T89 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.299509156 |
|
|
Apr 23 12:44:51 PM PDT 24 |
Apr 23 12:44:55 PM PDT 24 |
19701951 ps |
| T63 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3469476520 |
|
|
Apr 23 12:44:41 PM PDT 24 |
Apr 23 12:44:45 PM PDT 24 |
14386275 ps |
| T115 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1656048498 |
|
|
Apr 23 12:44:51 PM PDT 24 |
Apr 23 12:44:57 PM PDT 24 |
765591298 ps |
| T956 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.180295454 |
|
|
Apr 23 12:45:00 PM PDT 24 |
Apr 23 12:45:05 PM PDT 24 |
364684357 ps |
| T118 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2966362775 |
|
|
Apr 23 12:44:51 PM PDT 24 |
Apr 23 12:44:57 PM PDT 24 |
397058876 ps |
| T957 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3605980772 |
|
|
Apr 23 12:44:47 PM PDT 24 |
Apr 23 12:45:18 PM PDT 24 |
3715895005 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2972243643 |
|
|
Apr 23 12:44:42 PM PDT 24 |
Apr 23 12:44:48 PM PDT 24 |
365957239 ps |
| T64 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.872514698 |
|
|
Apr 23 12:45:00 PM PDT 24 |
Apr 23 12:45:53 PM PDT 24 |
33484621217 ps |
| T959 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3031750689 |
|
|
Apr 23 12:44:43 PM PDT 24 |
Apr 23 12:44:47 PM PDT 24 |
14151945 ps |
| T960 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2515498280 |
|
|
Apr 23 12:44:52 PM PDT 24 |
Apr 23 12:44:56 PM PDT 24 |
50802451 ps |
| T961 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2522547573 |
|
|
Apr 23 12:45:00 PM PDT 24 |
Apr 23 12:45:05 PM PDT 24 |
373724357 ps |
| T962 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2688890278 |
|
|
Apr 23 12:44:41 PM PDT 24 |
Apr 23 12:44:52 PM PDT 24 |
125309698 ps |
| T963 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.638948765 |
|
|
Apr 23 12:44:59 PM PDT 24 |
Apr 23 12:45:00 PM PDT 24 |
15820039 ps |
| T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3698948333 |
|
|
Apr 23 12:44:45 PM PDT 24 |
Apr 23 12:44:49 PM PDT 24 |
14459309 ps |
| T965 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4216577044 |
|
|
Apr 23 12:45:02 PM PDT 24 |
Apr 23 12:45:07 PM PDT 24 |
1522813464 ps |
| T122 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.631032105 |
|
|
Apr 23 12:44:32 PM PDT 24 |
Apr 23 12:44:34 PM PDT 24 |
139563181 ps |
| T65 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.51845467 |
|
|
Apr 23 12:44:43 PM PDT 24 |
Apr 23 12:44:48 PM PDT 24 |
36558292 ps |
| T66 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3392339718 |
|
|
Apr 23 12:44:45 PM PDT 24 |
Apr 23 12:45:21 PM PDT 24 |
14818797558 ps |
| T966 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2841365041 |
|
|
Apr 23 12:44:40 PM PDT 24 |
Apr 23 12:44:43 PM PDT 24 |
53292255 ps |
| T967 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1304908369 |
|
|
Apr 23 12:44:47 PM PDT 24 |
Apr 23 12:44:52 PM PDT 24 |
152647519 ps |
| T123 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1774975334 |
|
|
Apr 23 12:44:51 PM PDT 24 |
Apr 23 12:44:56 PM PDT 24 |
171224753 ps |
| T121 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.401715619 |
|
|
Apr 23 12:45:01 PM PDT 24 |
Apr 23 12:45:04 PM PDT 24 |
118283477 ps |
| T70 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.850253708 |
|
|
Apr 23 12:45:00 PM PDT 24 |
Apr 23 12:46:03 PM PDT 24 |
30584455154 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1010668465 |
|
|
Apr 23 12:44:50 PM PDT 24 |
Apr 23 12:44:56 PM PDT 24 |
821499923 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3543739188 |
|
|
Apr 23 12:44:50 PM PDT 24 |
Apr 23 12:44:54 PM PDT 24 |
111611850 ps |
| T970 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3096998977 |
|
|
Apr 23 12:44:50 PM PDT 24 |
Apr 23 12:44:54 PM PDT 24 |
12073203 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2994676580 |
|
|
Apr 23 12:44:44 PM PDT 24 |
Apr 23 12:44:50 PM PDT 24 |
105389597 ps |
| T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1163837496 |
|
|
Apr 23 12:44:57 PM PDT 24 |
Apr 23 12:45:03 PM PDT 24 |
868738988 ps |
| T973 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2741669599 |
|
|
Apr 23 12:45:05 PM PDT 24 |
Apr 23 12:45:06 PM PDT 24 |
18648948 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3224076188 |
|
|
Apr 23 12:44:56 PM PDT 24 |
Apr 23 12:44:58 PM PDT 24 |
41002349 ps |
| T975 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1696046580 |
|
|
Apr 23 12:44:51 PM PDT 24 |
Apr 23 12:44:56 PM PDT 24 |
606233526 ps |
| T976 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3878393965 |
|
|
Apr 23 12:44:42 PM PDT 24 |
Apr 23 12:44:48 PM PDT 24 |
360894587 ps |
| T119 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.480511476 |
|
|
Apr 23 12:44:52 PM PDT 24 |
Apr 23 12:44:57 PM PDT 24 |
180682413 ps |
| T977 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1483494477 |
|
|
Apr 23 12:44:49 PM PDT 24 |
Apr 23 12:44:56 PM PDT 24 |
1448677746 ps |
| T117 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2262491585 |
|
|
Apr 23 12:44:58 PM PDT 24 |
Apr 23 12:45:01 PM PDT 24 |
139253128 ps |
| T978 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1287938869 |
|
|
Apr 23 12:44:47 PM PDT 24 |
Apr 23 12:45:23 PM PDT 24 |
15382681886 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3672022726 |
|
|
Apr 23 12:44:42 PM PDT 24 |
Apr 23 12:44:46 PM PDT 24 |
360953312 ps |
| T71 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.355546350 |
|
|
Apr 23 12:44:43 PM PDT 24 |
Apr 23 12:45:41 PM PDT 24 |
16026710122 ps |
| T72 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1511119100 |
|
|
Apr 23 12:44:53 PM PDT 24 |
Apr 23 12:45:49 PM PDT 24 |
7093725176 ps |
| T73 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3611850921 |
|
|
Apr 23 12:44:44 PM PDT 24 |
Apr 23 12:44:48 PM PDT 24 |
20460209 ps |
| T980 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2221161084 |
|
|
Apr 23 12:44:45 PM PDT 24 |
Apr 23 12:44:52 PM PDT 24 |
107064623 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4205095561 |
|
|
Apr 23 12:44:56 PM PDT 24 |
Apr 23 12:44:58 PM PDT 24 |
26488666 ps |
| T120 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.696561552 |
|
|
Apr 23 12:44:52 PM PDT 24 |
Apr 23 12:44:57 PM PDT 24 |
174746993 ps |
| T982 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2440139434 |
|
|
Apr 23 12:44:47 PM PDT 24 |
Apr 23 12:44:51 PM PDT 24 |
16534595 ps |
| T983 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3081255449 |
|
|
Apr 23 12:45:02 PM PDT 24 |
Apr 23 12:45:07 PM PDT 24 |
120047050 ps |
| T984 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.730930181 |
|
|
Apr 23 12:44:44 PM PDT 24 |
Apr 23 12:44:49 PM PDT 24 |
59298906 ps |
| T985 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2693996209 |
|
|
Apr 23 12:44:56 PM PDT 24 |
Apr 23 12:45:02 PM PDT 24 |
231778785 ps |
| T986 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3328653957 |
|
|
Apr 23 12:44:55 PM PDT 24 |
Apr 23 12:44:57 PM PDT 24 |
41232779 ps |
| T79 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1391548263 |
|
|
Apr 23 12:44:51 PM PDT 24 |
Apr 23 12:44:55 PM PDT 24 |
76558003 ps |
| T987 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.484584555 |
|
|
Apr 23 12:44:51 PM PDT 24 |
Apr 23 12:44:59 PM PDT 24 |
240652038 ps |
| T988 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3757925409 |
|
|
Apr 23 12:44:54 PM PDT 24 |
Apr 23 12:44:57 PM PDT 24 |
80285741 ps |
| T80 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1123968833 |
|
|
Apr 23 12:45:09 PM PDT 24 |
Apr 23 12:45:38 PM PDT 24 |
7240301062 ps |
| T989 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.305756421 |
|
|
Apr 23 12:44:54 PM PDT 24 |
Apr 23 12:45:00 PM PDT 24 |
474802261 ps |
| T81 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.901608570 |
|
|
Apr 23 12:44:50 PM PDT 24 |
Apr 23 12:45:48 PM PDT 24 |
30632567048 ps |
| T990 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.896622747 |
|
|
Apr 23 12:45:03 PM PDT 24 |
Apr 23 12:45:04 PM PDT 24 |
145396774 ps |
| T991 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1642878068 |
|
|
Apr 23 12:45:03 PM PDT 24 |
Apr 23 12:45:04 PM PDT 24 |
14535308 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2699936280 |
|
|
Apr 23 12:44:58 PM PDT 24 |
Apr 23 12:45:00 PM PDT 24 |
365877353 ps |
| T993 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2935525290 |
|
|
Apr 23 12:44:46 PM PDT 24 |
Apr 23 12:44:50 PM PDT 24 |
23183897 ps |
| T994 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.859795366 |
|
|
Apr 23 12:44:54 PM PDT 24 |
Apr 23 12:44:57 PM PDT 24 |
120632868 ps |
| T995 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1175161907 |
|
|
Apr 23 12:45:09 PM PDT 24 |
Apr 23 12:45:11 PM PDT 24 |
26106260 ps |
| T996 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.677313250 |
|
|
Apr 23 12:44:58 PM PDT 24 |
Apr 23 12:45:03 PM PDT 24 |
1354326908 ps |
| T997 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2156170854 |
|
|
Apr 23 12:45:00 PM PDT 24 |
Apr 23 12:45:02 PM PDT 24 |
12749895 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2616311617 |
|
|
Apr 23 12:44:40 PM PDT 24 |
Apr 23 12:44:46 PM PDT 24 |
1439729177 ps |
| T999 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1391523203 |
|
|
Apr 23 12:44:54 PM PDT 24 |
Apr 23 12:44:58 PM PDT 24 |
19891007 ps |
| T1000 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.466050771 |
|
|
Apr 23 12:44:52 PM PDT 24 |
Apr 23 12:44:57 PM PDT 24 |
148102292 ps |
| T1001 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2852417428 |
|
|
Apr 23 12:44:52 PM PDT 24 |
Apr 23 12:44:58 PM PDT 24 |
36783555 ps |
| T1002 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2924162203 |
|
|
Apr 23 12:44:58 PM PDT 24 |
Apr 23 12:45:03 PM PDT 24 |
105880955 ps |
| T1003 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4096184926 |
|
|
Apr 23 12:44:47 PM PDT 24 |
Apr 23 12:44:55 PM PDT 24 |
714845151 ps |
| T125 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3893211540 |
|
|
Apr 23 12:44:44 PM PDT 24 |
Apr 23 12:44:51 PM PDT 24 |
908223130 ps |
| T1004 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4028112663 |
|
|
Apr 23 12:44:46 PM PDT 24 |
Apr 23 12:44:51 PM PDT 24 |
29307505 ps |