Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16430290	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

154164631

1

T1

35798

T2

26355

T3

1125

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	84125117	1			T1	98240		T2	72965		T3	536
values[0x0]	41593725	1			T1	32856		T2	24403		T3	277
values[0x1]	44876079	1			T1	65197		T2	48395		T3	312

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8345769	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

162249152

1

T1

116623

T2

85842

T3

1125

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	557603	1			T1	774		T2	550		T3	2
valid_sources[0x01]	556221	1			T1	757		T2	564		T4	1318
valid_sources[0x02]	595870	1			T1	846		T2	553		T4	1382
valid_sources[0x03]	610462	1			T1	722		T2	551		T3	2
valid_sources[0x04]	630867	1			T1	820		T2	535		T4	1229
valid_sources[0x05]	582666	1			T1	779		T2	544		T3	16
valid_sources[0x06]	542146	1			T1	786		T2	560		T4	1281
valid_sources[0x07]	593905	1			T1	808		T2	561		T3	15
valid_sources[0x08]	573512	1			T1	756		T2	592		T4	1204
valid_sources[0x09]	599416	1			T1	750		T2	551		T3	32
valid_sources[0x0a]	612647	1			T1	746		T2	583		T4	1270
valid_sources[0x0b]	631051	1			T1	785		T2	541		T3	23
valid_sources[0x0c]	578234	1			T1	789		T2	592		T3	3
valid_sources[0x0d]	631805	1			T1	633		T2	574		T3	3
valid_sources[0x0e]	2057602	1			T1	801		T2	524		T4	1151
valid_sources[0x0f]	1367995	1			T1	784		T2	560		T4	1291
valid_sources[0x10]	634344	1			T1	851		T2	578		T4	1305
valid_sources[0x11]	539788	1			T1	733		T2	509		T4	1245
valid_sources[0x12]	630757	1			T1	717		T2	547		T3	1
valid_sources[0x13]	575252	1			T1	738		T2	580		T3	4
valid_sources[0x14]	541952	1			T1	809		T2	559		T4	1228
valid_sources[0x15]	615846	1			T1	797		T2	588		T4	1243
valid_sources[0x16]	619617	1			T1	790		T2	612		T4	1266
valid_sources[0x17]	590984	1			T1	801		T2	596		T4	1234
valid_sources[0x18]	1576315	1			T1	801		T2	575		T4	1292
valid_sources[0x19]	560033	1			T1	780		T2	529		T4	1316
valid_sources[0x1a]	562570	1			T1	834		T2	562		T3	19
valid_sources[0x1b]	555568	1			T1	734		T2	553		T4	1225
valid_sources[0x1c]	613419	1			T1	770		T2	557		T4	1218
valid_sources[0x1d]	603526	1			T1	707		T2	556		T3	2
valid_sources[0x1e]	541809	1			T1	764		T2	570		T4	1253
valid_sources[0x1f]	1553051	1			T1	892		T2	566		T3	2
valid_sources[0x20]	574149	1			T1	769		T2	549		T3	8
valid_sources[0x21]	648545	1			T1	746		T2	582		T4	1293
valid_sources[0x22]	576359	1			T1	658		T2	572		T4	1235
valid_sources[0x23]	647802	1			T1	736		T2	570		T4	1313
valid_sources[0x24]	553480	1			T1	779		T2	582		T3	7
valid_sources[0x25]	573315	1			T1	731		T2	561		T4	1278
valid_sources[0x26]	618623	1			T1	780		T2	525		T3	13
valid_sources[0x27]	577909	1			T1	756		T2	560		T4	1203
valid_sources[0x28]	555208	1			T1	723		T2	546		T4	1216
valid_sources[0x29]	537226	1			T1	730		T2	581		T3	2
valid_sources[0x2a]	616536	1			T1	783		T2	577		T4	1144
valid_sources[0x2b]	654230	1			T1	765		T2	570		T4	1287
valid_sources[0x2c]	557250	1			T1	678		T2	556		T4	1270
valid_sources[0x2d]	767993	1			T1	767		T2	612		T3	7
valid_sources[0x2e]	601430	1			T1	874		T2	620		T3	2
valid_sources[0x2f]	577907	1			T1	739		T2	532		T4	1323
valid_sources[0x30]	566128	1			T1	740		T2	634		T4	1328
valid_sources[0x31]	931111	1			T1	824		T2	578		T4	1341
valid_sources[0x32]	581105	1			T1	776		T2	558		T4	1143
valid_sources[0x33]	552401	1			T1	756		T2	558		T3	17
valid_sources[0x34]	1564756	1			T1	744		T2	573		T3	7
valid_sources[0x35]	622435	1			T1	722		T2	577		T3	21
valid_sources[0x36]	580256	1			T1	818		T2	586		T3	2
valid_sources[0x37]	560786	1			T1	691		T2	564		T4	1183
valid_sources[0x38]	605454	1			T1	708		T2	555		T3	1
valid_sources[0x39]	599583	1			T1	751		T2	607		T3	7
valid_sources[0x3a]	542946	1			T1	780		T2	599		T3	5
valid_sources[0x3b]	543421	1			T1	833		T2	532		T4	1260
valid_sources[0x3c]	560816	1			T1	772		T2	550		T4	1243
valid_sources[0x3d]	632144	1			T1	772		T2	560		T3	4
valid_sources[0x3e]	583798	1			T1	818		T2	581		T4	1165
valid_sources[0x3f]	644325	1			T1	812		T2	562		T4	1369
valid_sources[0x40]	546217	1			T1	758		T2	588		T4	1177
valid_sources[0x41]	581372	1			T1	850		T2	565		T4	1213
valid_sources[0x42]	614685	1			T1	696		T2	552		T3	6
valid_sources[0x43]	612497	1			T1	754		T2	592		T4	1209
valid_sources[0x44]	543495	1			T1	740		T2	571		T3	11
valid_sources[0x45]	556497	1			T1	791		T2	542		T3	5
valid_sources[0x46]	543358	1			T1	759		T2	585		T4	1214
valid_sources[0x47]	561230	1			T1	759		T2	605		T3	1
valid_sources[0x48]	582447	1			T1	754		T2	548		T3	16
valid_sources[0x49]	764945	1			T1	844		T2	561		T4	1195
valid_sources[0x4a]	563897	1			T1	684		T2	570		T4	1336
valid_sources[0x4b]	555173	1			T1	847		T2	601		T4	1232
valid_sources[0x4c]	586882	1			T1	757		T2	595		T4	1165
valid_sources[0x4d]	561294	1			T1	695		T2	585		T3	2
valid_sources[0x4e]	556358	1			T1	791		T2	623		T4	1242
valid_sources[0x4f]	662886	1			T1	757		T2	579		T3	14
valid_sources[0x50]	609745	1			T1	824		T2	608		T4	1243
valid_sources[0x51]	586841	1			T1	801		T2	600		T4	1338
valid_sources[0x52]	539834	1			T1	743		T2	586		T3	4
valid_sources[0x53]	566404	1			T1	863		T2	598		T4	1198
valid_sources[0x54]	553418	1			T1	830		T2	591		T4	1247
valid_sources[0x55]	534189	1			T1	652		T2	588		T4	1251
valid_sources[0x56]	602593	1			T1	837		T2	578		T3	17
valid_sources[0x57]	607184	1			T1	743		T2	568		T4	1182
valid_sources[0x58]	594599	1			T1	793		T2	578		T3	22
valid_sources[0x59]	580505	1			T1	744		T2	579		T3	16
valid_sources[0x5a]	1429388	1			T1	817		T2	571		T4	1199
valid_sources[0x5b]	545306	1			T1	774		T2	534		T4	1268
valid_sources[0x5c]	2192107	1			T1	676		T2	603		T4	1217
valid_sources[0x5d]	611793	1			T1	791		T2	585		T3	3
valid_sources[0x5e]	550417	1			T1	790		T2	602		T3	27
valid_sources[0x5f]	597522	1			T1	836		T2	542		T3	17
valid_sources[0x60]	575575	1			T1	803		T2	558		T3	8
valid_sources[0x61]	548946	1			T1	788		T2	531		T3	11
valid_sources[0x62]	579382	1			T1	824		T2	574		T3	4
valid_sources[0x63]	618765	1			T1	827		T2	557		T3	9
valid_sources[0x64]	1255280	1			T1	802		T2	572		T3	48
valid_sources[0x65]	567136	1			T1	803		T2	583		T3	5
valid_sources[0x66]	544322	1			T1	688		T2	534		T3	3
valid_sources[0x67]	559436	1			T1	850		T2	577		T4	1318
valid_sources[0x68]	555539	1			T1	809		T2	556		T4	1232
valid_sources[0x69]	544284	1			T1	786		T2	624		T3	4
valid_sources[0x6a]	533622	1			T1	729		T2	546		T4	1236
valid_sources[0x6b]	551151	1			T1	788		T2	538		T4	1250
valid_sources[0x6c]	578199	1			T1	843		T2	574		T3	5
valid_sources[0x6d]	568405	1			T1	713		T2	591		T4	1185
valid_sources[0x6e]	601574	1			T1	724		T2	571		T4	1373
valid_sources[0x6f]	585849	1			T1	690		T2	569		T4	1275
valid_sources[0x70]	554650	1			T1	656		T2	530		T3	2
valid_sources[0x71]	565637	1			T1	665		T2	592		T3	25
valid_sources[0x72]	666379	1			T1	717		T2	523		T3	19
valid_sources[0x73]	561762	1			T1	735		T2	636		T4	1208
valid_sources[0x74]	622334	1			T1	679		T2	595		T3	9
valid_sources[0x75]	608386	1			T1	786		T2	559		T3	4
valid_sources[0x76]	580079	1			T1	795		T2	584		T4	1165
valid_sources[0x77]	545654	1			T1	813		T2	543		T4	1222
valid_sources[0x78]	579269	1			T1	873		T2	547		T3	14
valid_sources[0x79]	576598	1			T1	727		T2	613		T4	1239
valid_sources[0x7a]	556616	1			T1	782		T2	548		T4	1305
valid_sources[0x7b]	547330	1			T1	742		T2	554		T4	1265
valid_sources[0x7c]	539064	1			T1	845		T2	574		T4	1302
valid_sources[0x7d]	652769	1			T1	765		T2	547		T4	1295
valid_sources[0x7e]	572286	1			T1	806		T2	578		T3	36
valid_sources[0x7f]	594599	1			T1	746		T2	558		T4	1333
valid_sources[0x80]	556610	1			T1	728		T2	580		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75869829

1

T1

17800

T2

13291

T3

536

values[0x0]

all_enables

biggest_size

39142609

1

T1

8891

T2

6536

T3

277

values[0x1]

all_enables

biggest_size

39152193

1

T1

9107

T2

6528

T3

312

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

141232

1

T1

2

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50871	1			T5	34		T11	14		T14	17
values[0x0]	59647	1			T1	2		T2	2		T4	2
values[0x1]	63724	1			T1	5		T2	1		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149298

1

T1

3

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	514	1			T25	3		T26	13		T69	1
valid_sources[0x01]	641	1			T14	5		T25	3		T26	14
valid_sources[0x02]	688	1			T11	1		T25	6		T7	2
valid_sources[0x03]	565	1			T25	10		T26	11		T68	1
valid_sources[0x04]	697	1			T25	4		T26	11		T128	3
valid_sources[0x05]	659	1			T25	9		T39	1		T26	18
valid_sources[0x06]	648	1			T25	12		T26	20		T69	1
valid_sources[0x07]	518	1			T10	1		T6	1		T49	2
valid_sources[0x08]	583	1			T14	1		T25	7		T26	12
valid_sources[0x09]	523	1			T6	2		T25	14		T26	6
valid_sources[0x0a]	771	1			T28	1		T25	8		T26	22
valid_sources[0x0b]	521	1			T25	6		T26	31		T50	1
valid_sources[0x0c]	721	1			T13	21		T6	3		T25	11
valid_sources[0x0d]	623	1			T25	15		T26	14		T41	1
valid_sources[0x0e]	519	1			T12	1		T25	6		T26	22
valid_sources[0x0f]	1140	1			T25	9		T26	6		T128	2
valid_sources[0x10]	816	1			T25	6		T39	1		T26	4
valid_sources[0x11]	462	1			T25	8		T26	2		T136	11
valid_sources[0x12]	585	1			T11	2		T49	1		T25	8
valid_sources[0x13]	741	1			T14	1		T25	16		T37	2
valid_sources[0x14]	580	1			T49	1		T25	12		T39	2
valid_sources[0x15]	562	1			T11	1		T6	1		T25	6
valid_sources[0x16]	761	1			T25	6		T35	1		T26	7
valid_sources[0x17]	1435	1			T6	1		T25	14		T26	14
valid_sources[0x18]	612	1			T6	1		T25	6		T26	9
valid_sources[0x19]	582	1			T49	1		T25	9		T137	1
valid_sources[0x1a]	576	1			T14	1		T32	9		T25	9
valid_sources[0x1b]	638	1			T25	12		T39	1		T26	10
valid_sources[0x1c]	703	1			T25	5		T138	1		T26	1
valid_sources[0x1d]	515	1			T25	5		T39	1		T26	7
valid_sources[0x1e]	710	1			T25	10		T26	3		T71	1
valid_sources[0x1f]	822	1			T6	1		T25	7		T26	1
valid_sources[0x20]	540	1			T6	1		T25	11		T26	22
valid_sources[0x21]	562	1			T14	2		T25	7		T39	1
valid_sources[0x22]	539	1			T25	11		T36	1		T26	7
valid_sources[0x23]	767	1			T14	2		T25	6		T26	32
valid_sources[0x24]	695	1			T49	1		T25	11		T39	7
valid_sources[0x25]	620	1			T6	1		T49	2		T25	12
valid_sources[0x26]	488	1			T49	1		T25	12		T128	2
valid_sources[0x27]	572	1			T25	2		T41	1		T139	2
valid_sources[0x28]	806	1			T25	7		T26	17		T140	1
valid_sources[0x29]	796	1			T25	2		T26	23		T40	3
valid_sources[0x2a]	631	1			T49	1		T25	7		T7	2
valid_sources[0x2b]	811	1			T25	3		T71	3		T41	1
valid_sources[0x2c]	635	1			T14	2		T25	11		T26	8
valid_sources[0x2d]	537	1			T25	8		T26	44		T40	1
valid_sources[0x2e]	589	1			T49	1		T25	3		T138	1
valid_sources[0x2f]	506	1			T14	6		T6	2		T49	2
valid_sources[0x30]	749	1			T6	1		T25	12		T26	1
valid_sources[0x31]	825	1			T14	1		T25	11		T36	1
valid_sources[0x32]	626	1			T25	11		T26	16		T40	1
valid_sources[0x33]	755	1			T11	3		T25	11		T26	11
valid_sources[0x34]	859	1			T6	1		T25	7		T36	1
valid_sources[0x35]	523	1			T4	3		T6	2		T25	10
valid_sources[0x36]	564	1			T6	1		T49	1		T25	16
valid_sources[0x37]	1012	1			T6	1		T25	5		T39	1
valid_sources[0x38]	504	1			T14	1		T25	18		T39	1
valid_sources[0x39]	657	1			T11	5		T25	8		T26	12
valid_sources[0x3a]	535	1			T11	2		T25	14		T26	5
valid_sources[0x3b]	643	1			T6	2		T49	1		T25	13
valid_sources[0x3c]	856	1			T49	1		T25	5		T35	1
valid_sources[0x3d]	627	1			T6	2		T49	1		T25	5
valid_sources[0x3e]	609	1			T11	1		T25	7		T26	10
valid_sources[0x3f]	563	1			T14	2		T49	1		T25	10
valid_sources[0x40]	827	1			T25	12		T36	1		T26	20
valid_sources[0x41]	549	1			T11	1		T25	9		T26	27
valid_sources[0x42]	554	1			T25	9		T23	11		T26	7
valid_sources[0x43]	659	1			T11	3		T6	1		T141	1
valid_sources[0x44]	487	1			T25	5		T26	16		T142	1
valid_sources[0x45]	774	1			T6	1		T25	7		T26	20
valid_sources[0x46]	751	1			T25	16		T26	3		T143	2
valid_sources[0x47]	671	1			T11	1		T25	7		T26	3
valid_sources[0x48]	499	1			T6	1		T16	2		T25	3
valid_sources[0x49]	551	1			T8	40		T25	6		T26	16
valid_sources[0x4a]	1122	1			T25	12		T7	2		T128	1
valid_sources[0x4b]	544	1			T49	1		T25	5		T26	6
valid_sources[0x4c]	506	1			T49	2		T25	8		T137	2
valid_sources[0x4d]	634	1			T25	9		T39	1		T26	6
valid_sources[0x4e]	851	1			T6	1		T25	8		T26	10
valid_sources[0x4f]	624	1			T25	2		T144	2		T71	7
valid_sources[0x50]	459	1			T49	1		T141	1		T25	6
valid_sources[0x51]	653	1			T25	8		T37	2		T26	35
valid_sources[0x52]	672	1			T6	1		T29	1		T25	4
valid_sources[0x53]	574	1			T14	2		T6	1		T25	7
valid_sources[0x54]	690	1			T25	4		T26	11		T114	1
valid_sources[0x55]	513	1			T14	1		T49	1		T141	1
valid_sources[0x56]	653	1			T11	2		T25	7		T145	1
valid_sources[0x57]	609	1			T11	5		T25	11		T26	19
valid_sources[0x58]	489	1			T49	1		T25	16		T26	1
valid_sources[0x59]	621	1			T25	8		T39	1		T26	18
valid_sources[0x5a]	609	1			T25	5		T26	35		T50	3
valid_sources[0x5b]	585	1			T141	1		T25	12		T26	1
valid_sources[0x5c]	798	1			T25	8		T7	4		T41	18
valid_sources[0x5d]	677	1			T11	1		T14	1		T6	1
valid_sources[0x5e]	620	1			T6	3		T25	8		T94	1
valid_sources[0x5f]	850	1			T12	1		T14	1		T49	1
valid_sources[0x60]	717	1			T25	4		T35	1		T26	10
valid_sources[0x61]	682	1			T25	9		T26	2		T41	8
valid_sources[0x62]	512	1			T25	5		T36	1		T26	11
valid_sources[0x63]	1605	1			T2	2		T14	1		T25	5
valid_sources[0x64]	495	1			T4	1		T25	10		T26	2
valid_sources[0x65]	613	1			T25	3		T26	32		T41	8
valid_sources[0x66]	529	1			T14	1		T25	6		T26	43
valid_sources[0x67]	938	1			T25	10		T36	2		T26	3
valid_sources[0x68]	713	1			T146	1		T25	4		T26	18
valid_sources[0x69]	585	1			T14	1		T141	1		T25	3
valid_sources[0x6a]	1105	1			T141	1		T25	7		T26	38
valid_sources[0x6b]	627	1			T25	4		T26	23		T27	37
valid_sources[0x6c]	687	1			T11	1		T25	6		T138	1
valid_sources[0x6d]	784	1			T12	1		T6	1		T49	1
valid_sources[0x6e]	669	1			T49	3		T25	8		T26	21
valid_sources[0x6f]	768	1			T14	1		T6	1		T25	12
valid_sources[0x70]	878	1			T6	1		T25	9		T26	36
valid_sources[0x71]	523	1			T25	8		T147	1		T26	8
valid_sources[0x72]	577	1			T6	1		T25	6		T26	8
valid_sources[0x73]	744	1			T11	1		T25	8		T26	3
valid_sources[0x74]	793	1			T14	1		T49	2		T25	8
valid_sources[0x75]	1136	1			T25	13		T34	1		T26	24
valid_sources[0x76]	880	1			T25	6		T20	1		T26	14
valid_sources[0x77]	531	1			T6	1		T49	1		T25	3
valid_sources[0x78]	658	1			T25	3		T35	1		T26	20
valid_sources[0x79]	927	1			T14	1		T25	15		T137	2
valid_sources[0x7a]	1027	1			T25	3		T36	1		T26	10
valid_sources[0x7b]	644	1			T25	10		T20	1		T26	17
valid_sources[0x7c]	489	1			T49	3		T25	3		T26	16
valid_sources[0x7d]	621	1			T14	1		T25	6		T26	4
valid_sources[0x7e]	619	1			T15	1		T25	4		T26	45
valid_sources[0x7f]	913	1			T141	1		T25	6		T62	2
valid_sources[0x80]	597	1			T14	1		T25	7		T39	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38656

1

T5

21

T11

6

T14

9

values[0x0]

all_enables

biggest_size

52070

1

T1

1

T2

1

T5

9

values[0x1]

all_enables

biggest_size

50506

1

T1

1

T3

1

T5

4