Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16327348

1

T1

160495

T2

119408

T4

262793

full_word

151297290

1

T1

35798

T2

26355

T3

1125

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	167624318	1			T1	196293		T2	145763		T3	1125
auto[TlIntgErrCmd]	90	1			T100	4		T101	4		T102	4
auto[TlIntgErrData]	114	1			T100	3		T101	5		T102	2
auto[TlIntgErrBoth]	116	1			T100	3		T101	11		T102	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81079268

1

T1

98240

T2

72965

T3

536

auto[1]

86545370

1

T1

98053

T2

72798

T3

589

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8012828	1			T1	80440		T2	59674		T4	131441
auto[TlIntgErrNone]	partial	auto[1]	8314233	1			T1	80055		T2	59734		T4	131352
auto[TlIntgErrNone]	full_word	auto[0]	73066307	1			T1	17800		T2	13291		T3	536
auto[TlIntgErrNone]	full_word	auto[1]	78230950	1			T1	17998		T2	13064		T3	589
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T100	1		T101	1		T102	2
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T100	3		T101	2		T102	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T119	1		T120	1		T126	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T101	1		T117	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T100	2		T101	1		T102	2
auto[TlIntgErrData]	partial	auto[1]	58	1			T100	1		T101	3		T121	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T120	2		T122	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T101	1		T121	1		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T101	5		T102	2		T121	4
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T100	3		T101	5		T102	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T121	1		T123	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T101	1		T119	1		T117	2