| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 66.67 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.scr_key_rotated.success | 0.00 | 1 | 100 | 1 | 64 | 64 |
| mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.exec.en | 100.00 | 1 | 100 | 1 | 64 | 64 |
| mubi4_cov_of_mubi4_cov_of_tb.dut.u_hw_debug_en_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 0.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 6 | 0 | 0.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 6 | 0 | 0.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 0 | 6 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 0 | 6 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 6 | 0 | 0.00 |
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| others[0] | 0 | 1 | 1 | |
| others[1] | 0 | 1 | 1 | |
| others[2] | 0 | 1 | 1 | |
| others[3] | 0 | 1 | 1 | |
| false | 0 | 1 | 1 | |
| true | 0 | 1 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 96 | 1 | T11 | 1 | T14 | 2 | T23 | 2 | ||||
| others[1] | 124 | 1 | T11 | 1 | T14 | 1 | T49 | 2 | ||||
| others[2] | 98 | 1 | T23 | 1 | T128 | 2 | T113 | 1 | ||||
| others[3] | 169 | 1 | T11 | 2 | T17 | 3 | T49 | 1 | ||||
| false | 901 | 1 | T11 | 5 | T14 | 6 | T17 | 4 | ||||
| true | 928 | 1 | T11 | 5 | T14 | 8 | T17 | 5 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 85 | 1 | T14 | 2 | T17 | 1 | T23 | 1 | ||||
| others[1] | 664 | 1 | T11 | 3 | T14 | 2 | T17 | 4 | ||||
| others[2] | 5402 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
| others[3] | 165 | 1 | T11 | 2 | T14 | 2 | T49 | 4 | ||||
| false | 31 | 1 | T129 | 1 | T113 | 1 | T130 | 2 | ||||
| true | 40 | 1 | T17 | 1 | T23 | 1 | T50 | 1 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |