Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	915603	1			T2	9023		T4	37468		T12	35795
auto[1]	12225665	1			T1	10246		T2	9543		T3	535
auto[2]	688521	1			T2	9101		T4	26739		T12	31028
auto[3]	11939340	1			T1	10284		T2	10006		T3	588

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15593671	1			T1	306		T2	752		T3	1123
auto[1]	2444995	1			T1	2342		T2	4102		T4	16824
auto[2]	2468414	1			T1	2423		T2	5394		T4	13999
auto[3]	5262049	1			T1	15459		T2	27425		T4	84031

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11287851

1

T1

7

T3

1123

T4

6

auto[1]

14481278

1

T1

20523

T2

37673

T4

117533

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	372566	1			T14	3188		T17	806		T61	3
auto[0]	auto[0]	auto[1]	38407	1			T14	311		T17	84		T35	713
auto[0]	auto[0]	auto[2]	38489	1			T14	313		T17	86		T35	695
auto[0]	auto[0]	auto[3]	57545	1			T4	1		T12	5		T14	26
auto[0]	auto[1]	auto[0]	3816081	1			T3	535		T5	457		T9	327
auto[0]	auto[1]	auto[1]	410057	1			T5	51		T11	74		T12	1
auto[0]	auto[1]	auto[2]	442326	1			T5	40		T11	28		T14	28
auto[0]	auto[1]	auto[3]	637411	1			T1	4		T4	2		T5	1
auto[0]	auto[2]	auto[0]	273614	1			T14	1700		T17	435		T61	3
auto[0]	auto[2]	auto[1]	31971	1			T4	1		T14	148		T17	45
auto[0]	auto[2]	auto[2]	24989	1			T14	160		T17	80		T35	449
auto[0]	auto[2]	auto[3]	40103	1			T12	3		T14	13		T17	7
auto[0]	auto[3]	auto[0]	3664278	1			T3	588		T5	497		T9	311
auto[0]	auto[3]	auto[1]	420358	1			T1	1		T5	71		T11	20
auto[0]	auto[3]	auto[2]	435734	1			T1	1		T5	57		T11	62
auto[0]	auto[3]	auto[3]	583922	1			T1	1		T4	2		T5	4
auto[1]	auto[0]	auto[0]	13429	1			T2	302		T4	1244		T12	1213
auto[1]	auto[0]	auto[1]	61218	1			T2	1432		T4	5582		T12	5278
auto[1]	auto[0]	auto[2]	61112	1			T2	1328		T4	5519		T12	5410
auto[1]	auto[0]	auto[3]	272837	1			T2	5961		T4	25122		T12	23889
auto[1]	auto[1]	auto[0]	3720782	1			T1	159		T2	202		T4	185
auto[1]	auto[1]	auto[1]	730746	1			T1	1707		T2	1513		T4	5642
auto[1]	auto[1]	auto[2]	703801	1			T1	647		T2	820		T4	952
auto[1]	auto[1]	auto[3]	1764461	1			T1	7729		T2	7008		T4	25055
auto[1]	auto[2]	auto[0]	12335	1			T2	188		T4	1120		T12	1109
auto[1]	auto[2]	auto[1]	54781	1			T2	836		T4	5067		T12	5030
auto[1]	auto[2]	auto[2]	45940	1			T2	1494		T4	3778		T12	4510
auto[1]	auto[2]	auto[3]	204788	1			T2	6583		T4	16773		T12	20376
auto[1]	auto[3]	auto[0]	3720586	1			T1	147		T2	60		T4	136
auto[1]	auto[3]	auto[1]	697457	1			T1	634		T2	321		T4	532
auto[1]	auto[3]	auto[2]	716023	1			T1	1775		T2	1752		T4	3750
auto[1]	auto[3]	auto[3]	1700982	1			T1	7725		T2	7873		T4	17076