Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1148548316	130889	0	0
ctrl_regwen_rd_A	1148548316	9044	0	0
exec_rd_A	1148548316	8373	0	0
exec_regwen_rd_A	1148548316	9058	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148548316	130889	0	0
T7	845039	0	0	0
T23	441877	0	0	0
T25	45265	1802	0	0
T26	0	4793	0	0
T27	0	706	0	0
T33	686917	0	0	0
T34	151306	0	0	0
T35	159188	0	0	0
T36	114921	0	0	0
T37	102920	0	0	0
T38	252823	0	0	0
T41	0	1306	0	0
T42	0	610	0	0
T43	0	1538	0	0
T44	0	682	0	0
T45	0	821	0	0
T46	0	2262	0	0
T47	0	5977	0	0
T48	54637	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148548316	9044	0	0
T27	20364	78	0	0
T43	0	264	0	0
T45	0	86	0	0
T46	0	445	0	0
T71	139886	0	0	0
T72	371713	0	0	0
T73	933165	0	0	0
T103	0	283	0	0
T104	0	682	0	0
T105	0	301	0	0
T106	0	231	0	0
T107	0	327	0	0
T108	0	689	0	0
T109	127969	0	0	0
T110	74325	0	0	0
T111	84191	0	0	0
T112	416341	0	0	0
T113	982333	0	0	0
T114	151788	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148548316	8373	0	0
T27	20364	77	0	0
T43	0	218	0	0
T45	0	53	0	0
T46	0	371	0	0
T71	139886	0	0	0
T72	371713	0	0	0
T73	933165	0	0	0
T103	0	248	0	0
T104	0	615	0	0
T105	0	243	0	0
T106	0	145	0	0
T107	0	321	0	0
T108	0	675	0	0
T109	127969	0	0	0
T110	74325	0	0	0
T111	84191	0	0	0
T112	416341	0	0	0
T113	982333	0	0	0
T114	151788	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148548316	9058	0	0
T27	20364	51	0	0
T43	0	220	0	0
T45	0	62	0	0
T46	0	418	0	0
T71	139886	0	0	0
T72	371713	0	0	0
T73	933165	0	0	0
T103	0	324	0	0
T104	0	679	0	0
T105	0	271	0	0
T106	0	176	0	0
T107	0	280	0	0
T108	0	768	0	0
T109	127969	0	0	0
T110	74325	0	0	0
T111	84191	0	0	0
T112	416341	0	0	0
T113	982333	0	0	0
T114	151788	0	0	0