| T793 |
/workspace/coverage/default/42.sram_ctrl_partial_access.2824543996 |
|
|
Apr 25 02:25:43 PM PDT 24 |
Apr 25 02:25:51 PM PDT 24 |
424235728 ps |
| T794 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.321706730 |
|
|
Apr 25 02:18:42 PM PDT 24 |
Apr 25 02:18:58 PM PDT 24 |
1523923469 ps |
| T795 |
/workspace/coverage/default/4.sram_ctrl_bijection.2032822218 |
|
|
Apr 25 02:16:34 PM PDT 24 |
Apr 25 02:48:02 PM PDT 24 |
460111338282 ps |
| T796 |
/workspace/coverage/default/3.sram_ctrl_executable.1947026077 |
|
|
Apr 25 02:16:22 PM PDT 24 |
Apr 25 02:18:48 PM PDT 24 |
10639744220 ps |
| T797 |
/workspace/coverage/default/24.sram_ctrl_alert_test.66998784 |
|
|
Apr 25 02:20:55 PM PDT 24 |
Apr 25 02:20:56 PM PDT 24 |
46538913 ps |
| T798 |
/workspace/coverage/default/48.sram_ctrl_smoke.4057242849 |
|
|
Apr 25 02:27:26 PM PDT 24 |
Apr 25 02:27:46 PM PDT 24 |
1457777558 ps |
| T799 |
/workspace/coverage/default/15.sram_ctrl_partial_access.1315494194 |
|
|
Apr 25 02:18:20 PM PDT 24 |
Apr 25 02:18:48 PM PDT 24 |
10395827745 ps |
| T800 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.1018578644 |
|
|
Apr 25 02:21:38 PM PDT 24 |
Apr 25 02:21:42 PM PDT 24 |
707362425 ps |
| T801 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.985063425 |
|
|
Apr 25 02:22:40 PM PDT 24 |
Apr 25 02:22:47 PM PDT 24 |
931481744 ps |
| T802 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3988387458 |
|
|
Apr 25 02:17:36 PM PDT 24 |
Apr 25 02:18:36 PM PDT 24 |
4757668333 ps |
| T803 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2659109109 |
|
|
Apr 25 02:24:38 PM PDT 24 |
Apr 25 02:24:46 PM PDT 24 |
3063932572 ps |
| T804 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3479821205 |
|
|
Apr 25 02:19:22 PM PDT 24 |
Apr 25 02:21:00 PM PDT 24 |
1693822849 ps |
| T805 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.3059729840 |
|
|
Apr 25 02:21:52 PM PDT 24 |
Apr 25 02:21:56 PM PDT 24 |
1395825292 ps |
| T806 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.4108273052 |
|
|
Apr 25 02:19:50 PM PDT 24 |
Apr 25 02:23:19 PM PDT 24 |
17017853246 ps |
| T807 |
/workspace/coverage/default/7.sram_ctrl_bijection.1049809214 |
|
|
Apr 25 02:17:00 PM PDT 24 |
Apr 25 02:35:56 PM PDT 24 |
103716854910 ps |
| T808 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.3892664143 |
|
|
Apr 25 02:18:28 PM PDT 24 |
Apr 25 02:19:28 PM PDT 24 |
10122491947 ps |
| T809 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.1911184694 |
|
|
Apr 25 02:23:49 PM PDT 24 |
Apr 25 02:25:04 PM PDT 24 |
2339507616 ps |
| T810 |
/workspace/coverage/default/7.sram_ctrl_regwen.2300327808 |
|
|
Apr 25 02:17:06 PM PDT 24 |
Apr 25 02:26:42 PM PDT 24 |
4519161994 ps |
| T811 |
/workspace/coverage/default/35.sram_ctrl_stress_all.952470779 |
|
|
Apr 25 02:23:33 PM PDT 24 |
Apr 25 04:22:53 PM PDT 24 |
832946514941 ps |
| T812 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.3870200063 |
|
|
Apr 25 02:16:39 PM PDT 24 |
Apr 25 02:16:49 PM PDT 24 |
3395559561 ps |
| T813 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.2474028362 |
|
|
Apr 25 02:24:32 PM PDT 24 |
Apr 25 02:28:09 PM PDT 24 |
13943265109 ps |
| T814 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.4043440875 |
|
|
Apr 25 02:18:07 PM PDT 24 |
Apr 25 02:19:21 PM PDT 24 |
2576224439 ps |
| T815 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.55359441 |
|
|
Apr 25 02:20:17 PM PDT 24 |
Apr 25 02:20:36 PM PDT 24 |
2906095241 ps |
| T816 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.1511574944 |
|
|
Apr 25 02:23:49 PM PDT 24 |
Apr 25 02:41:36 PM PDT 24 |
43307762787 ps |
| T817 |
/workspace/coverage/default/33.sram_ctrl_partial_access.2792878282 |
|
|
Apr 25 02:22:59 PM PDT 24 |
Apr 25 02:23:18 PM PDT 24 |
8533638027 ps |
| T818 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1377363423 |
|
|
Apr 25 02:23:13 PM PDT 24 |
Apr 25 02:24:00 PM PDT 24 |
6982565537 ps |
| T819 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.3793550067 |
|
|
Apr 25 02:16:32 PM PDT 24 |
Apr 25 02:18:24 PM PDT 24 |
18231272800 ps |
| T820 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3170841563 |
|
|
Apr 25 02:28:07 PM PDT 24 |
Apr 25 02:34:56 PM PDT 24 |
40421233120 ps |
| T821 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.362902974 |
|
|
Apr 25 02:21:05 PM PDT 24 |
Apr 25 02:21:25 PM PDT 24 |
727012644 ps |
| T822 |
/workspace/coverage/default/10.sram_ctrl_bijection.1855802131 |
|
|
Apr 25 02:17:28 PM PDT 24 |
Apr 25 02:42:55 PM PDT 24 |
717290407085 ps |
| T823 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.516425168 |
|
|
Apr 25 02:21:23 PM PDT 24 |
Apr 25 02:23:48 PM PDT 24 |
8736402771 ps |
| T824 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.460414057 |
|
|
Apr 25 02:18:27 PM PDT 24 |
Apr 25 02:20:30 PM PDT 24 |
8232103495 ps |
| T825 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.2446754437 |
|
|
Apr 25 02:21:25 PM PDT 24 |
Apr 25 02:21:30 PM PDT 24 |
1409756239 ps |
| T826 |
/workspace/coverage/default/2.sram_ctrl_alert_test.174871532 |
|
|
Apr 25 02:16:22 PM PDT 24 |
Apr 25 02:16:24 PM PDT 24 |
45566507 ps |
| T827 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.29824038 |
|
|
Apr 25 02:17:52 PM PDT 24 |
Apr 25 02:23:35 PM PDT 24 |
5061022119 ps |
| T828 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.453036431 |
|
|
Apr 25 02:22:44 PM PDT 24 |
Apr 25 02:23:11 PM PDT 24 |
16044085172 ps |
| T829 |
/workspace/coverage/default/44.sram_ctrl_alert_test.265426207 |
|
|
Apr 25 02:26:30 PM PDT 24 |
Apr 25 02:26:31 PM PDT 24 |
26625671 ps |
| T830 |
/workspace/coverage/default/40.sram_ctrl_executable.1233923013 |
|
|
Apr 25 02:25:01 PM PDT 24 |
Apr 25 02:34:13 PM PDT 24 |
13265399312 ps |
| T831 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1738336735 |
|
|
Apr 25 02:16:59 PM PDT 24 |
Apr 25 02:19:42 PM PDT 24 |
10003918642 ps |
| T832 |
/workspace/coverage/default/5.sram_ctrl_regwen.3083456821 |
|
|
Apr 25 02:16:44 PM PDT 24 |
Apr 25 02:25:22 PM PDT 24 |
25644702490 ps |
| T833 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1592646685 |
|
|
Apr 25 02:25:29 PM PDT 24 |
Apr 25 02:25:50 PM PDT 24 |
2839876938 ps |
| T834 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.416501736 |
|
|
Apr 25 02:20:40 PM PDT 24 |
Apr 25 02:22:42 PM PDT 24 |
2276271436 ps |
| T835 |
/workspace/coverage/default/18.sram_ctrl_regwen.459216066 |
|
|
Apr 25 02:19:06 PM PDT 24 |
Apr 25 02:36:08 PM PDT 24 |
3955020319 ps |
| T836 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.705325635 |
|
|
Apr 25 02:23:26 PM PDT 24 |
Apr 25 02:25:20 PM PDT 24 |
4136325778 ps |
| T837 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.939633374 |
|
|
Apr 25 02:21:08 PM PDT 24 |
Apr 25 02:22:26 PM PDT 24 |
2669029451 ps |
| T838 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.917373929 |
|
|
Apr 25 02:17:15 PM PDT 24 |
Apr 25 02:22:04 PM PDT 24 |
4355206827 ps |
| T839 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3669249580 |
|
|
Apr 25 02:27:36 PM PDT 24 |
Apr 25 02:28:14 PM PDT 24 |
2786062610 ps |
| T840 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1553748245 |
|
|
Apr 25 02:17:15 PM PDT 24 |
Apr 25 02:18:50 PM PDT 24 |
23730637493 ps |
| T841 |
/workspace/coverage/default/47.sram_ctrl_regwen.1243455195 |
|
|
Apr 25 02:27:22 PM PDT 24 |
Apr 25 02:31:09 PM PDT 24 |
8237670677 ps |
| T842 |
/workspace/coverage/default/35.sram_ctrl_regwen.1459000961 |
|
|
Apr 25 02:23:26 PM PDT 24 |
Apr 25 02:30:51 PM PDT 24 |
8111106818 ps |
| T843 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2307374383 |
|
|
Apr 25 02:27:30 PM PDT 24 |
Apr 25 02:28:25 PM PDT 24 |
36496280433 ps |
| T844 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1096353535 |
|
|
Apr 25 02:18:21 PM PDT 24 |
Apr 25 02:23:40 PM PDT 24 |
4681173245 ps |
| T845 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1392056114 |
|
|
Apr 25 02:22:37 PM PDT 24 |
Apr 25 02:23:54 PM PDT 24 |
2511118916 ps |
| T846 |
/workspace/coverage/default/17.sram_ctrl_stress_all.2200252945 |
|
|
Apr 25 02:19:01 PM PDT 24 |
Apr 25 04:33:39 PM PDT 24 |
588948999193 ps |
| T847 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2517511671 |
|
|
Apr 25 02:25:25 PM PDT 24 |
Apr 25 02:25:39 PM PDT 24 |
721369350 ps |
| T848 |
/workspace/coverage/default/41.sram_ctrl_partial_access.1914547846 |
|
|
Apr 25 02:25:24 PM PDT 24 |
Apr 25 02:26:54 PM PDT 24 |
3345254405 ps |
| T849 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.3036808477 |
|
|
Apr 25 02:18:57 PM PDT 24 |
Apr 25 02:21:30 PM PDT 24 |
40587673532 ps |
| T850 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3497146892 |
|
|
Apr 25 02:16:07 PM PDT 24 |
Apr 25 02:20:36 PM PDT 24 |
17424804090 ps |
| T851 |
/workspace/coverage/default/1.sram_ctrl_stress_all.2109863561 |
|
|
Apr 25 02:16:15 PM PDT 24 |
Apr 25 03:08:15 PM PDT 24 |
52161168933 ps |
| T852 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2015225360 |
|
|
Apr 25 02:18:58 PM PDT 24 |
Apr 25 02:21:00 PM PDT 24 |
6211418714 ps |
| T853 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.2125878175 |
|
|
Apr 25 02:27:46 PM PDT 24 |
Apr 25 02:30:15 PM PDT 24 |
6898258655 ps |
| T854 |
/workspace/coverage/default/35.sram_ctrl_executable.4032742365 |
|
|
Apr 25 02:23:26 PM PDT 24 |
Apr 25 02:41:38 PM PDT 24 |
45555017564 ps |
| T855 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.2801647190 |
|
|
Apr 25 02:24:39 PM PDT 24 |
Apr 25 02:25:21 PM PDT 24 |
1521214435 ps |
| T856 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2506955450 |
|
|
Apr 25 02:19:37 PM PDT 24 |
Apr 25 02:20:42 PM PDT 24 |
4167512202 ps |
| T857 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.442738512 |
|
|
Apr 25 02:22:32 PM PDT 24 |
Apr 25 02:27:20 PM PDT 24 |
29967961712 ps |
| T858 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1146428014 |
|
|
Apr 25 02:23:48 PM PDT 24 |
Apr 25 02:23:50 PM PDT 24 |
12654432 ps |
| T859 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.1058555191 |
|
|
Apr 25 02:16:14 PM PDT 24 |
Apr 25 02:18:02 PM PDT 24 |
3180843213 ps |
| T860 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2428561327 |
|
|
Apr 25 02:24:38 PM PDT 24 |
Apr 25 02:42:55 PM PDT 24 |
62537184660 ps |
| T861 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.4092910860 |
|
|
Apr 25 02:24:24 PM PDT 24 |
Apr 25 02:25:41 PM PDT 24 |
9758271925 ps |
| T862 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.4292803059 |
|
|
Apr 25 02:25:30 PM PDT 24 |
Apr 25 02:25:34 PM PDT 24 |
359406516 ps |
| T863 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.348184211 |
|
|
Apr 25 02:23:31 PM PDT 24 |
Apr 25 02:25:32 PM PDT 24 |
26008428642 ps |
| T864 |
/workspace/coverage/default/38.sram_ctrl_partial_access.69578759 |
|
|
Apr 25 02:24:13 PM PDT 24 |
Apr 25 02:25:03 PM PDT 24 |
3171680794 ps |
| T865 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3544739193 |
|
|
Apr 25 02:19:37 PM PDT 24 |
Apr 25 02:25:28 PM PDT 24 |
23925201849 ps |
| T866 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2947968619 |
|
|
Apr 25 02:18:13 PM PDT 24 |
Apr 25 02:18:48 PM PDT 24 |
1447756812 ps |
| T867 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.420166952 |
|
|
Apr 25 02:17:52 PM PDT 24 |
Apr 25 02:25:14 PM PDT 24 |
7979777673 ps |
| T868 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.1900568976 |
|
|
Apr 25 02:24:51 PM PDT 24 |
Apr 25 02:49:20 PM PDT 24 |
96732327237 ps |
| T869 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.3318934110 |
|
|
Apr 25 02:16:50 PM PDT 24 |
Apr 25 02:17:23 PM PDT 24 |
819953693 ps |
| T870 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.285140043 |
|
|
Apr 25 02:22:31 PM PDT 24 |
Apr 25 02:27:26 PM PDT 24 |
6560746034 ps |
| T871 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.3263996228 |
|
|
Apr 25 02:25:01 PM PDT 24 |
Apr 25 02:25:19 PM PDT 24 |
5292337733 ps |
| T872 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.811222973 |
|
|
Apr 25 02:21:38 PM PDT 24 |
Apr 25 02:26:54 PM PDT 24 |
82739135129 ps |
| T873 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.3058416481 |
|
|
Apr 25 02:19:37 PM PDT 24 |
Apr 25 02:20:03 PM PDT 24 |
6269637928 ps |
| T874 |
/workspace/coverage/default/0.sram_ctrl_alert_test.832756044 |
|
|
Apr 25 02:16:02 PM PDT 24 |
Apr 25 02:16:04 PM PDT 24 |
43211614 ps |
| T875 |
/workspace/coverage/default/5.sram_ctrl_alert_test.3214641522 |
|
|
Apr 25 02:16:44 PM PDT 24 |
Apr 25 02:16:45 PM PDT 24 |
113736792 ps |
| T876 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3108166165 |
|
|
Apr 25 02:21:18 PM PDT 24 |
Apr 25 02:22:20 PM PDT 24 |
775649144 ps |
| T877 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.819303186 |
|
|
Apr 25 02:18:34 PM PDT 24 |
Apr 25 02:19:34 PM PDT 24 |
3041783394 ps |
| T878 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.718901564 |
|
|
Apr 25 02:22:38 PM PDT 24 |
Apr 25 02:22:53 PM PDT 24 |
608538101 ps |
| T879 |
/workspace/coverage/default/40.sram_ctrl_smoke.3270698972 |
|
|
Apr 25 02:24:49 PM PDT 24 |
Apr 25 02:25:01 PM PDT 24 |
3824508933 ps |
| T880 |
/workspace/coverage/default/46.sram_ctrl_smoke.4205253179 |
|
|
Apr 25 02:26:50 PM PDT 24 |
Apr 25 02:26:57 PM PDT 24 |
1699520997 ps |
| T881 |
/workspace/coverage/default/30.sram_ctrl_alert_test.1820443371 |
|
|
Apr 25 02:22:26 PM PDT 24 |
Apr 25 02:22:27 PM PDT 24 |
17760868 ps |
| T882 |
/workspace/coverage/default/5.sram_ctrl_smoke.3879851705 |
|
|
Apr 25 02:16:36 PM PDT 24 |
Apr 25 02:18:02 PM PDT 24 |
1552635333 ps |
| T883 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2668328915 |
|
|
Apr 25 02:21:42 PM PDT 24 |
Apr 25 02:22:58 PM PDT 24 |
2782115381 ps |
| T884 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.3966384306 |
|
|
Apr 25 02:21:02 PM PDT 24 |
Apr 25 02:32:00 PM PDT 24 |
105558616342 ps |
| T885 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.3818017444 |
|
|
Apr 25 02:20:11 PM PDT 24 |
Apr 25 02:22:24 PM PDT 24 |
4032547711 ps |
| T886 |
/workspace/coverage/default/26.sram_ctrl_bijection.2664407348 |
|
|
Apr 25 02:21:18 PM PDT 24 |
Apr 25 02:49:02 PM PDT 24 |
351154163030 ps |
| T887 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.1043983468 |
|
|
Apr 25 02:20:18 PM PDT 24 |
Apr 25 02:21:35 PM PDT 24 |
25400253155 ps |
| T888 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2122950511 |
|
|
Apr 25 02:26:55 PM PDT 24 |
Apr 25 02:33:40 PM PDT 24 |
27626562296 ps |
| T889 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3706144497 |
|
|
Apr 25 02:27:26 PM PDT 24 |
Apr 25 02:30:29 PM PDT 24 |
8673468280 ps |
| T890 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.3431899442 |
|
|
Apr 25 02:16:13 PM PDT 24 |
Apr 25 02:16:16 PM PDT 24 |
2600176638 ps |
| T891 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.340590232 |
|
|
Apr 25 02:22:00 PM PDT 24 |
Apr 25 02:25:19 PM PDT 24 |
2387669077 ps |
| T892 |
/workspace/coverage/default/1.sram_ctrl_smoke.782725729 |
|
|
Apr 25 02:16:07 PM PDT 24 |
Apr 25 02:16:19 PM PDT 24 |
3453345344 ps |
| T893 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.3964910210 |
|
|
Apr 25 02:20:19 PM PDT 24 |
Apr 25 02:25:36 PM PDT 24 |
11050790606 ps |
| T894 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1051504544 |
|
|
Apr 25 02:26:31 PM PDT 24 |
Apr 25 02:27:22 PM PDT 24 |
8912030546 ps |
| T895 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2362319981 |
|
|
Apr 25 02:27:24 PM PDT 24 |
Apr 25 02:37:55 PM PDT 24 |
14831070867 ps |
| T896 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.1480156274 |
|
|
Apr 25 02:22:59 PM PDT 24 |
Apr 25 02:45:41 PM PDT 24 |
102410378217 ps |
| T897 |
/workspace/coverage/default/13.sram_ctrl_partial_access.3671827055 |
|
|
Apr 25 02:18:06 PM PDT 24 |
Apr 25 02:18:12 PM PDT 24 |
457618896 ps |
| T898 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.854045861 |
|
|
Apr 25 02:21:52 PM PDT 24 |
Apr 25 02:24:17 PM PDT 24 |
98566014629 ps |
| T899 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.903006134 |
|
|
Apr 25 02:18:44 PM PDT 24 |
Apr 25 02:18:49 PM PDT 24 |
357572052 ps |
| T900 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2509884632 |
|
|
Apr 25 02:19:37 PM PDT 24 |
Apr 25 02:25:37 PM PDT 24 |
6685197107 ps |
| T901 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.3823711930 |
|
|
Apr 25 02:20:49 PM PDT 24 |
Apr 25 02:20:53 PM PDT 24 |
3368948250 ps |
| T902 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3924161806 |
|
|
Apr 25 02:27:41 PM PDT 24 |
Apr 25 02:46:33 PM PDT 24 |
174546614911 ps |
| T903 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2193249725 |
|
|
Apr 25 02:26:48 PM PDT 24 |
Apr 25 02:26:49 PM PDT 24 |
15389000 ps |
| T904 |
/workspace/coverage/default/41.sram_ctrl_stress_all.913618067 |
|
|
Apr 25 02:25:28 PM PDT 24 |
Apr 25 04:13:20 PM PDT 24 |
932872290576 ps |
| T905 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2940392531 |
|
|
Apr 25 02:16:45 PM PDT 24 |
Apr 25 02:20:27 PM PDT 24 |
20223815429 ps |
| T906 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.315368386 |
|
|
Apr 25 02:26:41 PM PDT 24 |
Apr 25 02:27:52 PM PDT 24 |
3762259701 ps |
| T907 |
/workspace/coverage/default/31.sram_ctrl_executable.357854368 |
|
|
Apr 25 02:22:32 PM PDT 24 |
Apr 25 02:39:59 PM PDT 24 |
26786992382 ps |
| T908 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.2173138863 |
|
|
Apr 25 02:24:24 PM PDT 24 |
Apr 25 02:26:51 PM PDT 24 |
24883151031 ps |
| T909 |
/workspace/coverage/default/23.sram_ctrl_bijection.1541997680 |
|
|
Apr 25 02:20:17 PM PDT 24 |
Apr 25 02:49:29 PM PDT 24 |
359182858368 ps |
| T910 |
/workspace/coverage/default/7.sram_ctrl_executable.3630224190 |
|
|
Apr 25 02:17:07 PM PDT 24 |
Apr 25 02:23:50 PM PDT 24 |
9047214468 ps |
| T911 |
/workspace/coverage/default/8.sram_ctrl_partial_access.1128667616 |
|
|
Apr 25 02:17:15 PM PDT 24 |
Apr 25 02:17:31 PM PDT 24 |
1486178187 ps |
| T912 |
/workspace/coverage/default/32.sram_ctrl_partial_access.699522955 |
|
|
Apr 25 02:22:44 PM PDT 24 |
Apr 25 02:23:01 PM PDT 24 |
1704647641 ps |
| T913 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.2424483868 |
|
|
Apr 25 02:23:48 PM PDT 24 |
Apr 25 02:23:52 PM PDT 24 |
2396342452 ps |
| T914 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3638170116 |
|
|
Apr 25 02:17:52 PM PDT 24 |
Apr 25 02:18:28 PM PDT 24 |
8290173090 ps |
| T915 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.1476557055 |
|
|
Apr 25 02:17:24 PM PDT 24 |
Apr 25 02:22:34 PM PDT 24 |
25200276486 ps |
| T916 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.3205420993 |
|
|
Apr 25 02:17:06 PM PDT 24 |
Apr 25 02:21:45 PM PDT 24 |
14192703318 ps |
| T917 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2210570049 |
|
|
Apr 25 02:16:13 PM PDT 24 |
Apr 25 02:17:00 PM PDT 24 |
819559418 ps |
| T918 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.4128597046 |
|
|
Apr 25 02:17:22 PM PDT 24 |
Apr 25 02:23:12 PM PDT 24 |
10355058697 ps |
| T919 |
/workspace/coverage/default/7.sram_ctrl_partial_access.1368193254 |
|
|
Apr 25 02:17:00 PM PDT 24 |
Apr 25 02:17:25 PM PDT 24 |
4065445828 ps |
| T920 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.3421970617 |
|
|
Apr 25 02:23:26 PM PDT 24 |
Apr 25 02:24:10 PM PDT 24 |
728397474 ps |
| T921 |
/workspace/coverage/default/16.sram_ctrl_partial_access.1364079128 |
|
|
Apr 25 02:18:35 PM PDT 24 |
Apr 25 02:19:45 PM PDT 24 |
4503247528 ps |
| T922 |
/workspace/coverage/default/21.sram_ctrl_partial_access.764385063 |
|
|
Apr 25 02:19:45 PM PDT 24 |
Apr 25 02:20:48 PM PDT 24 |
997080106 ps |
| T923 |
/workspace/coverage/default/20.sram_ctrl_stress_all.3824573581 |
|
|
Apr 25 02:19:46 PM PDT 24 |
Apr 25 04:13:03 PM PDT 24 |
343082434419 ps |
| T924 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.1968437990 |
|
|
Apr 25 02:20:54 PM PDT 24 |
Apr 25 02:31:52 PM PDT 24 |
3568796364 ps |
| T76 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.1859668228 |
|
|
Apr 25 02:25:46 PM PDT 24 |
Apr 25 02:27:51 PM PDT 24 |
1589731987 ps |
| T925 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.1778327003 |
|
|
Apr 25 02:20:34 PM PDT 24 |
Apr 25 02:35:17 PM PDT 24 |
4845132700 ps |
| T926 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3166360939 |
|
|
Apr 25 02:27:26 PM PDT 24 |
Apr 25 04:26:19 PM PDT 24 |
79008655640 ps |
| T927 |
/workspace/coverage/default/30.sram_ctrl_executable.3266280795 |
|
|
Apr 25 02:22:18 PM PDT 24 |
Apr 25 02:47:10 PM PDT 24 |
11726296018 ps |
| T928 |
/workspace/coverage/default/47.sram_ctrl_smoke.302421398 |
|
|
Apr 25 02:27:25 PM PDT 24 |
Apr 25 02:27:32 PM PDT 24 |
2818169243 ps |
| T929 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.538058832 |
|
|
Apr 25 02:16:44 PM PDT 24 |
Apr 25 02:22:18 PM PDT 24 |
25852695452 ps |
| T930 |
/workspace/coverage/default/20.sram_ctrl_partial_access.4108041945 |
|
|
Apr 25 02:19:36 PM PDT 24 |
Apr 25 02:20:40 PM PDT 24 |
3272904734 ps |
| T931 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2556287258 |
|
|
Apr 25 02:18:00 PM PDT 24 |
Apr 25 02:20:18 PM PDT 24 |
8898521542 ps |
| T932 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3155850152 |
|
|
Apr 25 02:16:07 PM PDT 24 |
Apr 25 02:21:03 PM PDT 24 |
8459632341 ps |
| T933 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1969891908 |
|
|
Apr 25 02:23:13 PM PDT 24 |
Apr 25 02:26:28 PM PDT 24 |
12687121290 ps |
| T934 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.1896126611 |
|
|
Apr 25 02:19:50 PM PDT 24 |
Apr 25 02:20:01 PM PDT 24 |
2709560832 ps |
| T935 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1336815223 |
|
|
Apr 25 02:18:13 PM PDT 24 |
Apr 25 02:19:24 PM PDT 24 |
12160888914 ps |
| T936 |
/workspace/coverage/default/0.sram_ctrl_stress_all.1659833216 |
|
|
Apr 25 02:15:58 PM PDT 24 |
Apr 25 02:57:54 PM PDT 24 |
566508056359 ps |
| T937 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3973375657 |
|
|
Apr 25 02:17:53 PM PDT 24 |
Apr 25 02:18:24 PM PDT 24 |
4032776169 ps |
| T938 |
/workspace/coverage/default/38.sram_ctrl_smoke.3498461824 |
|
|
Apr 25 02:24:15 PM PDT 24 |
Apr 25 02:24:27 PM PDT 24 |
810759513 ps |
| T939 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.1982050447 |
|
|
Apr 25 02:18:37 PM PDT 24 |
Apr 25 02:37:18 PM PDT 24 |
36261653426 ps |
| T940 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2662549510 |
|
|
Apr 25 02:18:11 PM PDT 24 |
Apr 25 02:18:48 PM PDT 24 |
5709161796 ps |
| T941 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3637092083 |
|
|
Apr 25 02:27:27 PM PDT 24 |
Apr 25 02:44:39 PM PDT 24 |
142933196602 ps |
| T51 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4011844535 |
|
|
Apr 25 12:49:29 PM PDT 24 |
Apr 25 12:50:22 PM PDT 24 |
7331983835 ps |
| T100 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1228158468 |
|
|
Apr 25 12:49:02 PM PDT 24 |
Apr 25 12:49:09 PM PDT 24 |
315497159 ps |
| T942 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4136262516 |
|
|
Apr 25 12:49:18 PM PDT 24 |
Apr 25 12:49:23 PM PDT 24 |
2059359263 ps |
| T96 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1955708676 |
|
|
Apr 25 12:49:09 PM PDT 24 |
Apr 25 12:49:14 PM PDT 24 |
19912654 ps |
| T97 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.611304894 |
|
|
Apr 25 12:49:02 PM PDT 24 |
Apr 25 12:49:08 PM PDT 24 |
43218984 ps |
| T101 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2357539392 |
|
|
Apr 25 12:49:20 PM PDT 24 |
Apr 25 12:49:23 PM PDT 24 |
566532384 ps |
| T52 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2079605038 |
|
|
Apr 25 12:49:03 PM PDT 24 |
Apr 25 12:49:09 PM PDT 24 |
64734380 ps |
| T98 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.472881023 |
|
|
Apr 25 12:49:23 PM PDT 24 |
Apr 25 12:49:24 PM PDT 24 |
12388969 ps |
| T99 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1946227618 |
|
|
Apr 25 12:48:59 PM PDT 24 |
Apr 25 12:49:07 PM PDT 24 |
29152792 ps |
| T53 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2208211403 |
|
|
Apr 25 12:49:14 PM PDT 24 |
Apr 25 12:49:17 PM PDT 24 |
17216278 ps |
| T54 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2557777849 |
|
|
Apr 25 12:49:04 PM PDT 24 |
Apr 25 12:49:11 PM PDT 24 |
276188977 ps |
| T55 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2687783081 |
|
|
Apr 25 12:49:10 PM PDT 24 |
Apr 25 12:49:42 PM PDT 24 |
7697720052 ps |
| T943 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3195601355 |
|
|
Apr 25 12:49:13 PM PDT 24 |
Apr 25 12:49:19 PM PDT 24 |
1360606667 ps |
| T944 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.664184870 |
|
|
Apr 25 12:49:02 PM PDT 24 |
Apr 25 12:49:11 PM PDT 24 |
793009256 ps |
| T945 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2607519787 |
|
|
Apr 25 12:49:11 PM PDT 24 |
Apr 25 12:49:18 PM PDT 24 |
34513981 ps |
| T102 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3049158838 |
|
|
Apr 25 12:49:01 PM PDT 24 |
Apr 25 12:49:08 PM PDT 24 |
224001045 ps |
| T119 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3129940806 |
|
|
Apr 25 12:49:17 PM PDT 24 |
Apr 25 12:49:20 PM PDT 24 |
77206878 ps |
| T946 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.793123381 |
|
|
Apr 25 12:49:03 PM PDT 24 |
Apr 25 12:49:11 PM PDT 24 |
379792345 ps |
| T56 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3387524325 |
|
|
Apr 25 12:49:09 PM PDT 24 |
Apr 25 12:50:01 PM PDT 24 |
14220657714 ps |
| T91 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2565866576 |
|
|
Apr 25 12:49:10 PM PDT 24 |
Apr 25 12:49:15 PM PDT 24 |
28788692 ps |
| T947 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.671654097 |
|
|
Apr 25 12:49:01 PM PDT 24 |
Apr 25 12:49:11 PM PDT 24 |
1389747291 ps |
| T948 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.696104050 |
|
|
Apr 25 12:49:29 PM PDT 24 |
Apr 25 12:49:31 PM PDT 24 |
19386599 ps |
| T121 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1776192583 |
|
|
Apr 25 12:49:10 PM PDT 24 |
Apr 25 12:49:17 PM PDT 24 |
322345673 ps |
| T57 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.434570906 |
|
|
Apr 25 12:49:15 PM PDT 24 |
Apr 25 12:49:18 PM PDT 24 |
60194580 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.560777662 |
|
|
Apr 25 12:49:10 PM PDT 24 |
Apr 25 12:49:17 PM PDT 24 |
349282466 ps |
| T58 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.365772272 |
|
|
Apr 25 12:49:12 PM PDT 24 |
Apr 25 12:49:16 PM PDT 24 |
33808192 ps |
| T59 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3027053255 |
|
|
Apr 25 12:49:10 PM PDT 24 |
Apr 25 12:49:15 PM PDT 24 |
15688397 ps |
| T950 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1816654527 |
|
|
Apr 25 12:49:02 PM PDT 24 |
Apr 25 12:49:08 PM PDT 24 |
32280677 ps |
| T951 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3605749872 |
|
|
Apr 25 12:49:09 PM PDT 24 |
Apr 25 12:49:17 PM PDT 24 |
375106482 ps |
| T952 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1587895099 |
|
|
Apr 25 12:49:06 PM PDT 24 |
Apr 25 12:49:11 PM PDT 24 |
59451521 ps |
| T953 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2138671101 |
|
|
Apr 25 12:49:06 PM PDT 24 |
Apr 25 12:49:12 PM PDT 24 |
64298396 ps |
| T117 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1972082271 |
|
|
Apr 25 12:49:07 PM PDT 24 |
Apr 25 12:49:13 PM PDT 24 |
511562783 ps |
| T954 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1419483986 |
|
|
Apr 25 12:49:00 PM PDT 24 |
Apr 25 12:49:07 PM PDT 24 |
15663682 ps |
| T92 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3251140186 |
|
|
Apr 25 12:49:14 PM PDT 24 |
Apr 25 12:49:17 PM PDT 24 |
25255693 ps |
| T118 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1728841830 |
|
|
Apr 25 12:48:55 PM PDT 24 |
Apr 25 12:49:04 PM PDT 24 |
350721399 ps |
| T60 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2940990092 |
|
|
Apr 25 12:48:50 PM PDT 24 |
Apr 25 12:48:55 PM PDT 24 |
39738910 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1100700728 |
|
|
Apr 25 12:49:02 PM PDT 24 |
Apr 25 12:49:08 PM PDT 24 |
22193215 ps |
| T63 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2815151478 |
|
|
Apr 25 12:49:17 PM PDT 24 |
Apr 25 12:49:48 PM PDT 24 |
7544181460 ps |
| T64 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1720020381 |
|
|
Apr 25 12:49:15 PM PDT 24 |
Apr 25 12:49:18 PM PDT 24 |
23127845 ps |
| T956 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4264201287 |
|
|
Apr 25 12:48:47 PM PDT 24 |
Apr 25 12:48:53 PM PDT 24 |
1406076814 ps |
| T65 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3765802427 |
|
|
Apr 25 12:49:10 PM PDT 24 |
Apr 25 12:50:03 PM PDT 24 |
7074057094 ps |
| T957 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1067336854 |
|
|
Apr 25 12:49:12 PM PDT 24 |
Apr 25 12:49:16 PM PDT 24 |
32163202 ps |
| T66 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.235920176 |
|
|
Apr 25 12:49:13 PM PDT 24 |
Apr 25 12:50:10 PM PDT 24 |
15291117035 ps |
| T958 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1291692021 |
|
|
Apr 25 12:49:11 PM PDT 24 |
Apr 25 12:49:19 PM PDT 24 |
1579066733 ps |
| T959 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4155397365 |
|
|
Apr 25 12:49:27 PM PDT 24 |
Apr 25 12:49:31 PM PDT 24 |
150288773 ps |
| T77 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2973716752 |
|
|
Apr 25 12:49:06 PM PDT 24 |
Apr 25 12:49:11 PM PDT 24 |
11454585 ps |
| T83 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1821294557 |
|
|
Apr 25 12:49:00 PM PDT 24 |
Apr 25 12:49:07 PM PDT 24 |
14726203 ps |
| T960 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3283710086 |
|
|
Apr 25 12:49:24 PM PDT 24 |
Apr 25 12:49:30 PM PDT 24 |
154803778 ps |
| T961 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2908326327 |
|
|
Apr 25 12:49:04 PM PDT 24 |
Apr 25 12:49:09 PM PDT 24 |
11809961 ps |
| T962 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3639820429 |
|
|
Apr 25 12:49:28 PM PDT 24 |
Apr 25 12:49:30 PM PDT 24 |
14549253 ps |
| T78 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2040166111 |
|
|
Apr 25 12:48:56 PM PDT 24 |
Apr 25 12:49:58 PM PDT 24 |
32056257418 ps |
| T963 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3106954475 |
|
|
Apr 25 12:49:26 PM PDT 24 |
Apr 25 12:49:30 PM PDT 24 |
385467067 ps |
| T79 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2900318750 |
|
|
Apr 25 12:49:29 PM PDT 24 |
Apr 25 12:49:57 PM PDT 24 |
15547611746 ps |
| T127 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.326978064 |
|
|
Apr 25 12:49:00 PM PDT 24 |
Apr 25 12:49:08 PM PDT 24 |
199562082 ps |
| T964 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1531557423 |
|
|
Apr 25 12:49:26 PM PDT 24 |
Apr 25 12:49:28 PM PDT 24 |
18886660 ps |
| T965 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3134361820 |
|
|
Apr 25 12:49:11 PM PDT 24 |
Apr 25 12:49:44 PM PDT 24 |
3891044721 ps |
| T80 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4072674733 |
|
|
Apr 25 12:49:06 PM PDT 24 |
Apr 25 12:50:03 PM PDT 24 |
28175742641 ps |
| T966 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2691470974 |
|
|
Apr 25 12:49:03 PM PDT 24 |
Apr 25 12:49:11 PM PDT 24 |
691717758 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2843718355 |
|
|
Apr 25 12:49:05 PM PDT 24 |
Apr 25 12:49:10 PM PDT 24 |
24413910 ps |
| T968 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2620315566 |
|
|
Apr 25 12:48:58 PM PDT 24 |
Apr 25 12:49:06 PM PDT 24 |
29122044 ps |
| T81 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.313175982 |
|
|
Apr 25 12:49:05 PM PDT 24 |
Apr 25 12:49:10 PM PDT 24 |
17091093 ps |
| T120 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.187213990 |
|
|
Apr 25 12:49:06 PM PDT 24 |
Apr 25 12:49:12 PM PDT 24 |
515228108 ps |
| T969 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.776302259 |
|
|
Apr 25 12:49:11 PM PDT 24 |
Apr 25 12:49:16 PM PDT 24 |
49284141 ps |
| T970 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1266139776 |
|
|
Apr 25 12:49:07 PM PDT 24 |
Apr 25 12:49:43 PM PDT 24 |
16838772819 ps |
| T971 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1260221018 |
|
|
Apr 25 12:49:11 PM PDT 24 |
Apr 25 12:49:18 PM PDT 24 |
81669698 ps |
| T125 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2765479088 |
|
|
Apr 25 12:49:32 PM PDT 24 |
Apr 25 12:49:35 PM PDT 24 |
443291239 ps |
| T972 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.906083243 |
|
|
Apr 25 12:49:11 PM PDT 24 |
Apr 25 12:50:13 PM PDT 24 |
29402264470 ps |
| T973 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3881744279 |
|
|
Apr 25 12:49:12 PM PDT 24 |
Apr 25 12:49:16 PM PDT 24 |
23444880 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.6851041 |
|
|
Apr 25 12:49:04 PM PDT 24 |
Apr 25 12:49:10 PM PDT 24 |
16913705 ps |
| T975 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2944992819 |
|
|
Apr 25 12:48:55 PM PDT 24 |
Apr 25 12:49:52 PM PDT 24 |
7595063481 ps |
| T976 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2819249772 |
|
|
Apr 25 12:49:19 PM PDT 24 |
Apr 25 12:49:25 PM PDT 24 |
636251523 ps |
| T82 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3319357709 |
|
|
Apr 25 12:48:56 PM PDT 24 |
Apr 25 12:49:29 PM PDT 24 |
3963856951 ps |
| T977 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3998853874 |
|
|
Apr 25 12:49:17 PM PDT 24 |
Apr 25 12:49:19 PM PDT 24 |
58712356 ps |
| T978 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.463210525 |
|
|
Apr 25 12:49:33 PM PDT 24 |
Apr 25 12:49:35 PM PDT 24 |
40522479 ps |
| T979 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.477532613 |
|
|
Apr 25 12:49:01 PM PDT 24 |
Apr 25 12:49:09 PM PDT 24 |
140304206 ps |
| T980 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2818681814 |
|
|
Apr 25 12:49:14 PM PDT 24 |
Apr 25 12:49:20 PM PDT 24 |
454465256 ps |
| T981 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1190972116 |
|
|
Apr 25 12:49:07 PM PDT 24 |
Apr 25 12:49:12 PM PDT 24 |
16673350 ps |
| T982 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4245342567 |
|
|
Apr 25 12:49:19 PM PDT 24 |
Apr 25 12:49:23 PM PDT 24 |
364273385 ps |
| T983 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.63332317 |
|
|
Apr 25 12:49:00 PM PDT 24 |
Apr 25 12:50:06 PM PDT 24 |
28122359021 ps |
| T984 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1961538829 |
|
|
Apr 25 12:49:10 PM PDT 24 |
Apr 25 12:49:18 PM PDT 24 |
460798010 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1945617793 |
|
|
Apr 25 12:49:02 PM PDT 24 |
Apr 25 12:49:08 PM PDT 24 |
42914795 ps |
| T986 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2066512672 |
|
|
Apr 25 12:49:11 PM PDT 24 |
Apr 25 12:49:18 PM PDT 24 |
799499301 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2883359968 |
|
|
Apr 25 12:48:47 PM PDT 24 |
Apr 25 12:48:50 PM PDT 24 |
44165790 ps |
| T988 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2084731133 |
|
|
Apr 25 12:49:18 PM PDT 24 |
Apr 25 12:49:23 PM PDT 24 |
1917668084 ps |
| T989 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2014552222 |
|
|
Apr 25 12:48:57 PM PDT 24 |
Apr 25 12:49:06 PM PDT 24 |
255812897 ps |
| T990 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3650427963 |
|
|
Apr 25 12:49:18 PM PDT 24 |
Apr 25 12:49:22 PM PDT 24 |
106818230 ps |
| T991 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1169156779 |
|
|
Apr 25 12:49:26 PM PDT 24 |
Apr 25 12:49:55 PM PDT 24 |
3788214171 ps |
| T992 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2853785973 |
|
|
Apr 25 12:49:06 PM PDT 24 |
Apr 25 12:49:11 PM PDT 24 |
14001384 ps |
| T993 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2884524323 |
|
|
Apr 25 12:49:18 PM PDT 24 |
Apr 25 12:49:22 PM PDT 24 |
61937990 ps |
| T994 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.694137481 |
|
|
Apr 25 12:49:07 PM PDT 24 |
Apr 25 12:49:14 PM PDT 24 |
327965371 ps |
| T995 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1754397623 |
|
|
Apr 25 12:49:07 PM PDT 24 |
Apr 25 12:49:12 PM PDT 24 |
82382033 ps |
| T996 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.154881137 |
|
|
Apr 25 12:49:10 PM PDT 24 |
Apr 25 12:49:15 PM PDT 24 |
15238902 ps |
| T997 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2256138786 |
|
|
Apr 25 12:49:14 PM PDT 24 |
Apr 25 12:49:20 PM PDT 24 |
121801118 ps |
| T126 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2017811406 |
|
|
Apr 25 12:49:09 PM PDT 24 |
Apr 25 12:49:15 PM PDT 24 |
167608820 ps |
| T998 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1191732856 |
|
|
Apr 25 12:49:10 PM PDT 24 |
Apr 25 12:49:18 PM PDT 24 |
402062122 ps |
| T999 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2735825353 |
|
|
Apr 25 12:49:12 PM PDT 24 |
Apr 25 12:49:17 PM PDT 24 |
119596093 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4169197131 |
|
|
Apr 25 12:49:05 PM PDT 24 |
Apr 25 12:49:18 PM PDT 24 |
42212266 ps |
| T1001 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3570039031 |
|
|
Apr 25 12:49:23 PM PDT 24 |
Apr 25 12:49:24 PM PDT 24 |
35458226 ps |
| T1002 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3223891917 |
|
|
Apr 25 12:48:58 PM PDT 24 |
Apr 25 12:49:08 PM PDT 24 |
368862116 ps |
| T1003 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1391117848 |
|
|
Apr 25 12:49:17 PM PDT 24 |
Apr 25 12:49:19 PM PDT 24 |
56191282 ps |