Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	361450038	1			T1	258240		T2	3514		T3	6564
instr_valid_dis	324713516	1			T1	258240		T2	3514		T3	6564
instr_en	23665556	1			T4	38176		T16	289090		T28	233870

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12458982	1			T4	40162		T16	43376		T28	39634
sram_ifetch_valid_disable	319129344	1			T1	258240		T2	3514		T3	6564
sram_ifetch_enable	29861712	1			T4	198650		T16	102968		T28	128704

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	361450038	1			T1	258240		T2	3514		T3	6564
hw_debug_en_valid_off	319840113	1			T1	258240		T2	3514		T3	6564
hw_debug_en_on	29162528	1			T4	190662		T16	218764		T28	161522

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	319129344	1			T1	258240		T2	3514		T3	6564
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	306545540	1			T1	258240		T2	3514		T3	6564
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9152212	1			T4	38176		T16	142746		T28	123826
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4532860	1			T4	9200		T28	29312		T6	32322
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2287570	1			T4	9200		T28	13738		T50	46152
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1599670	1			T6	32322		T7	44518		T138	32426
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4238534	1			T4	778		T28	10322		T6	38862
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1916078	1			T4	778		T28	10322		T50	30934
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1482370	1			T6	38862		T7	49798		T139	28718
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10404592	1			T4	50600		T16	122524		T28	63424
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4160154	1			T4	50600		T28	54308		T6	286692
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4640240	1			T16	122524		T28	9116		T6	65882

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10690500	1			T16	102968		T28	110044		T6	124420
lc_exec_en	14519402	1			T4	139284		T16	96240		T28	87776
valid_exec_dis	317902697	1			T1	258240		T2	3514		T3	6564
invalid_exec_dis	42320694	1			T4	238812		T16	146344		T28	168338