Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52


Total tests in report: 1036
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
83.61 83.61 97.38 97.38 83.90 83.90 92.51 92.51 71.43 71.43 92.96 92.96 94.95 94.95 52.13 52.13 /workspace/coverage/default/26.sram_ctrl_regwen.3846989743
91.46 7.85 98.97 1.59 86.75 2.86 93.82 1.31 100.00 28.57 96.34 3.38 94.95 0.00 69.39 17.25 /workspace/coverage/default/25.sram_ctrl_stress_all.2059068276
95.40 3.94 99.35 0.37 90.78 4.03 97.59 3.76 100.00 0.00 97.18 0.85 96.29 1.34 86.64 17.25 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1890953756
96.43 1.02 99.53 0.19 91.69 0.91 97.80 0.21 100.00 0.00 98.03 0.85 96.29 0.00 91.65 5.01 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3334743476
97.04 0.61 99.72 0.19 93.64 1.95 98.15 0.36 100.00 0.00 98.87 0.85 96.88 0.59 92.02 0.37 /workspace/coverage/default/0.sram_ctrl_sec_cm.568180757
97.64 0.60 99.72 0.00 93.64 0.00 98.69 0.53 100.00 0.00 98.87 0.00 97.03 0.15 95.55 3.53 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2712203955
97.84 0.20 99.72 0.00 93.64 0.00 98.76 0.07 100.00 0.00 98.87 0.00 98.37 1.34 95.55 0.00 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2819729894
98.04 0.20 99.72 0.00 94.03 0.39 99.18 0.43 100.00 0.00 98.87 0.00 98.37 0.00 96.10 0.56 /workspace/coverage/default/10.sram_ctrl_alert_test.3856841417
98.20 0.16 99.72 0.00 94.16 0.13 99.29 0.11 100.00 0.00 98.87 0.00 99.26 0.89 96.10 0.00 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3438947932
98.33 0.13 99.72 0.00 94.16 0.00 99.29 0.00 100.00 0.00 98.87 0.00 99.26 0.00 97.03 0.93 /workspace/coverage/default/46.sram_ctrl_stress_all.2389410184
98.45 0.11 99.81 0.09 94.16 0.00 100.00 0.71 100.00 0.00 98.87 0.00 99.26 0.00 97.03 0.00 /workspace/coverage/default/2.sram_ctrl_ram_cfg.3125253850
98.55 0.11 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.26 0.00 97.77 0.74 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2612575433
98.63 0.08 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.26 0.00 98.33 0.56 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2038802758
98.70 0.06 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.45 98.33 0.00 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.46955787
98.72 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.00 98.52 0.19 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4174419405

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2219353761
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.547812959
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3359656045
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.61428871
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3569362380
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2749437598
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2243261363
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1844364209
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1024678426
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3737785330
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.721000290
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3579986399
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3977154630
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.59336602
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2782844528
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1660210373
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2950360602
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3033724400
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.628848148
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2299684225
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1200752021
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.791136347
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2498941600
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1134370801
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2060675352
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.177146141
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.205421378
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3439686315
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.464998928
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1476319661
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2718382802
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.363409368
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1290413419
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3606116989
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2358074927
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.374225704
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2058530606
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2968581872
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.393945923
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3822205536
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1350600355
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1517447581
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4203046083
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.518221570
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.378978897
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.852671641
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2927105600
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2128336103
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.37733744
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3616826241
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1800516812
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1103697274
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.666929546
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4147229541
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2998423762
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1547329803
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1844703252
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2296050934
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2470216931
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.426772305
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3429949715
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1780226674
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2568573746
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1596986449
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.153457884
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3349880666
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1242761390
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.338931918
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2599664782
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2028098217
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1917822290
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1273317593
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3618786219
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1054567997
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4015414774
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2957186661
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.115579665
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2186761620
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.619094476
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1223768829
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.528105817
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.826207109
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3739799387
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1572000279
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.368584602
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2946192871
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.912991068
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2202496726
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1360276501
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2373902122
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2774441132
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1861819305
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3068393446
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2169338555
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.604478132
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1381440944
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2699290123
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3580557785
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2783857723
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3739967066
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4131922297
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1792990981
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.88778474
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.95446531
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1215164092
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2526610625
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3707766155
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3952808926
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.690862636
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2117079868
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3561917138
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3235941777
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.171511194
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.856125688
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2057851237
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.956505346
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4072090255
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3416088071
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.329527761
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3682619248
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.360850629
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3858015187
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2523221492
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2854597590
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2740023721
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3265554285
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3582106636
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4217265654
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1452046368
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3184293469
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.452751126
/workspace/coverage/default/0.sram_ctrl_alert_test.1797999464
/workspace/coverage/default/0.sram_ctrl_bijection.2487969609
/workspace/coverage/default/0.sram_ctrl_executable.2917916643
/workspace/coverage/default/0.sram_ctrl_lc_escalation.4040982
/workspace/coverage/default/0.sram_ctrl_max_throughput.772336681
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2310730864
/workspace/coverage/default/0.sram_ctrl_mem_walk.3546721501
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2000653367
/workspace/coverage/default/0.sram_ctrl_partial_access.3937057080
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1697766752
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1674911567
/workspace/coverage/default/0.sram_ctrl_regwen.300448326
/workspace/coverage/default/0.sram_ctrl_smoke.1464574684
/workspace/coverage/default/0.sram_ctrl_stress_all.655226757
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.347359337
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3876934367
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3826043184
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1280502395
/workspace/coverage/default/1.sram_ctrl_alert_test.318332277
/workspace/coverage/default/1.sram_ctrl_bijection.851609382
/workspace/coverage/default/1.sram_ctrl_executable.3472417096
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3282320899
/workspace/coverage/default/1.sram_ctrl_max_throughput.556976801
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2629247370
/workspace/coverage/default/1.sram_ctrl_mem_walk.1416294308
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2444578436
/workspace/coverage/default/1.sram_ctrl_partial_access.1125963282
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2629934675
/workspace/coverage/default/1.sram_ctrl_ram_cfg.216590167
/workspace/coverage/default/1.sram_ctrl_regwen.3491360474
/workspace/coverage/default/1.sram_ctrl_sec_cm.3540947334
/workspace/coverage/default/1.sram_ctrl_smoke.1814142252
/workspace/coverage/default/1.sram_ctrl_stress_all.3413002179
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2926834470
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2235275863
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3722162346
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.808806008
/workspace/coverage/default/10.sram_ctrl_bijection.2065536515
/workspace/coverage/default/10.sram_ctrl_executable.521764478
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2476388962
/workspace/coverage/default/10.sram_ctrl_max_throughput.3250202886
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2448449086
/workspace/coverage/default/10.sram_ctrl_mem_walk.2838570133
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1288483706
/workspace/coverage/default/10.sram_ctrl_partial_access.2825807844
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.4272117982
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1499111429
/workspace/coverage/default/10.sram_ctrl_regwen.2063957412
/workspace/coverage/default/10.sram_ctrl_smoke.3798687061
/workspace/coverage/default/10.sram_ctrl_stress_all.3593901157
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2474976685
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2017081693
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1161561576
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2380302860
/workspace/coverage/default/11.sram_ctrl_alert_test.3206917790
/workspace/coverage/default/11.sram_ctrl_bijection.3171003714
/workspace/coverage/default/11.sram_ctrl_executable.974996123
/workspace/coverage/default/11.sram_ctrl_lc_escalation.903772004
/workspace/coverage/default/11.sram_ctrl_max_throughput.1276966669
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.938481852
/workspace/coverage/default/11.sram_ctrl_mem_walk.481444118
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1169698
/workspace/coverage/default/11.sram_ctrl_partial_access.1086599996
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2169988161
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2927201880
/workspace/coverage/default/11.sram_ctrl_regwen.463479564
/workspace/coverage/default/11.sram_ctrl_smoke.3957661860
/workspace/coverage/default/11.sram_ctrl_stress_all.1907446865
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2269596584
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.170433418
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2131276775
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1533584184
/workspace/coverage/default/12.sram_ctrl_alert_test.179748310
/workspace/coverage/default/12.sram_ctrl_bijection.184526316
/workspace/coverage/default/12.sram_ctrl_executable.3903293077
/workspace/coverage/default/12.sram_ctrl_lc_escalation.829165041
/workspace/coverage/default/12.sram_ctrl_max_throughput.132778133
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3420725165
/workspace/coverage/default/12.sram_ctrl_mem_walk.1812857399
/workspace/coverage/default/12.sram_ctrl_multiple_keys.214857195
/workspace/coverage/default/12.sram_ctrl_partial_access.2701347256
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1745473818
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3562450359
/workspace/coverage/default/12.sram_ctrl_regwen.1729360450
/workspace/coverage/default/12.sram_ctrl_smoke.3149676238
/workspace/coverage/default/12.sram_ctrl_stress_all.339989363
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/workspace/coverage/default/43.sram_ctrl_mem_walk.4279098577
/workspace/coverage/default/43.sram_ctrl_multiple_keys.103010927
/workspace/coverage/default/43.sram_ctrl_partial_access.3175121868
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1388894328
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1986487284
/workspace/coverage/default/43.sram_ctrl_regwen.1397450833
/workspace/coverage/default/43.sram_ctrl_smoke.3720747217
/workspace/coverage/default/43.sram_ctrl_stress_all.3948438075
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3490655674
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3208241072
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.773407924
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.812718500
/workspace/coverage/default/44.sram_ctrl_alert_test.3572519980
/workspace/coverage/default/44.sram_ctrl_bijection.1246934627
/workspace/coverage/default/44.sram_ctrl_executable.701398120
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1410068103
/workspace/coverage/default/44.sram_ctrl_max_throughput.2651853226
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3367106833
/workspace/coverage/default/44.sram_ctrl_mem_walk.3923130896
/workspace/coverage/default/44.sram_ctrl_multiple_keys.383587456
/workspace/coverage/default/44.sram_ctrl_partial_access.2902758039
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2132666623
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3630261271
/workspace/coverage/default/44.sram_ctrl_regwen.393793366
/workspace/coverage/default/44.sram_ctrl_smoke.81169127
/workspace/coverage/default/44.sram_ctrl_stress_all.2357180141
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1056493635
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2661262913
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1920300896
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3626478518
/workspace/coverage/default/45.sram_ctrl_alert_test.2454879857
/workspace/coverage/default/45.sram_ctrl_bijection.408416445
/workspace/coverage/default/45.sram_ctrl_executable.1822896628
/workspace/coverage/default/45.sram_ctrl_lc_escalation.980802395
/workspace/coverage/default/45.sram_ctrl_max_throughput.3014486828
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.475379002
/workspace/coverage/default/45.sram_ctrl_mem_walk.1250785028
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3213826836
/workspace/coverage/default/45.sram_ctrl_partial_access.792304695
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2387980727
/workspace/coverage/default/45.sram_ctrl_ram_cfg.762459946
/workspace/coverage/default/45.sram_ctrl_regwen.2079742737
/workspace/coverage/default/45.sram_ctrl_smoke.3837519338
/workspace/coverage/default/45.sram_ctrl_stress_all.2879457662
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.278986301
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2439718204
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.857748241
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2454147674
/workspace/coverage/default/46.sram_ctrl_alert_test.1934271782
/workspace/coverage/default/46.sram_ctrl_bijection.395709092
/workspace/coverage/default/46.sram_ctrl_executable.3681550533
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3461267690
/workspace/coverage/default/46.sram_ctrl_max_throughput.2978675746
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.490283771
/workspace/coverage/default/46.sram_ctrl_mem_walk.3887804568
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2830362244
/workspace/coverage/default/46.sram_ctrl_partial_access.3869381233
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4247309941
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3352161669
/workspace/coverage/default/46.sram_ctrl_regwen.1410105742
/workspace/coverage/default/46.sram_ctrl_smoke.558571892
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3893201210
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3942500
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3162695534
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.464709405
/workspace/coverage/default/47.sram_ctrl_alert_test.1521565479
/workspace/coverage/default/47.sram_ctrl_bijection.717071933
/workspace/coverage/default/47.sram_ctrl_executable.3035468757
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1560299410
/workspace/coverage/default/47.sram_ctrl_max_throughput.2329171562
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3228794466
/workspace/coverage/default/47.sram_ctrl_mem_walk.4092241087
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1199948248
/workspace/coverage/default/47.sram_ctrl_partial_access.995128574
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.786347771
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1075198109
/workspace/coverage/default/47.sram_ctrl_regwen.4075688698
/workspace/coverage/default/47.sram_ctrl_smoke.530572836
/workspace/coverage/default/47.sram_ctrl_stress_all.995433466
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.819085168
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3528102158
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1901348644
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1602187282
/workspace/coverage/default/48.sram_ctrl_alert_test.3570479509
/workspace/coverage/default/48.sram_ctrl_bijection.2422123365
/workspace/coverage/default/48.sram_ctrl_executable.1532134312
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1086415470
/workspace/coverage/default/48.sram_ctrl_max_throughput.3109614786
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3684897600
/workspace/coverage/default/48.sram_ctrl_mem_walk.1732000312
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2194776595
/workspace/coverage/default/48.sram_ctrl_partial_access.11736113
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.969405403
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3717725946
/workspace/coverage/default/48.sram_ctrl_regwen.494437359
/workspace/coverage/default/48.sram_ctrl_smoke.2672844252
/workspace/coverage/default/48.sram_ctrl_stress_all.1881811543
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3747367796
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2523740106
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1794573625
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2010979082
/workspace/coverage/default/49.sram_ctrl_alert_test.1405861648
/workspace/coverage/default/49.sram_ctrl_bijection.1858647752
/workspace/coverage/default/49.sram_ctrl_executable.3444108676
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2110154757
/workspace/coverage/default/49.sram_ctrl_max_throughput.4194009219
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.374455557
/workspace/coverage/default/49.sram_ctrl_mem_walk.857010609
/workspace/coverage/default/49.sram_ctrl_multiple_keys.419138509
/workspace/coverage/default/49.sram_ctrl_partial_access.3074757954
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1011327277
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2012374038
/workspace/coverage/default/49.sram_ctrl_regwen.3901292695
/workspace/coverage/default/49.sram_ctrl_smoke.48330398
/workspace/coverage/default/49.sram_ctrl_stress_all.3171849199
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1338080782
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3754682566
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.119551844
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.477836291
/workspace/coverage/default/5.sram_ctrl_alert_test.3455097088
/workspace/coverage/default/5.sram_ctrl_bijection.3850934430
/workspace/coverage/default/5.sram_ctrl_executable.1954900957
/workspace/coverage/default/5.sram_ctrl_lc_escalation.146893037
/workspace/coverage/default/5.sram_ctrl_max_throughput.506507774
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1678195176
/workspace/coverage/default/5.sram_ctrl_mem_walk.4010075774
/workspace/coverage/default/5.sram_ctrl_multiple_keys.113664672
/workspace/coverage/default/5.sram_ctrl_partial_access.1360533349
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2713674822
/workspace/coverage/default/5.sram_ctrl_ram_cfg.387639586
/workspace/coverage/default/5.sram_ctrl_regwen.208230846
/workspace/coverage/default/5.sram_ctrl_smoke.2351619779
/workspace/coverage/default/5.sram_ctrl_stress_all.2028456923
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1109444397
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.4250260902
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1535666062
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.697924727
/workspace/coverage/default/6.sram_ctrl_alert_test.809453649
/workspace/coverage/default/6.sram_ctrl_bijection.630272510
/workspace/coverage/default/6.sram_ctrl_executable.3241552057
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1261413572
/workspace/coverage/default/6.sram_ctrl_max_throughput.3620899898
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1675557354
/workspace/coverage/default/6.sram_ctrl_mem_walk.1284813015
/workspace/coverage/default/6.sram_ctrl_multiple_keys.600224607
/workspace/coverage/default/6.sram_ctrl_partial_access.1918608261
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2875044473
/workspace/coverage/default/6.sram_ctrl_ram_cfg.4232082292
/workspace/coverage/default/6.sram_ctrl_regwen.3189366573
/workspace/coverage/default/6.sram_ctrl_smoke.3840839144
/workspace/coverage/default/6.sram_ctrl_stress_all.3833937787
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1193957542
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2661169667
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2525552751
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1707877562
/workspace/coverage/default/7.sram_ctrl_alert_test.1690910799
/workspace/coverage/default/7.sram_ctrl_bijection.923843142
/workspace/coverage/default/7.sram_ctrl_executable.3206806428
/workspace/coverage/default/7.sram_ctrl_lc_escalation.258890899
/workspace/coverage/default/7.sram_ctrl_max_throughput.2941367080
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1597043171
/workspace/coverage/default/7.sram_ctrl_mem_walk.3011209981
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1483508120
/workspace/coverage/default/7.sram_ctrl_partial_access.2474954734
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3205735076
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3696261744
/workspace/coverage/default/7.sram_ctrl_regwen.1552954032
/workspace/coverage/default/7.sram_ctrl_smoke.598908127
/workspace/coverage/default/7.sram_ctrl_stress_all.2637027056
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.152383280
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3704766488
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2088927088
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2384471091
/workspace/coverage/default/8.sram_ctrl_alert_test.4122794382
/workspace/coverage/default/8.sram_ctrl_bijection.4181884932
/workspace/coverage/default/8.sram_ctrl_executable.2363422292
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3179739140
/workspace/coverage/default/8.sram_ctrl_max_throughput.3535349113
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3181850880
/workspace/coverage/default/8.sram_ctrl_mem_walk.980703999
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3654465503
/workspace/coverage/default/8.sram_ctrl_partial_access.88180355
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2201651634
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1109150661
/workspace/coverage/default/8.sram_ctrl_regwen.3817501058
/workspace/coverage/default/8.sram_ctrl_smoke.3307665624
/workspace/coverage/default/8.sram_ctrl_stress_all.1886598334
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3038422010
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2186866951
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3158577326
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3163460600
/workspace/coverage/default/9.sram_ctrl_alert_test.771932519
/workspace/coverage/default/9.sram_ctrl_bijection.1932207580
/workspace/coverage/default/9.sram_ctrl_executable.3902531669
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1358769456
/workspace/coverage/default/9.sram_ctrl_max_throughput.1607423829
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.4240846737
/workspace/coverage/default/9.sram_ctrl_mem_walk.1270879814
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2170423655
/workspace/coverage/default/9.sram_ctrl_partial_access.1353512771
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2186814501
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3984691582
/workspace/coverage/default/9.sram_ctrl_regwen.4278392423
/workspace/coverage/default/9.sram_ctrl_smoke.2066603780
/workspace/coverage/default/9.sram_ctrl_stress_all.2647905545
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3959460600
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2766995169
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.699358551



Total test records in report: 1036
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3438947932 Apr 28 03:03:21 PM PDT 24 Apr 28 03:17:28 PM PDT 24 8239608708 ps
T2 /workspace/coverage/default/44.sram_ctrl_partial_access.2902758039 Apr 28 03:06:01 PM PDT 24 Apr 28 03:06:08 PM PDT 24 565035143 ps
T3 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1890953756 Apr 28 03:03:36 PM PDT 24 Apr 28 03:03:50 PM PDT 24 902720709 ps
T5 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2186866951 Apr 28 03:00:26 PM PDT 24 Apr 28 03:02:41 PM PDT 24 24424444976 ps
T9 /workspace/coverage/default/31.sram_ctrl_multiple_keys.655673407 Apr 28 03:03:19 PM PDT 24 Apr 28 03:07:24 PM PDT 24 11056347762 ps
T10 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.4095559042 Apr 28 03:00:07 PM PDT 24 Apr 28 03:02:27 PM PDT 24 787730830 ps
T4 /workspace/coverage/default/26.sram_ctrl_regwen.3846989743 Apr 28 03:02:32 PM PDT 24 Apr 28 03:22:42 PM PDT 24 77055292816 ps
T11 /workspace/coverage/default/31.sram_ctrl_ram_cfg.651463817 Apr 28 03:03:24 PM PDT 24 Apr 28 03:03:28 PM PDT 24 358335492 ps
T12 /workspace/coverage/default/26.sram_ctrl_smoke.3751029150 Apr 28 03:02:22 PM PDT 24 Apr 28 03:02:35 PM PDT 24 804469264 ps
T13 /workspace/coverage/default/39.sram_ctrl_max_throughput.1450309561 Apr 28 03:05:02 PM PDT 24 Apr 28 03:05:08 PM PDT 24 8318850449 ps
T16 /workspace/coverage/default/9.sram_ctrl_regwen.4278392423 Apr 28 03:00:17 PM PDT 24 Apr 28 03:20:24 PM PDT 24 43693396382 ps
T17 /workspace/coverage/default/42.sram_ctrl_smoke.2131276770 Apr 28 03:05:37 PM PDT 24 Apr 28 03:05:52 PM PDT 24 4386877651 ps
T14 /workspace/coverage/default/0.sram_ctrl_multiple_keys.2000653367 Apr 28 02:59:57 PM PDT 24 Apr 28 03:08:09 PM PDT 24 66079023798 ps
T29 /workspace/coverage/default/48.sram_ctrl_ram_cfg.3717725946 Apr 28 03:07:01 PM PDT 24 Apr 28 03:07:05 PM PDT 24 1403819927 ps
T21 /workspace/coverage/default/5.sram_ctrl_alert_test.3455097088 Apr 28 03:00:20 PM PDT 24 Apr 28 03:00:26 PM PDT 24 12382218 ps
T22 /workspace/coverage/default/28.sram_ctrl_alert_test.1463779768 Apr 28 03:02:53 PM PDT 24 Apr 28 03:02:54 PM PDT 24 35228704 ps
T64 /workspace/coverage/default/12.sram_ctrl_partial_access.2701347256 Apr 28 03:00:23 PM PDT 24 Apr 28 03:02:30 PM PDT 24 3956679206 ps
T15 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2712203955 Apr 28 03:00:53 PM PDT 24 Apr 28 03:06:41 PM PDT 24 16855595417 ps
T65 /workspace/coverage/default/38.sram_ctrl_multiple_keys.2500052998 Apr 28 03:04:42 PM PDT 24 Apr 28 03:18:06 PM PDT 24 35965901576 ps
T152 /workspace/coverage/default/39.sram_ctrl_partial_access.476251678 Apr 28 03:05:01 PM PDT 24 Apr 28 03:05:16 PM PDT 24 1010517940 ps
T66 /workspace/coverage/default/9.sram_ctrl_partial_access.1353512771 Apr 28 03:00:21 PM PDT 24 Apr 28 03:02:03 PM PDT 24 3886325841 ps
T24 /workspace/coverage/default/16.sram_ctrl_bijection.84419310 Apr 28 03:01:00 PM PDT 24 Apr 28 03:36:11 PM PDT 24 126767392992 ps
T149 /workspace/coverage/default/36.sram_ctrl_max_throughput.456669720 Apr 28 03:04:20 PM PDT 24 Apr 28 03:04:49 PM PDT 24 2988988418 ps
T145 /workspace/coverage/default/7.sram_ctrl_max_throughput.2941367080 Apr 28 03:00:10 PM PDT 24 Apr 28 03:01:16 PM PDT 24 789052486 ps
T28 /workspace/coverage/default/49.sram_ctrl_executable.3444108676 Apr 28 03:07:15 PM PDT 24 Apr 28 03:28:24 PM PDT 24 93774841935 ps
T6 /workspace/coverage/default/46.sram_ctrl_stress_all.2389410184 Apr 28 03:06:41 PM PDT 24 Apr 28 04:42:42 PM PDT 24 203841251282 ps
T7 /workspace/coverage/default/13.sram_ctrl_stress_all.1548615910 Apr 28 03:00:44 PM PDT 24 Apr 28 05:07:47 PM PDT 24 394746420179 ps
T23 /workspace/coverage/default/2.sram_ctrl_alert_test.4179021585 Apr 28 03:00:08 PM PDT 24 Apr 28 03:00:10 PM PDT 24 24605257 ps
T151 /workspace/coverage/default/19.sram_ctrl_multiple_keys.4052233096 Apr 28 03:01:20 PM PDT 24 Apr 28 03:09:12 PM PDT 24 10612031229 ps
T153 /workspace/coverage/default/30.sram_ctrl_partial_access.1203992643 Apr 28 03:03:05 PM PDT 24 Apr 28 03:03:25 PM PDT 24 9428730374 ps
T154 /workspace/coverage/default/9.sram_ctrl_smoke.2066603780 Apr 28 03:00:25 PM PDT 24 Apr 28 03:00:41 PM PDT 24 1482176090 ps
T71 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.4240846737 Apr 28 03:00:17 PM PDT 24 Apr 28 03:02:49 PM PDT 24 45226925371 ps
T140 /workspace/coverage/default/32.sram_ctrl_bijection.566242899 Apr 28 03:03:29 PM PDT 24 Apr 28 03:51:11 PM PDT 24 167916963002 ps
T50 /workspace/coverage/default/24.sram_ctrl_stress_all.2906637215 Apr 28 03:02:13 PM PDT 24 Apr 28 03:40:31 PM PDT 24 32708465423 ps
T91 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2991864569 Apr 28 03:03:17 PM PDT 24 Apr 28 03:06:53 PM PDT 24 20659463408 ps
T92 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.118431596 Apr 28 03:02:09 PM PDT 24 Apr 28 03:08:27 PM PDT 24 47923856325 ps
T144 /workspace/coverage/default/10.sram_ctrl_alert_test.3856841417 Apr 28 03:00:20 PM PDT 24 Apr 28 03:00:27 PM PDT 24 25933645 ps
T93 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1745473818 Apr 28 03:00:24 PM PDT 24 Apr 28 03:07:19 PM PDT 24 34772407463 ps
T8 /workspace/coverage/default/25.sram_ctrl_stress_all.2059068276 Apr 28 03:02:20 PM PDT 24 Apr 28 04:28:09 PM PDT 24 120888446148 ps
T155 /workspace/coverage/default/15.sram_ctrl_max_throughput.3643652686 Apr 28 03:00:56 PM PDT 24 Apr 28 03:01:21 PM PDT 24 771684166 ps
T156 /workspace/coverage/default/29.sram_ctrl_mem_walk.3520894912 Apr 28 03:03:01 PM PDT 24 Apr 28 03:06:58 PM PDT 24 3943817853 ps
T139 /workspace/coverage/default/41.sram_ctrl_executable.3450613957 Apr 28 03:05:28 PM PDT 24 Apr 28 03:11:30 PM PDT 24 2341595491 ps
T142 /workspace/coverage/default/29.sram_ctrl_multiple_keys.3577590455 Apr 28 03:02:58 PM PDT 24 Apr 28 03:05:46 PM PDT 24 8352266540 ps
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T26 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1357051770 Apr 28 03:05:08 PM PDT 24 Apr 28 03:05:35 PM PDT 24 1900539633 ps
T157 /workspace/coverage/default/40.sram_ctrl_alert_test.4119922290 Apr 28 03:05:32 PM PDT 24 Apr 28 03:05:33 PM PDT 24 11471362 ps
T95 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3003258563 Apr 28 03:01:42 PM PDT 24 Apr 28 03:05:07 PM PDT 24 13421161166 ps
T42 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.2336935049 Apr 28 03:05:29 PM PDT 24 Apr 28 03:18:24 PM PDT 24 45100002594 ps
T72 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.490283771 Apr 28 03:06:40 PM PDT 24 Apr 28 03:07:57 PM PDT 24 2698927600 ps
T51 /workspace/coverage/default/12.sram_ctrl_regwen.1729360450 Apr 28 03:00:30 PM PDT 24 Apr 28 03:06:36 PM PDT 24 14663096845 ps
T158 /workspace/coverage/default/22.sram_ctrl_mem_walk.24844459 Apr 28 03:01:52 PM PDT 24 Apr 28 03:05:55 PM PDT 24 15767618941 ps
T143 /workspace/coverage/default/30.sram_ctrl_alert_test.2062060162 Apr 28 03:03:13 PM PDT 24 Apr 28 03:03:14 PM PDT 24 11753111 ps
T141 /workspace/coverage/default/18.sram_ctrl_bijection.2895774444 Apr 28 03:01:15 PM PDT 24 Apr 28 03:41:56 PM PDT 24 480549819092 ps
T159 /workspace/coverage/default/6.sram_ctrl_partial_access.1918608261 Apr 28 03:00:07 PM PDT 24 Apr 28 03:00:19 PM PDT 24 750240165 ps
T25 /workspace/coverage/default/33.sram_ctrl_stress_all.4095362154 Apr 28 03:03:51 PM PDT 24 Apr 28 03:46:12 PM PDT 24 104895163874 ps
T52 /workspace/coverage/default/2.sram_ctrl_regwen.1703233274 Apr 28 02:59:59 PM PDT 24 Apr 28 03:05:09 PM PDT 24 68927459161 ps
T160 /workspace/coverage/default/10.sram_ctrl_bijection.2065536515 Apr 28 03:00:17 PM PDT 24 Apr 28 03:07:45 PM PDT 24 6915478724 ps
T161 /workspace/coverage/default/32.sram_ctrl_mem_walk.3438992549 Apr 28 03:03:37 PM PDT 24 Apr 28 03:08:42 PM PDT 24 91915179747 ps
T96 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.153912297 Apr 28 03:00:48 PM PDT 24 Apr 28 03:07:14 PM PDT 24 39575878214 ps
T30 /workspace/coverage/default/23.sram_ctrl_ram_cfg.1250831901 Apr 28 03:02:13 PM PDT 24 Apr 28 03:02:18 PM PDT 24 656304260 ps
T162 /workspace/coverage/default/1.sram_ctrl_mem_walk.1416294308 Apr 28 03:00:02 PM PDT 24 Apr 28 03:04:39 PM PDT 24 27551294569 ps
T43 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.1558194113 Apr 28 03:02:23 PM PDT 24 Apr 28 03:05:05 PM PDT 24 7095980599 ps
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T135 /workspace/coverage/default/33.sram_ctrl_regwen.214646868 Apr 28 03:03:50 PM PDT 24 Apr 28 03:24:47 PM PDT 24 57921998046 ps
T146 /workspace/coverage/default/5.sram_ctrl_stress_all.2028456923 Apr 28 03:00:08 PM PDT 24 Apr 28 03:51:02 PM PDT 24 494936468966 ps
T147 /workspace/coverage/default/26.sram_ctrl_stress_all.862801629 Apr 28 03:02:41 PM PDT 24 Apr 28 04:28:05 PM PDT 24 1223488211739 ps
T163 /workspace/coverage/default/2.sram_ctrl_ram_cfg.3125253850 Apr 28 03:00:01 PM PDT 24 Apr 28 03:00:06 PM PDT 24 1346360541 ps
T73 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.374455557 Apr 28 03:07:15 PM PDT 24 Apr 28 03:08:26 PM PDT 24 4872194668 ps
T164 /workspace/coverage/default/33.sram_ctrl_multiple_keys.3828015243 Apr 28 03:03:47 PM PDT 24 Apr 28 03:08:37 PM PDT 24 33542967011 ps
T74 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.500297962 Apr 28 03:00:54 PM PDT 24 Apr 28 03:02:56 PM PDT 24 6514009302 ps
T165 /workspace/coverage/default/32.sram_ctrl_max_throughput.3816597732 Apr 28 03:03:28 PM PDT 24 Apr 28 03:04:14 PM PDT 24 734619712 ps
T148 /workspace/coverage/default/47.sram_ctrl_regwen.4075688698 Apr 28 03:06:45 PM PDT 24 Apr 28 03:18:22 PM PDT 24 24675734317 ps
T166 /workspace/coverage/default/26.sram_ctrl_max_throughput.679207036 Apr 28 03:02:27 PM PDT 24 Apr 28 03:03:36 PM PDT 24 753232603 ps
T75 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.1080883324 Apr 28 03:04:21 PM PDT 24 Apr 28 03:06:38 PM PDT 24 6736657842 ps
T150 /workspace/coverage/default/37.sram_ctrl_max_throughput.3759053547 Apr 28 03:04:32 PM PDT 24 Apr 28 03:05:42 PM PDT 24 739970711 ps
T138 /workspace/coverage/default/23.sram_ctrl_stress_all.3413503331 Apr 28 03:02:02 PM PDT 24 Apr 28 03:45:30 PM PDT 24 32158529300 ps
T167 /workspace/coverage/default/7.sram_ctrl_mem_walk.3011209981 Apr 28 03:00:14 PM PDT 24 Apr 28 03:05:38 PM PDT 24 71098058365 ps
T168 /workspace/coverage/default/2.sram_ctrl_partial_access.3099670246 Apr 28 03:00:06 PM PDT 24 Apr 28 03:00:20 PM PDT 24 1487247785 ps
T169 /workspace/coverage/default/16.sram_ctrl_alert_test.3424173409 Apr 28 03:01:03 PM PDT 24 Apr 28 03:01:07 PM PDT 24 13643077 ps
T97 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.2545635572 Apr 28 03:01:31 PM PDT 24 Apr 28 03:06:29 PM PDT 24 38769034545 ps
T76 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2894293400 Apr 28 03:02:54 PM PDT 24 Apr 28 03:03:58 PM PDT 24 1051626722 ps
T170 /workspace/coverage/default/3.sram_ctrl_smoke.426342685 Apr 28 03:00:05 PM PDT 24 Apr 28 03:00:24 PM PDT 24 869530468 ps
T171 /workspace/coverage/default/24.sram_ctrl_max_throughput.2568782829 Apr 28 03:02:10 PM PDT 24 Apr 28 03:04:12 PM PDT 24 768453851 ps
T172 /workspace/coverage/default/24.sram_ctrl_mem_walk.1469281484 Apr 28 03:02:09 PM PDT 24 Apr 28 03:07:13 PM PDT 24 31796514082 ps
T77 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.457036019 Apr 28 03:01:28 PM PDT 24 Apr 28 03:02:45 PM PDT 24 5018010899 ps
T173 /workspace/coverage/default/0.sram_ctrl_lc_escalation.4040982 Apr 28 03:00:00 PM PDT 24 Apr 28 03:00:37 PM PDT 24 13219279426 ps
T174 /workspace/coverage/default/31.sram_ctrl_mem_walk.3395269730 Apr 28 03:03:32 PM PDT 24 Apr 28 03:07:32 PM PDT 24 3942385113 ps
T175 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2380302860 Apr 28 03:00:17 PM PDT 24 Apr 28 03:18:10 PM PDT 24 11929855541 ps
T176 /workspace/coverage/default/34.sram_ctrl_multiple_keys.3801897303 Apr 28 03:03:57 PM PDT 24 Apr 28 03:23:32 PM PDT 24 83082076443 ps
T27 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3173008559 Apr 28 03:00:58 PM PDT 24 Apr 28 03:01:21 PM PDT 24 534118852 ps
T122 /workspace/coverage/default/23.sram_ctrl_lc_escalation.2741232856 Apr 28 03:02:00 PM PDT 24 Apr 28 03:03:17 PM PDT 24 22053618318 ps
T177 /workspace/coverage/default/7.sram_ctrl_partial_access.2474954734 Apr 28 03:00:26 PM PDT 24 Apr 28 03:00:53 PM PDT 24 4752671476 ps
T44 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1736802338 Apr 28 03:01:12 PM PDT 24 Apr 28 03:01:29 PM PDT 24 437013926 ps
T84 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.760462700 Apr 28 03:03:33 PM PDT 24 Apr 28 03:04:50 PM PDT 24 9830123247 ps
T178 /workspace/coverage/default/27.sram_ctrl_ram_cfg.363575261 Apr 28 03:02:44 PM PDT 24 Apr 28 03:02:48 PM PDT 24 712361684 ps
T179 /workspace/coverage/default/17.sram_ctrl_bijection.3546930292 Apr 28 03:01:03 PM PDT 24 Apr 28 03:33:47 PM PDT 24 33602972435 ps
T180 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2439718204 Apr 28 03:06:11 PM PDT 24 Apr 28 03:09:43 PM PDT 24 3161926458 ps
T181 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1597043171 Apr 28 03:00:16 PM PDT 24 Apr 28 03:01:33 PM PDT 24 4095956816 ps
T182 /workspace/coverage/default/43.sram_ctrl_executable.2290111077 Apr 28 03:05:52 PM PDT 24 Apr 28 03:10:48 PM PDT 24 33785198466 ps
T183 /workspace/coverage/default/10.sram_ctrl_smoke.3798687061 Apr 28 03:00:22 PM PDT 24 Apr 28 03:01:39 PM PDT 24 1582168648 ps
T184 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.1880034865 Apr 28 03:05:02 PM PDT 24 Apr 28 03:05:33 PM PDT 24 5567529507 ps
T185 /workspace/coverage/default/21.sram_ctrl_stress_all.877204570 Apr 28 03:01:47 PM PDT 24 Apr 28 03:37:22 PM PDT 24 115158001859 ps
T186 /workspace/coverage/default/26.sram_ctrl_ram_cfg.330306654 Apr 28 03:02:32 PM PDT 24 Apr 28 03:02:36 PM PDT 24 358350029 ps
T187 /workspace/coverage/default/47.sram_ctrl_alert_test.1521565479 Apr 28 03:06:55 PM PDT 24 Apr 28 03:06:56 PM PDT 24 33400789 ps
T188 /workspace/coverage/default/30.sram_ctrl_ram_cfg.1880682423 Apr 28 03:03:12 PM PDT 24 Apr 28 03:03:17 PM PDT 24 1464379903 ps
T189 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.4045097214 Apr 28 03:00:57 PM PDT 24 Apr 28 03:13:42 PM PDT 24 26332634911 ps
T190 /workspace/coverage/default/18.sram_ctrl_smoke.2297665087 Apr 28 03:01:14 PM PDT 24 Apr 28 03:01:57 PM PDT 24 3386467829 ps
T191 /workspace/coverage/default/48.sram_ctrl_partial_access.11736113 Apr 28 03:06:59 PM PDT 24 Apr 28 03:07:31 PM PDT 24 786261412 ps
T192 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.2343534680 Apr 28 03:01:04 PM PDT 24 Apr 28 03:17:18 PM PDT 24 16007411955 ps
T193 /workspace/coverage/default/33.sram_ctrl_alert_test.3572903031 Apr 28 03:03:51 PM PDT 24 Apr 28 03:03:52 PM PDT 24 30969809 ps
T194 /workspace/coverage/default/10.sram_ctrl_executable.521764478 Apr 28 03:00:17 PM PDT 24 Apr 28 03:13:22 PM PDT 24 25054381848 ps
T195 /workspace/coverage/default/25.sram_ctrl_regwen.411287072 Apr 28 03:02:21 PM PDT 24 Apr 28 03:05:27 PM PDT 24 11986112992 ps
T196 /workspace/coverage/default/2.sram_ctrl_mem_walk.571395854 Apr 28 03:00:07 PM PDT 24 Apr 28 03:04:57 PM PDT 24 14344481665 ps
T197 /workspace/coverage/default/19.sram_ctrl_executable.1471022572 Apr 28 03:01:25 PM PDT 24 Apr 28 03:27:36 PM PDT 24 22759166690 ps
T45 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2699103388 Apr 28 03:03:14 PM PDT 24 Apr 28 03:07:04 PM PDT 24 3661203590 ps
T198 /workspace/coverage/default/3.sram_ctrl_regwen.2906354807 Apr 28 03:00:07 PM PDT 24 Apr 28 03:29:12 PM PDT 24 80842072672 ps
T199 /workspace/coverage/default/21.sram_ctrl_regwen.1189958757 Apr 28 03:01:41 PM PDT 24 Apr 28 03:07:42 PM PDT 24 3809565376 ps
T200 /workspace/coverage/default/19.sram_ctrl_alert_test.1481732035 Apr 28 03:01:32 PM PDT 24 Apr 28 03:01:34 PM PDT 24 95867688 ps
T201 /workspace/coverage/default/26.sram_ctrl_executable.3031297926 Apr 28 03:02:29 PM PDT 24 Apr 28 03:04:42 PM PDT 24 559673255 ps
T202 /workspace/coverage/default/19.sram_ctrl_stress_all.2891530015 Apr 28 03:01:30 PM PDT 24 Apr 28 04:26:35 PM PDT 24 126406756067 ps
T203 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3162695534 Apr 28 03:06:31 PM PDT 24 Apr 28 03:07:06 PM PDT 24 8028143123 ps
T18 /workspace/coverage/default/4.sram_ctrl_sec_cm.2879475793 Apr 28 03:00:19 PM PDT 24 Apr 28 03:00:27 PM PDT 24 112062742 ps
T33 /workspace/coverage/default/24.sram_ctrl_ram_cfg.912636255 Apr 28 03:02:10 PM PDT 24 Apr 28 03:02:15 PM PDT 24 4203750987 ps
T34 /workspace/coverage/default/4.sram_ctrl_lc_escalation.2422392492 Apr 28 03:00:09 PM PDT 24 Apr 28 03:01:08 PM PDT 24 36400612739 ps
T35 /workspace/coverage/default/20.sram_ctrl_smoke.1880311827 Apr 28 03:01:30 PM PDT 24 Apr 28 03:01:58 PM PDT 24 1859782256 ps
T36 /workspace/coverage/default/33.sram_ctrl_smoke.16984877 Apr 28 03:03:38 PM PDT 24 Apr 28 03:03:49 PM PDT 24 4431260631 ps
T37 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2131276775 Apr 28 03:00:17 PM PDT 24 Apr 28 03:00:59 PM PDT 24 2937716731 ps
T38 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2926834470 Apr 28 03:00:10 PM PDT 24 Apr 28 03:00:39 PM PDT 24 5220342761 ps
T39 /workspace/coverage/default/9.sram_ctrl_alert_test.771932519 Apr 28 03:00:19 PM PDT 24 Apr 28 03:00:25 PM PDT 24 58785142 ps
T40 /workspace/coverage/default/44.sram_ctrl_lc_escalation.1410068103 Apr 28 03:06:08 PM PDT 24 Apr 28 03:07:14 PM PDT 24 9930359098 ps
T41 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1901614266 Apr 28 03:04:01 PM PDT 24 Apr 28 03:04:11 PM PDT 24 2871629709 ps
T204 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3331761361 Apr 28 03:05:30 PM PDT 24 Apr 28 03:08:48 PM PDT 24 5927479640 ps
T205 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.2241500360 Apr 28 03:02:25 PM PDT 24 Apr 28 03:08:02 PM PDT 24 21766132996 ps
T46 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1338080782 Apr 28 03:07:15 PM PDT 24 Apr 28 03:08:03 PM PDT 24 7439836180 ps
T206 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3081025103 Apr 28 03:04:33 PM PDT 24 Apr 28 03:06:51 PM PDT 24 4316896764 ps
T207 /workspace/coverage/default/26.sram_ctrl_partial_access.230623008 Apr 28 03:02:28 PM PDT 24 Apr 28 03:02:57 PM PDT 24 822393994 ps
T208 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2661169667 Apr 28 03:00:14 PM PDT 24 Apr 28 03:06:08 PM PDT 24 23624402947 ps
T209 /workspace/coverage/default/8.sram_ctrl_executable.2363422292 Apr 28 03:00:18 PM PDT 24 Apr 28 03:16:18 PM PDT 24 22284046869 ps
T210 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.732492126 Apr 28 03:05:45 PM PDT 24 Apr 28 03:37:26 PM PDT 24 20892650025 ps
T211 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3208241072 Apr 28 03:05:49 PM PDT 24 Apr 28 03:09:43 PM PDT 24 4120901924 ps
T212 /workspace/coverage/default/30.sram_ctrl_executable.387341514 Apr 28 03:03:12 PM PDT 24 Apr 28 03:09:49 PM PDT 24 18545301720 ps
T213 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2915963930 Apr 28 03:05:02 PM PDT 24 Apr 28 03:06:48 PM PDT 24 777380219 ps
T214 /workspace/coverage/default/37.sram_ctrl_multiple_keys.2592106711 Apr 28 03:04:26 PM PDT 24 Apr 28 03:06:10 PM PDT 24 3623874070 ps
T215 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1373662194 Apr 28 03:01:21 PM PDT 24 Apr 28 03:06:24 PM PDT 24 4438951656 ps
T216 /workspace/coverage/default/48.sram_ctrl_smoke.2672844252 Apr 28 03:06:53 PM PDT 24 Apr 28 03:07:33 PM PDT 24 3151120866 ps
T217 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3967618817 Apr 28 03:02:28 PM PDT 24 Apr 28 03:04:07 PM PDT 24 810167258 ps
T218 /workspace/coverage/default/1.sram_ctrl_bijection.851609382 Apr 28 03:00:04 PM PDT 24 Apr 28 03:27:15 PM PDT 24 153780231799 ps
T219 /workspace/coverage/default/29.sram_ctrl_alert_test.786090455 Apr 28 03:03:03 PM PDT 24 Apr 28 03:03:04 PM PDT 24 38134962 ps
T220 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3722162346 Apr 28 03:00:05 PM PDT 24 Apr 28 03:00:57 PM PDT 24 828612333 ps
T221 /workspace/coverage/default/9.sram_ctrl_mem_walk.1270879814 Apr 28 03:00:17 PM PDT 24 Apr 28 03:02:49 PM PDT 24 41267129942 ps
T222 /workspace/coverage/default/17.sram_ctrl_executable.1167455809 Apr 28 03:01:12 PM PDT 24 Apr 28 03:09:19 PM PDT 24 16989603159 ps
T223 /workspace/coverage/default/39.sram_ctrl_lc_escalation.214193751 Apr 28 03:05:04 PM PDT 24 Apr 28 03:06:16 PM PDT 24 48261604207 ps
T136 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1223816506 Apr 28 03:00:40 PM PDT 24 Apr 28 03:06:49 PM PDT 24 18802445774 ps
T224 /workspace/coverage/default/40.sram_ctrl_ram_cfg.1757985080 Apr 28 03:05:26 PM PDT 24 Apr 28 03:05:30 PM PDT 24 1353132804 ps
T123 /workspace/coverage/default/14.sram_ctrl_stress_all.766492704 Apr 28 03:00:54 PM PDT 24 Apr 28 04:05:43 PM PDT 24 79366723626 ps
T225 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.754632181 Apr 28 03:02:06 PM PDT 24 Apr 28 03:08:21 PM PDT 24 26324944089 ps
T47 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1543479270 Apr 28 03:00:02 PM PDT 24 Apr 28 03:00:30 PM PDT 24 773031520 ps
T48 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.347359337 Apr 28 02:59:49 PM PDT 24 Apr 28 03:00:52 PM PDT 24 1067786148 ps
T226 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3570106176 Apr 28 03:02:47 PM PDT 24 Apr 28 03:06:50 PM PDT 24 3725983321 ps
T227 /workspace/coverage/default/28.sram_ctrl_bijection.1007784305 Apr 28 03:02:45 PM PDT 24 Apr 28 03:33:16 PM PDT 24 170209729690 ps
T228 /workspace/coverage/default/6.sram_ctrl_regwen.3189366573 Apr 28 03:00:16 PM PDT 24 Apr 28 03:17:47 PM PDT 24 10484046794 ps
T134 /workspace/coverage/default/0.sram_ctrl_stress_all.655226757 Apr 28 03:00:00 PM PDT 24 Apr 28 03:12:05 PM PDT 24 20357768530 ps
T229 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.452751126 Apr 28 02:59:56 PM PDT 24 Apr 28 03:14:03 PM PDT 24 47152546626 ps
T230 /workspace/coverage/default/29.sram_ctrl_partial_access.1265191009 Apr 28 03:02:55 PM PDT 24 Apr 28 03:03:14 PM PDT 24 755935675 ps
T231 /workspace/coverage/default/48.sram_ctrl_mem_walk.1732000312 Apr 28 03:07:00 PM PDT 24 Apr 28 03:10:02 PM PDT 24 93863829595 ps
T232 /workspace/coverage/default/19.sram_ctrl_bijection.1317120957 Apr 28 03:01:19 PM PDT 24 Apr 28 03:09:01 PM PDT 24 20270885705 ps
T233 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2388713145 Apr 28 03:04:59 PM PDT 24 Apr 28 03:06:25 PM PDT 24 4089153975 ps
T234 /workspace/coverage/default/35.sram_ctrl_multiple_keys.1690659931 Apr 28 03:04:12 PM PDT 24 Apr 28 03:21:59 PM PDT 24 90859915975 ps
T235 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3999874904 Apr 28 03:03:17 PM PDT 24 Apr 28 03:03:51 PM PDT 24 734205909 ps
T236 /workspace/coverage/default/2.sram_ctrl_multiple_keys.3288309601 Apr 28 03:00:02 PM PDT 24 Apr 28 03:06:47 PM PDT 24 7729245944 ps
T237 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.641921915 Apr 28 03:01:15 PM PDT 24 Apr 28 03:04:51 PM PDT 24 12054074765 ps
T238 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2422634535 Apr 28 03:01:57 PM PDT 24 Apr 28 03:03:28 PM PDT 24 788520444 ps
T239 /workspace/coverage/default/6.sram_ctrl_multiple_keys.600224607 Apr 28 03:00:13 PM PDT 24 Apr 28 03:03:38 PM PDT 24 17405285423 ps
T240 /workspace/coverage/default/46.sram_ctrl_executable.3681550533 Apr 28 03:06:38 PM PDT 24 Apr 28 03:17:09 PM PDT 24 90038658225 ps
T241 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.3883027777 Apr 28 03:05:48 PM PDT 24 Apr 28 03:07:08 PM PDT 24 8996710579 ps
T242 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3388121722 Apr 28 03:05:08 PM PDT 24 Apr 28 03:07:41 PM PDT 24 18215643068 ps
T243 /workspace/coverage/default/5.sram_ctrl_lc_escalation.146893037 Apr 28 03:00:11 PM PDT 24 Apr 28 03:00:56 PM PDT 24 29390548389 ps
T244 /workspace/coverage/default/42.sram_ctrl_alert_test.2596899441 Apr 28 03:05:48 PM PDT 24 Apr 28 03:05:50 PM PDT 24 25296609 ps
T245 /workspace/coverage/default/43.sram_ctrl_max_throughput.4256645956 Apr 28 03:05:51 PM PDT 24 Apr 28 03:06:45 PM PDT 24 3042759058 ps
T246 /workspace/coverage/default/42.sram_ctrl_bijection.1670086042 Apr 28 03:05:45 PM PDT 24 Apr 28 03:19:24 PM PDT 24 50567735251 ps
T247 /workspace/coverage/default/34.sram_ctrl_ram_cfg.192574971 Apr 28 03:04:05 PM PDT 24 Apr 28 03:04:09 PM PDT 24 665800047 ps
T248 /workspace/coverage/default/20.sram_ctrl_ram_cfg.3228064400 Apr 28 03:01:35 PM PDT 24 Apr 28 03:01:40 PM PDT 24 1365378071 ps
T49 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1740524534 Apr 28 03:04:53 PM PDT 24 Apr 28 03:06:21 PM PDT 24 2263235804 ps
T249 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3301378408 Apr 28 03:00:39 PM PDT 24 Apr 28 03:01:55 PM PDT 24 3091215116 ps
T250 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2384471091 Apr 28 03:00:17 PM PDT 24 Apr 28 03:02:36 PM PDT 24 2363658386 ps
T251 /workspace/coverage/default/6.sram_ctrl_lc_escalation.1261413572 Apr 28 03:00:16 PM PDT 24 Apr 28 03:01:28 PM PDT 24 91806125364 ps
T252 /workspace/coverage/default/41.sram_ctrl_partial_access.771535557 Apr 28 03:05:29 PM PDT 24 Apr 28 03:07:30 PM PDT 24 1860907748 ps
T253 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2766995169 Apr 28 03:00:21 PM PDT 24 Apr 28 03:06:34 PM PDT 24 5966506853 ps
T254 /workspace/coverage/default/1.sram_ctrl_smoke.1814142252 Apr 28 02:59:54 PM PDT 24 Apr 28 03:00:05 PM PDT 24 805035812 ps
T255 /workspace/coverage/default/45.sram_ctrl_stress_all.2879457662 Apr 28 03:06:21 PM PDT 24 Apr 28 03:56:06 PM PDT 24 362597898934 ps
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T257 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1790241076 Apr 28 03:02:56 PM PDT 24 Apr 28 03:06:33 PM PDT 24 5111031214 ps
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T259 /workspace/coverage/default/13.sram_ctrl_lc_escalation.1468674877 Apr 28 03:00:39 PM PDT 24 Apr 28 03:01:07 PM PDT 24 18893805183 ps
T260 /workspace/coverage/default/10.sram_ctrl_max_throughput.3250202886 Apr 28 03:00:18 PM PDT 24 Apr 28 03:00:31 PM PDT 24 6739646260 ps
T104 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3467078558 Apr 28 03:01:54 PM PDT 24 Apr 28 03:02:10 PM PDT 24 1967777516 ps
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T105 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3513774653 Apr 28 03:02:34 PM PDT 24 Apr 28 03:02:48 PM PDT 24 1923917865 ps
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T294 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.808806008 Apr 28 03:00:26 PM PDT 24 Apr 28 03:07:49 PM PDT 24 6391447508 ps
T295 /workspace/coverage/default/43.sram_ctrl_regwen.1397450833 Apr 28 03:05:52 PM PDT 24 Apr 28 03:17:34 PM PDT 24 25741326334 ps
T296 /workspace/coverage/default/20.sram_ctrl_executable.2325845262 Apr 28 03:01:37 PM PDT 24 Apr 28 03:16:23 PM PDT 24 19008803578 ps
T297 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.3072364843 Apr 28 03:03:50 PM PDT 24 Apr 28 03:19:15 PM PDT 24 10425838055 ps
T298 /workspace/coverage/default/1.sram_ctrl_lc_escalation.3282320899 Apr 28 03:00:02 PM PDT 24 Apr 28 03:01:12 PM PDT 24 14568032380 ps
T299 /workspace/coverage/default/26.sram_ctrl_multiple_keys.1053350725 Apr 28 03:02:32 PM PDT 24 Apr 28 03:15:27 PM PDT 24 9437740041 ps
T300 /workspace/coverage/default/13.sram_ctrl_executable.453577983 Apr 28 03:00:43 PM PDT 24 Apr 28 03:35:10 PM PDT 24 140930791390 ps
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T304 /workspace/coverage/default/28.sram_ctrl_max_throughput.399719571 Apr 28 03:02:51 PM PDT 24 Apr 28 03:03:17 PM PDT 24 1426770995 ps
T305 /workspace/coverage/default/41.sram_ctrl_alert_test.1668363221 Apr 28 03:05:36 PM PDT 24 Apr 28 03:05:37 PM PDT 24 46279194 ps
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