Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv



Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00
Crosses 10 0 10 100.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
subword_granularity_cp 5 0 5 100.00 100 1 1 0
subword_we_cp 2 0 2 100.00 100 1 1 2


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
subword_access 10 0 10 100.00 100 1 1 0


Summary for Variable subword_granularity_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for subword_granularity_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ill_access 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
word_access 151359318 1 T1 117324 T2 311 T3 22
triple_byte_access 2770403 1 T1 2373 T2 324 T5 1783
halfword_access 4249913 1 T1 3526 T2 428 T5 2867
byte_access 5955177 1 T1 4710 T2 564 T5 3706
zero_access 1815970 1 T1 1187 T2 130 T5 920



Summary for Variable subword_we_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for subword_we_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 82845383 1 T1 64258 T2 894 T5 51121
auto[1] 83305398 1 T1 64862 T2 863 T3 22



Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for subword_access

Bins
subword_we_cpsubword_granularity_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] word_access 75310910 1 T1 58384 T2 168 T5 46473
auto[0] triple_byte_access 1318203 1 T1 1173 T2 181 T5 930
auto[0] halfword_access 2071889 1 T1 1721 T2 201 T5 1421
auto[0] byte_access 3053210 1 T1 2367 T2 281 T5 1834
auto[0] zero_access 1091171 1 T1 613 T2 63 T5 463
auto[1] word_access 76048408 1 T1 58940 T2 143 T3 22
auto[1] triple_byte_access 1452200 1 T1 1200 T2 143 T5 853
auto[1] halfword_access 2178024 1 T1 1805 T2 227 T5 1446
auto[1] byte_access 2901967 1 T1 2343 T2 283 T5 1872
auto[1] zero_access 724799 1 T1 574 T2 67 T5 457

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%