Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	344264144	1			T2	312862		T4	11972		T6	10404
instr_valid_dis	295713267	1			T2	312862		T4	11972		T6	10404
instr_en	31974770	1			T11	59642		T20	51148		T34	242538

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12639688	1			T20	32248		T34	33188		T133	235400
sram_ifetch_valid_disable	299869107	1			T2	312862		T4	11972		T6	10404
sram_ifetch_enable	31755349	1			T11	34482		T20	67274		T21	106216

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	344264144	1			T2	312862		T4	11972		T6	10404
hw_debug_en_valid_off	296092107	1			T2	312862		T4	11972		T6	10404
hw_debug_en_on	32828211	1			T11	74148		T20	262150		T21	68136

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	299869107	1			T2	312862		T4	11972		T6	10404
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	281236931	1			T2	312862		T4	11972		T6	10404
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13120221	1			T11	33990		T20	40512		T34	153042
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5880902	1			T34	33188		T133	41796		T65	18864
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2855918	1			T65	9828		T137	12520		T143	50
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2149092	1			T34	33188		T133	41796		T65	9036
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4616776	1			T133	98938		T65	37764		T49	65834
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1878396	1			T133	84770		T65	37764		T50	18704
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1886162	1			T133	14168		T62	11522		T138	5066
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	12655158	1			T11	48496		T20	242150		T21	45658
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6693788	1			T20	199092		T21	45658		T133	17166
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2854680	1			T11	33990		T20	15708		T34	38300

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13996903	1			T11	25652		T20	10636		T34	56308
lc_exec_en	15556277	1			T11	25652		T20	20000		T21	22478
valid_exec_dis	288071253	1			T2	312862		T4	11972		T6	10404
invalid_exec_dis	44395037	1			T11	34482		T20	99522		T21	106216