Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52


Total tests in report: 1038
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
84.14 84.14 97.75 97.75 74.42 74.42 84.80 84.80 100.00 100.00 91.55 91.55 94.80 94.80 45.64 45.64 /workspace/coverage/default/47.sram_ctrl_lc_escalation.1780184297
90.39 6.25 98.78 1.03 80.91 6.49 86.58 1.78 100.00 0.00 93.52 1.97 96.14 1.34 76.81 31.17 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2355545277
93.54 3.15 98.88 0.09 86.36 5.45 98.08 11.51 100.00 0.00 94.65 1.13 96.29 0.15 80.52 3.71 /workspace/coverage/default/20.sram_ctrl_executable.2458480485
95.13 1.59 99.06 0.19 90.26 3.90 98.22 0.14 100.00 0.00 96.90 2.25 96.29 0.00 85.16 4.64 /workspace/coverage/default/42.sram_ctrl_stress_all.1503616108
96.18 1.05 99.25 0.19 91.17 0.91 98.44 0.21 100.00 0.00 97.75 0.85 96.29 0.00 90.35 5.19 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.86986035
96.79 0.61 99.44 0.19 93.12 1.95 98.79 0.36 100.00 0.00 98.59 0.85 96.88 0.59 90.72 0.37 /workspace/coverage/default/0.sram_ctrl_sec_cm.2392424188
97.22 0.42 99.44 0.00 93.12 0.00 98.79 0.00 100.00 0.00 98.59 0.00 96.88 0.00 93.69 2.97 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1092838436
97.60 0.38 99.72 0.28 93.25 0.13 98.79 0.00 100.00 0.00 98.87 0.28 97.92 1.04 94.62 0.93 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3707057352
97.80 0.20 99.72 0.00 93.25 0.00 98.86 0.07 100.00 0.00 98.87 0.00 99.26 1.34 94.62 0.00 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2032075758
97.99 0.20 99.72 0.00 93.64 0.39 99.29 0.43 100.00 0.00 98.87 0.00 99.26 0.00 95.18 0.56 /workspace/coverage/default/0.sram_ctrl_alert_test.3377040867
98.16 0.17 99.72 0.00 93.90 0.26 99.29 0.00 100.00 0.00 98.87 0.00 99.26 0.00 96.10 0.93 /workspace/coverage/default/49.sram_ctrl_stress_all.150183846
98.30 0.14 99.72 0.00 94.03 0.13 99.29 0.00 100.00 0.00 98.87 0.00 99.70 0.45 96.47 0.37 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1893021151
98.41 0.11 99.81 0.09 94.03 0.00 100.00 0.71 100.00 0.00 98.87 0.00 99.70 0.00 96.47 0.00 /workspace/coverage/default/16.sram_ctrl_ram_cfg.921365556
98.52 0.11 99.81 0.00 94.03 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.00 97.22 0.74 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.133887131
98.60 0.08 99.81 0.00 94.03 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.00 97.77 0.56 /workspace/coverage/default/0.sram_ctrl_regwen.3518929199
98.65 0.05 99.81 0.00 94.03 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.00 98.14 0.37 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.639086741
98.70 0.05 99.81 0.00 94.16 0.13 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.00 98.33 0.19 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.883996416
98.72 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.00 98.52 0.19 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2691939442

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.340216776
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3241456872
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2396192579
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3748444343
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2015067467
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.402590811
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1143148861
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3460240255
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1242041019
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.395594071
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.943565667
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2678346458
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3057037328
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.358634662
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3316076568
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3308417542
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2847835318
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.551291085
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.157170720
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1926032260
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2598889256
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1635277733
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3641873463
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2678292186
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2214299985
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1499260709
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2255842627
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.673203634
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1814090509
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.923147571
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.410002557
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1920675506
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.337194802
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3784456615
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2613970170
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3436966797
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1317586355
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4268988792
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.829161931
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4202936753
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1028828945
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3528679864
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1926114924
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2207387002
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3615704387
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2845285214
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2193038418
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2660664497
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2933872052
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1249114371
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3955544553
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3693482502
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1720891939
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1771981889
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2173003301
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3987658086
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3942783724
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2442502629
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1179299663
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4158624046
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1384733837
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.661479120
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3660731094
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.160689012
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3898599344
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1147966909
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.343896228
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.846621187
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3901528710
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2260671548
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.291331824
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1788679038
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3890341816
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.202007498
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3348367164
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2229872409
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2183612209
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.614981536
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3422628363
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3365000054
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2724960075
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3096942157
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1727284099
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1462725623
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1775708546
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.935172324
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1951510333
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3658447
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1819750282
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2694685442
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.305430148
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2092959455
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3272757335
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3233161811
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.250925931
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4204459701
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2799621286
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1250912383
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.631951347
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.29466331
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1596550113
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3912577639
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3820201155
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2882508981
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2967281664
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2987672060
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.716713598
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3454669252
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1943861571
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1730979328
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.62124167
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1376776858
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1550869587
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.631468303
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1275318227
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4289395285
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.985489752
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2502216131
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.572724072
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1328915368
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3675060406
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2738898920
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.894844475
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4242399037
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.356569607
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2866719570
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3278893219
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1365266329
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.979109993
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1256844497
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.170449935
/workspace/coverage/default/0.sram_ctrl_bijection.3679364085
/workspace/coverage/default/0.sram_ctrl_executable.3657053284
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2529282267
/workspace/coverage/default/0.sram_ctrl_max_throughput.915946046
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1422711810
/workspace/coverage/default/0.sram_ctrl_mem_walk.1414315806
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2860245456
/workspace/coverage/default/0.sram_ctrl_partial_access.2280330981
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3851541966
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3249755965
/workspace/coverage/default/0.sram_ctrl_smoke.476103627
/workspace/coverage/default/0.sram_ctrl_stress_all.3253708572
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.890455271
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2228665749
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1069479077
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.185441680
/workspace/coverage/default/1.sram_ctrl_alert_test.2742101464
/workspace/coverage/default/1.sram_ctrl_bijection.53796674
/workspace/coverage/default/1.sram_ctrl_executable.2987684637
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2022904728
/workspace/coverage/default/1.sram_ctrl_max_throughput.3620242333
/workspace/coverage/default/1.sram_ctrl_mem_walk.4292328513
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2585290996
/workspace/coverage/default/1.sram_ctrl_partial_access.352557652
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4039029347
/workspace/coverage/default/1.sram_ctrl_ram_cfg.316220650
/workspace/coverage/default/1.sram_ctrl_regwen.339522436
/workspace/coverage/default/1.sram_ctrl_sec_cm.555769533
/workspace/coverage/default/1.sram_ctrl_smoke.4129078852
/workspace/coverage/default/1.sram_ctrl_stress_all.3140260385
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3166277546
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.490362488
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.59602094
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3557865475
/workspace/coverage/default/10.sram_ctrl_alert_test.1567272223
/workspace/coverage/default/10.sram_ctrl_bijection.3964844865
/workspace/coverage/default/10.sram_ctrl_executable.3367516840
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3025603521
/workspace/coverage/default/10.sram_ctrl_max_throughput.3444163581
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1073440704
/workspace/coverage/default/10.sram_ctrl_mem_walk.3560649807
/workspace/coverage/default/10.sram_ctrl_multiple_keys.4288179306
/workspace/coverage/default/10.sram_ctrl_partial_access.3886839661
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1605037061
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2279208937
/workspace/coverage/default/10.sram_ctrl_regwen.2954117721
/workspace/coverage/default/10.sram_ctrl_smoke.2565713555
/workspace/coverage/default/10.sram_ctrl_stress_all.1143270646
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1302317838
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.499205870
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3706789403
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3858433319
/workspace/coverage/default/11.sram_ctrl_alert_test.1584263201
/workspace/coverage/default/11.sram_ctrl_bijection.1375358378
/workspace/coverage/default/11.sram_ctrl_executable.869039585
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1028347321
/workspace/coverage/default/11.sram_ctrl_max_throughput.2578172432
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3411641749
/workspace/coverage/default/11.sram_ctrl_mem_walk.1071177222
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3039685220
/workspace/coverage/default/11.sram_ctrl_partial_access.2681030053
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1464657012
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1623662190
/workspace/coverage/default/11.sram_ctrl_regwen.1274076446
/workspace/coverage/default/11.sram_ctrl_smoke.363999327
/workspace/coverage/default/11.sram_ctrl_stress_all.1779420434
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.130823336
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1173157969
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2616322323
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2660011150
/workspace/coverage/default/12.sram_ctrl_alert_test.1814530916
/workspace/coverage/default/12.sram_ctrl_bijection.1080726767
/workspace/coverage/default/12.sram_ctrl_executable.4096714715
/workspace/coverage/default/12.sram_ctrl_lc_escalation.670866679
/workspace/coverage/default/12.sram_ctrl_max_throughput.2247778978
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.1627217534
/workspace/coverage/default/12.sram_ctrl_mem_walk.487562135
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/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3811330757
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3122588704
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3049792247
/workspace/coverage/default/43.sram_ctrl_alert_test.591578834
/workspace/coverage/default/43.sram_ctrl_bijection.894495913
/workspace/coverage/default/43.sram_ctrl_executable.343515818
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3250854668
/workspace/coverage/default/43.sram_ctrl_max_throughput.2862627533
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.171546934
/workspace/coverage/default/43.sram_ctrl_mem_walk.4012854219
/workspace/coverage/default/43.sram_ctrl_multiple_keys.682295657
/workspace/coverage/default/43.sram_ctrl_partial_access.1707502905
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.43512251
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2588018319
/workspace/coverage/default/43.sram_ctrl_regwen.3000457601
/workspace/coverage/default/43.sram_ctrl_smoke.1109847617
/workspace/coverage/default/43.sram_ctrl_stress_all.1517179809
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2324190217
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2789099198
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1299922032
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3909597099
/workspace/coverage/default/44.sram_ctrl_alert_test.950005141
/workspace/coverage/default/44.sram_ctrl_bijection.412983955
/workspace/coverage/default/44.sram_ctrl_executable.4253045733
/workspace/coverage/default/44.sram_ctrl_lc_escalation.162780013
/workspace/coverage/default/44.sram_ctrl_max_throughput.2457919922
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.160943917
/workspace/coverage/default/44.sram_ctrl_mem_walk.3433540288
/workspace/coverage/default/44.sram_ctrl_multiple_keys.925935155
/workspace/coverage/default/44.sram_ctrl_partial_access.4166083482
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2010673569
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1324353247
/workspace/coverage/default/44.sram_ctrl_regwen.1846481380
/workspace/coverage/default/44.sram_ctrl_smoke.3226408407
/workspace/coverage/default/44.sram_ctrl_stress_all.3170462644
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1702191779
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.161836290
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1951176823
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1771942372
/workspace/coverage/default/45.sram_ctrl_alert_test.2248271923
/workspace/coverage/default/45.sram_ctrl_bijection.2780481031
/workspace/coverage/default/45.sram_ctrl_executable.2711503466
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3681508718
/workspace/coverage/default/45.sram_ctrl_max_throughput.3598874872
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2985445894
/workspace/coverage/default/45.sram_ctrl_mem_walk.1167530074
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2777604661
/workspace/coverage/default/45.sram_ctrl_partial_access.3399660261
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1365683695
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2279336890
/workspace/coverage/default/45.sram_ctrl_regwen.1440776866
/workspace/coverage/default/45.sram_ctrl_smoke.1414346480
/workspace/coverage/default/45.sram_ctrl_stress_all.362910534
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2184055510
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3901843146
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3294151838
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1118589510
/workspace/coverage/default/46.sram_ctrl_alert_test.2702661903
/workspace/coverage/default/46.sram_ctrl_bijection.1165446224
/workspace/coverage/default/46.sram_ctrl_executable.185478895
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1621121517
/workspace/coverage/default/46.sram_ctrl_max_throughput.3841050658
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2930440032
/workspace/coverage/default/46.sram_ctrl_mem_walk.770677613
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1394555145
/workspace/coverage/default/46.sram_ctrl_partial_access.3120106686
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1683669793
/workspace/coverage/default/46.sram_ctrl_ram_cfg.475737451
/workspace/coverage/default/46.sram_ctrl_regwen.2336263585
/workspace/coverage/default/46.sram_ctrl_smoke.1559161827
/workspace/coverage/default/46.sram_ctrl_stress_all.2759292325
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1855364640
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1736564062
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1017556705
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.333566192
/workspace/coverage/default/47.sram_ctrl_alert_test.180192372
/workspace/coverage/default/47.sram_ctrl_bijection.765132453
/workspace/coverage/default/47.sram_ctrl_executable.642631621
/workspace/coverage/default/47.sram_ctrl_max_throughput.1770062443
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.4183014736
/workspace/coverage/default/47.sram_ctrl_mem_walk.2250945537
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3881464691
/workspace/coverage/default/47.sram_ctrl_partial_access.2079814627
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2573301302
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3357546083
/workspace/coverage/default/47.sram_ctrl_regwen.1835185322
/workspace/coverage/default/47.sram_ctrl_smoke.859284993
/workspace/coverage/default/47.sram_ctrl_stress_all.107362631
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2770536889
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1468810186
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2544031668
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3327008505
/workspace/coverage/default/48.sram_ctrl_alert_test.2343339197
/workspace/coverage/default/48.sram_ctrl_bijection.1558412595
/workspace/coverage/default/48.sram_ctrl_executable.669819055
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1519091298
/workspace/coverage/default/48.sram_ctrl_max_throughput.2927603168
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2415798202
/workspace/coverage/default/48.sram_ctrl_mem_walk.3023287678
/workspace/coverage/default/48.sram_ctrl_multiple_keys.677251124
/workspace/coverage/default/48.sram_ctrl_partial_access.2257718231
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3830395717
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3226684238
/workspace/coverage/default/48.sram_ctrl_regwen.3641086912
/workspace/coverage/default/48.sram_ctrl_smoke.1842636240
/workspace/coverage/default/48.sram_ctrl_stress_all.1060789520
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.884153992
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.837036233
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3473934330
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1398684171
/workspace/coverage/default/49.sram_ctrl_alert_test.1086583432
/workspace/coverage/default/49.sram_ctrl_bijection.4195060373
/workspace/coverage/default/49.sram_ctrl_executable.410814758
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1538981388
/workspace/coverage/default/49.sram_ctrl_max_throughput.4266319670
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.4238884189
/workspace/coverage/default/49.sram_ctrl_mem_walk.2770182211
/workspace/coverage/default/49.sram_ctrl_multiple_keys.4168127013
/workspace/coverage/default/49.sram_ctrl_partial_access.3669336346
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.553816158
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2191268079
/workspace/coverage/default/49.sram_ctrl_regwen.2147784043
/workspace/coverage/default/49.sram_ctrl_smoke.3153358772
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2943123765
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2677582313
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.835609247
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3739360596
/workspace/coverage/default/5.sram_ctrl_alert_test.3740985927
/workspace/coverage/default/5.sram_ctrl_bijection.1359106161
/workspace/coverage/default/5.sram_ctrl_executable.404638081
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1528854738
/workspace/coverage/default/5.sram_ctrl_max_throughput.261523371
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2281617229
/workspace/coverage/default/5.sram_ctrl_mem_walk.1121195740
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1100778373
/workspace/coverage/default/5.sram_ctrl_partial_access.2525428456
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2262908064
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1087783691
/workspace/coverage/default/5.sram_ctrl_regwen.57823135
/workspace/coverage/default/5.sram_ctrl_smoke.3399798698
/workspace/coverage/default/5.sram_ctrl_stress_all.2692590471
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3639869569
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1328196434
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.354738558
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1558833616
/workspace/coverage/default/6.sram_ctrl_alert_test.2584999191
/workspace/coverage/default/6.sram_ctrl_bijection.1361749921
/workspace/coverage/default/6.sram_ctrl_executable.2072657603
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3867425396
/workspace/coverage/default/6.sram_ctrl_max_throughput.4157623786
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1462275295
/workspace/coverage/default/6.sram_ctrl_mem_walk.3431390936
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3492203776
/workspace/coverage/default/6.sram_ctrl_partial_access.2480731415
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1120305180
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1634001627
/workspace/coverage/default/6.sram_ctrl_regwen.2034024131
/workspace/coverage/default/6.sram_ctrl_smoke.504305593
/workspace/coverage/default/6.sram_ctrl_stress_all.574423700
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3491676219
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2140672993
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1195221972
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.888696581
/workspace/coverage/default/7.sram_ctrl_alert_test.3804282091
/workspace/coverage/default/7.sram_ctrl_bijection.1499168806
/workspace/coverage/default/7.sram_ctrl_executable.3507025370
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3626992427
/workspace/coverage/default/7.sram_ctrl_max_throughput.172164630
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3758805116
/workspace/coverage/default/7.sram_ctrl_mem_walk.2100620086
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3700502123
/workspace/coverage/default/7.sram_ctrl_partial_access.1813524930
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.66819794
/workspace/coverage/default/7.sram_ctrl_ram_cfg.868547574
/workspace/coverage/default/7.sram_ctrl_regwen.958411114
/workspace/coverage/default/7.sram_ctrl_smoke.2077241831
/workspace/coverage/default/7.sram_ctrl_stress_all.2810828772
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2078427595
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.21347722
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2520774500
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2591293851
/workspace/coverage/default/8.sram_ctrl_alert_test.1839032395
/workspace/coverage/default/8.sram_ctrl_bijection.4023708384
/workspace/coverage/default/8.sram_ctrl_executable.3913015843
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1479494287
/workspace/coverage/default/8.sram_ctrl_max_throughput.240586533
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.4027086241
/workspace/coverage/default/8.sram_ctrl_mem_walk.506261569
/workspace/coverage/default/8.sram_ctrl_multiple_keys.720483127
/workspace/coverage/default/8.sram_ctrl_partial_access.3105091413
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2082983738
/workspace/coverage/default/8.sram_ctrl_ram_cfg.898931659
/workspace/coverage/default/8.sram_ctrl_regwen.1196979150
/workspace/coverage/default/8.sram_ctrl_smoke.4100279389
/workspace/coverage/default/8.sram_ctrl_stress_all.3320189952
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3702445933
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3459602245
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3871911145
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2778473488
/workspace/coverage/default/9.sram_ctrl_alert_test.2010448327
/workspace/coverage/default/9.sram_ctrl_bijection.878952493
/workspace/coverage/default/9.sram_ctrl_executable.399171266
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1395242562
/workspace/coverage/default/9.sram_ctrl_max_throughput.903214326
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.423228894
/workspace/coverage/default/9.sram_ctrl_mem_walk.1319771728
/workspace/coverage/default/9.sram_ctrl_partial_access.1442330151
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1603983863
/workspace/coverage/default/9.sram_ctrl_ram_cfg.520827644
/workspace/coverage/default/9.sram_ctrl_regwen.1114428022
/workspace/coverage/default/9.sram_ctrl_smoke.249133141
/workspace/coverage/default/9.sram_ctrl_stress_all.4196789944
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2212744792
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1107572566
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2521921519



Total test records in report: 1038
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/2.sram_ctrl_alert_test.790850874 Apr 30 01:11:20 PM PDT 24 Apr 30 01:11:21 PM PDT 24 34394921 ps
T2 /workspace/coverage/default/40.sram_ctrl_multiple_keys.123956270 Apr 30 01:25:41 PM PDT 24 Apr 30 01:42:50 PM PDT 24 28911020978 ps
T3 /workspace/coverage/default/34.sram_ctrl_alert_test.420495820 Apr 30 01:23:52 PM PDT 24 Apr 30 01:23:53 PM PDT 24 41843881 ps
T4 /workspace/coverage/default/27.sram_ctrl_partial_access.128206630 Apr 30 01:20:56 PM PDT 24 Apr 30 01:21:14 PM PDT 24 2600562582 ps
T6 /workspace/coverage/default/0.sram_ctrl_max_throughput.915946046 Apr 30 01:11:03 PM PDT 24 Apr 30 01:11:37 PM PDT 24 2897350540 ps
T10 /workspace/coverage/default/35.sram_ctrl_ram_cfg.2913700258 Apr 30 01:24:04 PM PDT 24 Apr 30 01:24:09 PM PDT 24 1346515334 ps
T5 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1422711810 Apr 30 01:11:03 PM PDT 24 Apr 30 01:12:20 PM PDT 24 4813866518 ps
T7 /workspace/coverage/default/47.sram_ctrl_lc_escalation.1780184297 Apr 30 01:28:06 PM PDT 24 Apr 30 01:29:12 PM PDT 24 19129147677 ps
T11 /workspace/coverage/default/5.sram_ctrl_regwen.57823135 Apr 30 01:11:43 PM PDT 24 Apr 30 01:17:52 PM PDT 24 3507984133 ps
T12 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3294151838 Apr 30 01:27:28 PM PDT 24 Apr 30 01:28:26 PM PDT 24 1002755460 ps
T15 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3707057352 Apr 30 01:11:11 PM PDT 24 Apr 30 01:12:14 PM PDT 24 3775548887 ps
T16 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.883996416 Apr 30 01:25:01 PM PDT 24 Apr 30 01:38:09 PM PDT 24 11145806287 ps
T17 /workspace/coverage/default/16.sram_ctrl_partial_access.3756674796 Apr 30 01:16:15 PM PDT 24 Apr 30 01:16:37 PM PDT 24 1330954196 ps
T18 /workspace/coverage/default/12.sram_ctrl_stress_all.1470895668 Apr 30 01:14:54 PM PDT 24 Apr 30 03:37:16 PM PDT 24 426563341579 ps
T19 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.3557865475 Apr 30 01:13:47 PM PDT 24 Apr 30 01:23:33 PM PDT 24 16513483364 ps
T35 /workspace/coverage/default/29.sram_ctrl_ram_cfg.770787548 Apr 30 01:21:50 PM PDT 24 Apr 30 01:21:54 PM PDT 24 345404008 ps
T22 /workspace/coverage/default/46.sram_ctrl_multiple_keys.1394555145 Apr 30 01:27:40 PM PDT 24 Apr 30 01:41:03 PM PDT 24 65898899423 ps
T8 /workspace/coverage/default/38.sram_ctrl_lc_escalation.329420380 Apr 30 01:24:59 PM PDT 24 Apr 30 01:26:30 PM PDT 24 67877642009 ps
T97 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.837036233 Apr 30 01:28:21 PM PDT 24 Apr 30 01:33:18 PM PDT 24 17333126365 ps
T76 /workspace/coverage/default/20.sram_ctrl_partial_access.2612586280 Apr 30 01:17:48 PM PDT 24 Apr 30 01:17:54 PM PDT 24 1351449937 ps
T77 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2843151770 Apr 30 01:11:23 PM PDT 24 Apr 30 01:14:46 PM PDT 24 2517838779 ps
T20 /workspace/coverage/default/20.sram_ctrl_executable.2458480485 Apr 30 01:17:55 PM PDT 24 Apr 30 01:32:33 PM PDT 24 34845485174 ps
T26 /workspace/coverage/default/38.sram_ctrl_alert_test.1553141930 Apr 30 01:25:13 PM PDT 24 Apr 30 01:25:14 PM PDT 24 43264250 ps
T153 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3587502573 Apr 30 01:22:54 PM PDT 24 Apr 30 01:23:18 PM PDT 24 762214287 ps
T154 /workspace/coverage/default/5.sram_ctrl_smoke.3399798698 Apr 30 01:11:47 PM PDT 24 Apr 30 01:12:01 PM PDT 24 784492136 ps
T78 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2759410491 Apr 30 01:19:08 PM PDT 24 Apr 30 01:22:09 PM PDT 24 5507474931 ps
T21 /workspace/coverage/default/30.sram_ctrl_stress_all.1238157521 Apr 30 01:22:23 PM PDT 24 Apr 30 02:46:02 PM PDT 24 81185191866 ps
T34 /workspace/coverage/default/39.sram_ctrl_regwen.3035637902 Apr 30 01:25:28 PM PDT 24 Apr 30 01:45:14 PM PDT 24 12946034808 ps
T102 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2109982229 Apr 30 01:15:00 PM PDT 24 Apr 30 01:17:44 PM PDT 24 9608798259 ps
T13 /workspace/coverage/default/36.sram_ctrl_multiple_keys.4195336602 Apr 30 01:24:09 PM PDT 24 Apr 30 01:41:05 PM PDT 24 42684240946 ps
T133 /workspace/coverage/default/8.sram_ctrl_executable.3913015843 Apr 30 01:12:44 PM PDT 24 Apr 30 01:30:07 PM PDT 24 70758466898 ps
T149 /workspace/coverage/default/25.sram_ctrl_bijection.3746690234 Apr 30 01:20:04 PM PDT 24 Apr 30 01:32:28 PM PDT 24 180472470882 ps
T155 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1069479077 Apr 30 01:11:04 PM PDT 24 Apr 30 01:11:29 PM PDT 24 3014353325 ps
T82 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2985445894 Apr 30 01:27:34 PM PDT 24 Apr 30 01:29:39 PM PDT 24 5743512984 ps
T14 /workspace/coverage/default/35.sram_ctrl_multiple_keys.886850647 Apr 30 01:23:51 PM PDT 24 Apr 30 01:39:44 PM PDT 24 39337101520 ps
T65 /workspace/coverage/default/38.sram_ctrl_regwen.1365506273 Apr 30 01:25:07 PM PDT 24 Apr 30 01:32:46 PM PDT 24 2483437871 ps
T27 /workspace/coverage/default/37.sram_ctrl_alert_test.1813692128 Apr 30 01:24:44 PM PDT 24 Apr 30 01:24:45 PM PDT 24 38454347 ps
T9 /workspace/coverage/default/31.sram_ctrl_lc_escalation.1935283353 Apr 30 01:22:29 PM PDT 24 Apr 30 01:23:42 PM PDT 24 12780860506 ps
T156 /workspace/coverage/default/9.sram_ctrl_partial_access.1442330151 Apr 30 01:12:56 PM PDT 24 Apr 30 01:13:41 PM PDT 24 468587103 ps
T49 /workspace/coverage/default/42.sram_ctrl_stress_all.1503616108 Apr 30 01:26:40 PM PDT 24 Apr 30 02:30:15 PM PDT 24 121385139918 ps
T147 /workspace/coverage/default/45.sram_ctrl_multiple_keys.2777604661 Apr 30 01:27:21 PM PDT 24 Apr 30 01:34:34 PM PDT 24 18185418274 ps
T157 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.4119412052 Apr 30 01:11:26 PM PDT 24 Apr 30 01:11:32 PM PDT 24 1338798469 ps
T30 /workspace/coverage/default/37.sram_ctrl_lc_escalation.2742852524 Apr 30 01:24:37 PM PDT 24 Apr 30 01:26:06 PM PDT 24 28585243744 ps
T145 /workspace/coverage/default/10.sram_ctrl_partial_access.3886839661 Apr 30 01:13:34 PM PDT 24 Apr 30 01:14:00 PM PDT 24 9059199724 ps
T152 /workspace/coverage/default/26.sram_ctrl_multiple_keys.4151710735 Apr 30 01:20:28 PM PDT 24 Apr 30 01:21:49 PM PDT 24 2923866464 ps
T158 /workspace/coverage/default/31.sram_ctrl_partial_access.741713946 Apr 30 01:22:25 PM PDT 24 Apr 30 01:22:37 PM PDT 24 783110555 ps
T159 /workspace/coverage/default/8.sram_ctrl_mem_walk.506261569 Apr 30 01:12:51 PM PDT 24 Apr 30 01:18:00 PM PDT 24 35843408160 ps
T28 /workspace/coverage/default/47.sram_ctrl_regwen.1835185322 Apr 30 01:28:07 PM PDT 24 Apr 30 01:32:21 PM PDT 24 40821631337 ps
T148 /workspace/coverage/default/39.sram_ctrl_alert_test.4044239698 Apr 30 01:25:39 PM PDT 24 Apr 30 01:25:40 PM PDT 24 24865487 ps
T151 /workspace/coverage/default/42.sram_ctrl_multiple_keys.2503248199 Apr 30 01:26:20 PM PDT 24 Apr 30 01:35:54 PM PDT 24 196817706590 ps
T119 /workspace/coverage/default/13.sram_ctrl_lc_escalation.3947534787 Apr 30 01:15:08 PM PDT 24 Apr 30 01:16:15 PM PDT 24 19695182627 ps
T144 /workspace/coverage/default/1.sram_ctrl_multiple_keys.2585290996 Apr 30 01:11:03 PM PDT 24 Apr 30 01:26:38 PM PDT 24 104430272145 ps
T160 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1910511963 Apr 30 01:22:29 PM PDT 24 Apr 30 01:23:33 PM PDT 24 3160249261 ps
T103 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2625636520 Apr 30 01:11:21 PM PDT 24 Apr 30 01:17:16 PM PDT 24 14694445080 ps
T146 /workspace/coverage/default/21.sram_ctrl_regwen.2618517933 Apr 30 01:18:27 PM PDT 24 Apr 30 01:20:04 PM PDT 24 2431988040 ps
T36 /workspace/coverage/default/43.sram_ctrl_ram_cfg.2588018319 Apr 30 01:26:56 PM PDT 24 Apr 30 01:26:59 PM PDT 24 682655153 ps
T120 /workspace/coverage/default/16.sram_ctrl_lc_escalation.1771310179 Apr 30 01:16:18 PM PDT 24 Apr 30 01:17:34 PM PDT 24 40817754083 ps
T104 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1736564062 Apr 30 01:27:38 PM PDT 24 Apr 30 01:33:13 PM PDT 24 60813717020 ps
T161 /workspace/coverage/default/36.sram_ctrl_ram_cfg.4251786951 Apr 30 01:24:25 PM PDT 24 Apr 30 01:24:30 PM PDT 24 3349678052 ps
T83 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.420228388 Apr 30 01:25:27 PM PDT 24 Apr 30 01:27:29 PM PDT 24 3272502629 ps
T162 /workspace/coverage/default/49.sram_ctrl_bijection.4195060373 Apr 30 01:28:42 PM PDT 24 Apr 30 01:54:01 PM PDT 24 72016248475 ps
T163 /workspace/coverage/default/46.sram_ctrl_mem_walk.770677613 Apr 30 01:27:47 PM PDT 24 Apr 30 01:29:47 PM PDT 24 16447580730 ps
T31 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2355545277 Apr 30 01:21:34 PM PDT 24 Apr 30 01:21:51 PM PDT 24 724909984 ps
T58 /workspace/coverage/default/15.sram_ctrl_multiple_keys.246704335 Apr 30 01:15:34 PM PDT 24 Apr 30 01:32:46 PM PDT 24 91200245922 ps
T59 /workspace/coverage/default/35.sram_ctrl_mem_walk.1421053151 Apr 30 01:24:03 PM PDT 24 Apr 30 01:26:50 PM PDT 24 36904853133 ps
T50 /workspace/coverage/default/1.sram_ctrl_stress_all.3140260385 Apr 30 01:11:21 PM PDT 24 Apr 30 02:01:51 PM PDT 24 114111420454 ps
T60 /workspace/coverage/default/0.sram_ctrl_alert_test.3377040867 Apr 30 01:11:02 PM PDT 24 Apr 30 01:11:03 PM PDT 24 12725028 ps
T61 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.4238884189 Apr 30 01:28:56 PM PDT 24 Apr 30 01:31:05 PM PDT 24 12888809663 ps
T32 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.4068303823 Apr 30 01:25:35 PM PDT 24 Apr 30 01:26:23 PM PDT 24 883856627 ps
T62 /workspace/coverage/default/31.sram_ctrl_executable.2664033501 Apr 30 01:22:29 PM PDT 24 Apr 30 01:31:31 PM PDT 24 9083217423 ps
T63 /workspace/coverage/default/4.sram_ctrl_alert_test.1621096322 Apr 30 01:11:48 PM PDT 24 Apr 30 01:11:49 PM PDT 24 11264885 ps
T64 /workspace/coverage/default/7.sram_ctrl_mem_walk.2100620086 Apr 30 01:12:26 PM PDT 24 Apr 30 01:14:45 PM PDT 24 4114898268 ps
T48 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.185441680 Apr 30 01:11:11 PM PDT 24 Apr 30 01:28:19 PM PDT 24 17980140789 ps
T84 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1740734425 Apr 30 01:21:57 PM PDT 24 Apr 30 01:23:06 PM PDT 24 3649146990 ps
T140 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1092838436 Apr 30 01:24:16 PM PDT 24 Apr 30 01:32:18 PM PDT 24 54712489835 ps
T137 /workspace/coverage/default/45.sram_ctrl_executable.2711503466 Apr 30 01:27:28 PM PDT 24 Apr 30 01:43:35 PM PDT 24 37804881305 ps
T150 /workspace/coverage/default/20.sram_ctrl_alert_test.2122894759 Apr 30 01:18:12 PM PDT 24 Apr 30 01:18:13 PM PDT 24 14758596 ps
T164 /workspace/coverage/default/17.sram_ctrl_max_throughput.2403438585 Apr 30 01:16:40 PM PDT 24 Apr 30 01:17:40 PM PDT 24 2604294872 ps
T165 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.4168383503 Apr 30 01:22:49 PM PDT 24 Apr 30 01:28:16 PM PDT 24 25696198287 ps
T29 /workspace/coverage/default/25.sram_ctrl_regwen.25879325 Apr 30 01:20:14 PM PDT 24 Apr 30 01:26:13 PM PDT 24 1629199371 ps
T166 /workspace/coverage/default/23.sram_ctrl_bijection.3347097034 Apr 30 01:19:09 PM PDT 24 Apr 30 01:38:39 PM PDT 24 69528057854 ps
T138 /workspace/coverage/default/7.sram_ctrl_executable.3507025370 Apr 30 01:12:17 PM PDT 24 Apr 30 01:23:08 PM PDT 24 212829246140 ps
T167 /workspace/coverage/default/23.sram_ctrl_smoke.390950731 Apr 30 01:19:00 PM PDT 24 Apr 30 01:19:07 PM PDT 24 5561326761 ps
T168 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2520774500 Apr 30 01:12:12 PM PDT 24 Apr 30 01:12:52 PM PDT 24 9149247296 ps
T169 /workspace/coverage/default/41.sram_ctrl_partial_access.4013182669 Apr 30 01:26:01 PM PDT 24 Apr 30 01:26:19 PM PDT 24 1546736100 ps
T170 /workspace/coverage/default/43.sram_ctrl_partial_access.1707502905 Apr 30 01:26:47 PM PDT 24 Apr 30 01:27:10 PM PDT 24 1516381006 ps
T171 /workspace/coverage/default/11.sram_ctrl_alert_test.1584263201 Apr 30 01:14:19 PM PDT 24 Apr 30 01:14:21 PM PDT 24 43257738 ps
T143 /workspace/coverage/default/0.sram_ctrl_regwen.3518929199 Apr 30 01:11:02 PM PDT 24 Apr 30 01:32:44 PM PDT 24 13997022994 ps
T172 /workspace/coverage/default/28.sram_ctrl_alert_test.3655013279 Apr 30 01:21:50 PM PDT 24 Apr 30 01:21:51 PM PDT 24 159213294 ps
T136 /workspace/coverage/default/32.sram_ctrl_stress_all.3469817762 Apr 30 01:23:08 PM PDT 24 Apr 30 02:31:22 PM PDT 24 174129763323 ps
T173 /workspace/coverage/default/41.sram_ctrl_mem_walk.5820706 Apr 30 01:26:13 PM PDT 24 Apr 30 01:28:38 PM PDT 24 8014385335 ps
T139 /workspace/coverage/default/35.sram_ctrl_regwen.3868802219 Apr 30 01:24:02 PM PDT 24 Apr 30 01:44:00 PM PDT 24 5631616462 ps
T174 /workspace/coverage/default/44.sram_ctrl_partial_access.4166083482 Apr 30 01:27:04 PM PDT 24 Apr 30 01:27:35 PM PDT 24 19323106757 ps
T175 /workspace/coverage/default/2.sram_ctrl_ram_cfg.3317123074 Apr 30 01:11:19 PM PDT 24 Apr 30 01:11:23 PM PDT 24 710270754 ps
T141 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1610708527 Apr 30 01:11:33 PM PDT 24 Apr 30 01:17:52 PM PDT 24 66881188864 ps
T176 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1683669793 Apr 30 01:27:38 PM PDT 24 Apr 30 01:34:14 PM PDT 24 15142862605 ps
T33 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3491676219 Apr 30 01:12:06 PM PDT 24 Apr 30 01:12:26 PM PDT 24 2848379761 ps
T85 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1627217534 Apr 30 01:14:46 PM PDT 24 Apr 30 01:16:05 PM PDT 24 983596963 ps
T113 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3959039201 Apr 30 01:24:59 PM PDT 24 Apr 30 01:27:04 PM PDT 24 804546720 ps
T114 /workspace/coverage/default/34.sram_ctrl_partial_access.760947106 Apr 30 01:23:44 PM PDT 24 Apr 30 01:23:50 PM PDT 24 3117721708 ps
T115 /workspace/coverage/default/24.sram_ctrl_multiple_keys.1866962552 Apr 30 01:19:35 PM PDT 24 Apr 30 01:25:37 PM PDT 24 2722226445 ps
T116 /workspace/coverage/default/21.sram_ctrl_bijection.891902801 Apr 30 01:18:13 PM PDT 24 Apr 30 01:27:33 PM PDT 24 32815943253 ps
T51 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.831257855 Apr 30 01:22:17 PM PDT 24 Apr 30 01:22:34 PM PDT 24 2087708562 ps
T117 /workspace/coverage/default/13.sram_ctrl_executable.3309383091 Apr 30 01:15:07 PM PDT 24 Apr 30 01:31:30 PM PDT 24 16425312185 ps
T96 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.2832464771 Apr 30 01:19:48 PM PDT 24 Apr 30 01:22:30 PM PDT 24 4379233681 ps
T118 /workspace/coverage/default/36.sram_ctrl_regwen.3749397435 Apr 30 01:24:27 PM PDT 24 Apr 30 01:27:27 PM PDT 24 22597899186 ps
T177 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3788941209 Apr 30 01:23:15 PM PDT 24 Apr 30 01:23:36 PM PDT 24 745018316 ps
T178 /workspace/coverage/default/26.sram_ctrl_bijection.3363249933 Apr 30 01:20:29 PM PDT 24 Apr 30 01:38:08 PM PDT 24 46669977637 ps
T179 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1029076826 Apr 30 01:18:52 PM PDT 24 Apr 30 01:36:00 PM PDT 24 34933981109 ps
T180 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3735088205 Apr 30 01:23:02 PM PDT 24 Apr 30 01:25:33 PM PDT 24 19715401681 ps
T181 /workspace/coverage/default/8.sram_ctrl_multiple_keys.720483127 Apr 30 01:12:34 PM PDT 24 Apr 30 01:16:56 PM PDT 24 4609214729 ps
T182 /workspace/coverage/default/15.sram_ctrl_max_throughput.451646113 Apr 30 01:15:46 PM PDT 24 Apr 30 01:16:07 PM PDT 24 729281756 ps
T183 /workspace/coverage/default/2.sram_ctrl_multiple_keys.1943978848 Apr 30 01:11:16 PM PDT 24 Apr 30 01:30:33 PM PDT 24 18327088179 ps
T184 /workspace/coverage/default/18.sram_ctrl_smoke.3198722528 Apr 30 01:16:51 PM PDT 24 Apr 30 01:16:57 PM PDT 24 1380180262 ps
T142 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3842664153 Apr 30 01:14:36 PM PDT 24 Apr 30 01:21:12 PM PDT 24 18432213373 ps
T185 /workspace/coverage/default/33.sram_ctrl_stress_all.212324901 Apr 30 01:23:24 PM PDT 24 Apr 30 02:25:41 PM PDT 24 50496455822 ps
T186 /workspace/coverage/default/20.sram_ctrl_smoke.3771597787 Apr 30 01:17:41 PM PDT 24 Apr 30 01:19:21 PM PDT 24 1364921565 ps
T187 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1926314696 Apr 30 01:22:35 PM PDT 24 Apr 30 01:23:51 PM PDT 24 5339584033 ps
T188 /workspace/coverage/default/1.sram_ctrl_bijection.53796674 Apr 30 01:11:11 PM PDT 24 Apr 30 01:20:34 PM PDT 24 8460455686 ps
T189 /workspace/coverage/default/39.sram_ctrl_mem_walk.84965419 Apr 30 01:25:28 PM PDT 24 Apr 30 01:29:23 PM PDT 24 4108392349 ps
T134 /workspace/coverage/default/45.sram_ctrl_regwen.1440776866 Apr 30 01:27:27 PM PDT 24 Apr 30 01:33:22 PM PDT 24 34609934254 ps
T190 /workspace/coverage/default/22.sram_ctrl_alert_test.608971819 Apr 30 01:19:00 PM PDT 24 Apr 30 01:19:01 PM PDT 24 12791504 ps
T191 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3889221997 Apr 30 01:17:47 PM PDT 24 Apr 30 01:22:32 PM PDT 24 16678478746 ps
T192 /workspace/coverage/default/12.sram_ctrl_lc_escalation.670866679 Apr 30 01:14:41 PM PDT 24 Apr 30 01:15:07 PM PDT 24 12943803503 ps
T193 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2340330312 Apr 30 01:26:10 PM PDT 24 Apr 30 01:27:07 PM PDT 24 3115489233 ps
T135 /workspace/coverage/default/49.sram_ctrl_stress_all.150183846 Apr 30 01:28:57 PM PDT 24 Apr 30 03:18:52 PM PDT 24 1864522677435 ps
T194 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1783760368 Apr 30 01:21:51 PM PDT 24 Apr 30 01:26:38 PM PDT 24 49025924088 ps
T195 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2383879261 Apr 30 01:11:39 PM PDT 24 Apr 30 01:13:04 PM PDT 24 8388582242 ps
T196 /workspace/coverage/default/17.sram_ctrl_executable.2030581656 Apr 30 01:16:44 PM PDT 24 Apr 30 01:25:43 PM PDT 24 50540169717 ps
T197 /workspace/coverage/default/30.sram_ctrl_lc_escalation.3370580507 Apr 30 01:22:09 PM PDT 24 Apr 30 01:23:54 PM PDT 24 18547358030 ps
T198 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.2394015594 Apr 30 01:21:04 PM PDT 24 Apr 30 01:31:44 PM PDT 24 109799016194 ps
T199 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2591293851 Apr 30 01:12:44 PM PDT 24 Apr 30 01:15:46 PM PDT 24 19711266050 ps
T200 /workspace/coverage/default/36.sram_ctrl_partial_access.3287483761 Apr 30 01:24:09 PM PDT 24 Apr 30 01:25:30 PM PDT 24 1600440483 ps
T201 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2155785718 Apr 30 01:15:27 PM PDT 24 Apr 30 01:16:30 PM PDT 24 9446947563 ps
T202 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1120305180 Apr 30 01:11:59 PM PDT 24 Apr 30 01:17:24 PM PDT 24 27106877130 ps
T203 /workspace/coverage/default/2.sram_ctrl_max_throughput.3681963675 Apr 30 01:11:15 PM PDT 24 Apr 30 01:12:51 PM PDT 24 1867604145 ps
T204 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.41957611 Apr 30 01:25:10 PM PDT 24 Apr 30 01:27:21 PM PDT 24 6206446753 ps
T205 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2140672993 Apr 30 01:11:58 PM PDT 24 Apr 30 01:16:25 PM PDT 24 18443348299 ps
T52 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3105629284 Apr 30 01:24:44 PM PDT 24 Apr 30 01:25:45 PM PDT 24 2469198666 ps
T206 /workspace/coverage/default/49.sram_ctrl_lc_escalation.1538981388 Apr 30 01:28:50 PM PDT 24 Apr 30 01:29:48 PM PDT 24 8212927902 ps
T53 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1893021151 Apr 30 01:21:58 PM PDT 24 Apr 30 01:24:44 PM PDT 24 9239458361 ps
T207 /workspace/coverage/default/35.sram_ctrl_max_throughput.2996141908 Apr 30 01:23:57 PM PDT 24 Apr 30 01:24:15 PM PDT 24 734290961 ps
T208 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.285505547 Apr 30 01:26:31 PM PDT 24 Apr 30 01:51:56 PM PDT 24 27814716945 ps
T209 /workspace/coverage/default/28.sram_ctrl_executable.4278689375 Apr 30 01:21:38 PM PDT 24 Apr 30 01:32:01 PM PDT 24 14470279665 ps
T210 /workspace/coverage/default/16.sram_ctrl_ram_cfg.921365556 Apr 30 01:16:21 PM PDT 24 Apr 30 01:16:24 PM PDT 24 1401275942 ps
T211 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.203037236 Apr 30 01:15:13 PM PDT 24 Apr 30 01:18:06 PM PDT 24 13451450362 ps
T212 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.173258812 Apr 30 01:22:18 PM PDT 24 Apr 30 01:24:50 PM PDT 24 10352195102 ps
T213 /workspace/coverage/default/11.sram_ctrl_lc_escalation.1028347321 Apr 30 01:14:15 PM PDT 24 Apr 30 01:14:38 PM PDT 24 14350425348 ps
T214 /workspace/coverage/default/8.sram_ctrl_ram_cfg.898931659 Apr 30 01:12:49 PM PDT 24 Apr 30 01:12:52 PM PDT 24 1399595544 ps
T215 /workspace/coverage/default/38.sram_ctrl_multiple_keys.1781876575 Apr 30 01:24:51 PM PDT 24 Apr 30 01:28:28 PM PDT 24 1510560891 ps
T216 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3712466720 Apr 30 01:15:22 PM PDT 24 Apr 30 01:16:13 PM PDT 24 3111142170 ps
T217 /workspace/coverage/default/34.sram_ctrl_ram_cfg.91539541 Apr 30 01:23:43 PM PDT 24 Apr 30 01:23:47 PM PDT 24 1970495886 ps
T218 /workspace/coverage/default/3.sram_ctrl_bijection.325579287 Apr 30 01:11:19 PM PDT 24 Apr 30 01:44:14 PM PDT 24 349990763066 ps
T219 /workspace/coverage/default/30.sram_ctrl_bijection.2032122166 Apr 30 01:22:03 PM PDT 24 Apr 30 01:38:48 PM PDT 24 61513740947 ps
T220 /workspace/coverage/default/25.sram_ctrl_stress_all.2350485780 Apr 30 01:20:16 PM PDT 24 Apr 30 02:30:43 PM PDT 24 115488598500 ps
T221 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.3811330757 Apr 30 01:26:21 PM PDT 24 Apr 30 01:30:16 PM PDT 24 15999060188 ps
T54 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.545049845 Apr 30 01:11:48 PM PDT 24 Apr 30 01:14:30 PM PDT 24 2192026550 ps
T222 /workspace/coverage/default/24.sram_ctrl_mem_walk.3207659377 Apr 30 01:19:49 PM PDT 24 Apr 30 01:24:26 PM PDT 24 28109624550 ps
T223 /workspace/coverage/default/20.sram_ctrl_stress_all.774439476 Apr 30 01:18:13 PM PDT 24 Apr 30 01:55:53 PM PDT 24 15704974409 ps
T224 /workspace/coverage/default/3.sram_ctrl_lc_escalation.455375628 Apr 30 01:11:27 PM PDT 24 Apr 30 01:12:24 PM PDT 24 9743706570 ps
T225 /workspace/coverage/default/2.sram_ctrl_smoke.2427293702 Apr 30 01:11:16 PM PDT 24 Apr 30 01:11:24 PM PDT 24 2939613505 ps
T226 /workspace/coverage/default/46.sram_ctrl_partial_access.3120106686 Apr 30 01:27:41 PM PDT 24 Apr 30 01:28:30 PM PDT 24 790131888 ps
T227 /workspace/coverage/default/13.sram_ctrl_partial_access.4176424512 Apr 30 01:15:00 PM PDT 24 Apr 30 01:15:18 PM PDT 24 4113893461 ps
T228 /workspace/coverage/default/23.sram_ctrl_multiple_keys.2701684141 Apr 30 01:19:07 PM PDT 24 Apr 30 01:36:35 PM PDT 24 19963717160 ps
T229 /workspace/coverage/default/14.sram_ctrl_lc_escalation.4249311118 Apr 30 01:15:22 PM PDT 24 Apr 30 01:16:49 PM PDT 24 61568594299 ps
T230 /workspace/coverage/default/12.sram_ctrl_executable.4096714715 Apr 30 01:14:41 PM PDT 24 Apr 30 01:34:02 PM PDT 24 35841240202 ps
T55 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.4280901928 Apr 30 01:16:00 PM PDT 24 Apr 30 01:16:32 PM PDT 24 6254081479 ps
T56 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.117550773 Apr 30 01:23:27 PM PDT 24 Apr 30 01:23:59 PM PDT 24 976974410 ps
T231 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1036326881 Apr 30 01:17:11 PM PDT 24 Apr 30 01:20:04 PM PDT 24 17267434624 ps
T232 /workspace/coverage/default/30.sram_ctrl_alert_test.100653654 Apr 30 01:22:23 PM PDT 24 Apr 30 01:22:24 PM PDT 24 41507344 ps
T233 /workspace/coverage/default/26.sram_ctrl_lc_escalation.582162393 Apr 30 01:20:30 PM PDT 24 Apr 30 01:21:29 PM PDT 24 11329278788 ps
T234 /workspace/coverage/default/37.sram_ctrl_max_throughput.3890497725 Apr 30 01:24:30 PM PDT 24 Apr 30 01:25:51 PM PDT 24 3421809159 ps
T235 /workspace/coverage/default/6.sram_ctrl_alert_test.2584999191 Apr 30 01:12:08 PM PDT 24 Apr 30 01:12:09 PM PDT 24 39443058 ps
T236 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.888696581 Apr 30 01:12:19 PM PDT 24 Apr 30 01:29:53 PM PDT 24 60997774976 ps
T237 /workspace/coverage/default/6.sram_ctrl_lc_escalation.3867425396 Apr 30 01:11:59 PM PDT 24 Apr 30 01:12:06 PM PDT 24 694141395 ps
T238 /workspace/coverage/default/43.sram_ctrl_mem_walk.4012854219 Apr 30 01:26:57 PM PDT 24 Apr 30 01:31:36 PM PDT 24 29911480684 ps
T239 /workspace/coverage/default/31.sram_ctrl_regwen.2953930692 Apr 30 01:22:28 PM PDT 24 Apr 30 01:23:45 PM PDT 24 1394577585 ps
T240 /workspace/coverage/default/7.sram_ctrl_stress_all.2810828772 Apr 30 01:12:25 PM PDT 24 Apr 30 02:17:51 PM PDT 24 187086986877 ps
T241 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.219073708 Apr 30 01:15:35 PM PDT 24 Apr 30 01:20:03 PM PDT 24 42700816359 ps
T242 /workspace/coverage/default/16.sram_ctrl_executable.2313703403 Apr 30 01:16:20 PM PDT 24 Apr 30 01:19:48 PM PDT 24 4769743639 ps
T243 /workspace/coverage/default/29.sram_ctrl_regwen.702286712 Apr 30 01:21:51 PM PDT 24 Apr 30 01:35:48 PM PDT 24 5560635158 ps
T244 /workspace/coverage/default/19.sram_ctrl_executable.3232948504 Apr 30 01:17:31 PM PDT 24 Apr 30 01:40:56 PM PDT 24 10311762287 ps
T245 /workspace/coverage/default/39.sram_ctrl_multiple_keys.3345690165 Apr 30 01:25:12 PM PDT 24 Apr 30 01:28:50 PM PDT 24 4424291318 ps
T246 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.677097884 Apr 30 01:26:03 PM PDT 24 Apr 30 01:28:25 PM PDT 24 14562647577 ps
T247 /workspace/coverage/default/2.sram_ctrl_bijection.1535458984 Apr 30 01:11:15 PM PDT 24 Apr 30 01:23:42 PM PDT 24 41705981172 ps
T248 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.578622318 Apr 30 01:21:50 PM PDT 24 Apr 30 01:22:25 PM PDT 24 740229206 ps
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T300 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3858433319 Apr 30 01:14:21 PM PDT 24 Apr 30 01:30:02 PM PDT 24 12776159296 ps
T301 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3368006857 Apr 30 01:19:25 PM PDT 24 Apr 30 01:19:34 PM PDT 24 864806603 ps
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T303 /workspace/coverage/default/46.sram_ctrl_max_throughput.3841050658 Apr 30 01:27:43 PM PDT 24 Apr 30 01:28:10 PM PDT 24 2852382777 ps
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T308 /workspace/coverage/default/27.sram_ctrl_regwen.1354635032 Apr 30 01:21:03 PM PDT 24 Apr 30 01:36:14 PM PDT 24 13770146773 ps
T309 /workspace/coverage/default/46.sram_ctrl_executable.185478895 Apr 30 01:27:45 PM PDT 24 Apr 30 01:28:57 PM PDT 24 4203781912 ps
T310 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2037827513 Apr 30 01:11:15 PM PDT 24 Apr 30 01:11:21 PM PDT 24 1291471220 ps
T311 /workspace/coverage/default/28.sram_ctrl_multiple_keys.460987274 Apr 30 01:21:17 PM PDT 24 Apr 30 01:22:05 PM PDT 24 1098495675 ps
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