Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	142347975	1			T2	142179		T4	1065		T6	5202
triple_byte_access	2760346	1			T2	2812		T4	973		T5	3625
halfword_access	4236316	1			T2	4216		T4	1483		T5	6907
byte_access	5912634	1			T2	5791		T4	1987		T5	12956
zero_access	1788032	1			T2	1433		T4	478		T5	7451

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78297363

1

T2

77999

T4

2977

T6

2626

auto[1]

78747940

1

T2

78432

T4

3009

T6

2576

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	70809825	1			T2	70967		T4	531		T6	2626
auto[0]	triple_byte_access	1318464	1			T2	1404		T4	472		T5	652
auto[0]	halfword_access	2072650	1			T2	2050		T4	757		T5	2365
auto[0]	byte_access	3030200	1			T2	2910		T4	990		T5	6960
auto[0]	zero_access	1066224	1			T2	668		T4	227		T5	6002
auto[1]	word_access	71538150	1			T2	71212		T4	534		T6	2576
auto[1]	triple_byte_access	1441882	1			T2	1408		T4	501		T5	2973
auto[1]	halfword_access	2163666	1			T2	2166		T4	726		T5	4542
auto[1]	byte_access	2882434	1			T2	2881		T4	997		T5	5996
auto[1]	zero_access	721808	1			T2	765		T4	251		T5	1449