Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	334311762	1			T1	65110		T2	41136		T3	12490
instr_valid_dis	281399023	1			T1	65110		T2	41136		T3	12490
instr_en	38680744	1			T18	108286		T21	182300		T31	49662

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13262882	1			T18	76772		T21	59292		T31	22310
sram_ifetch_valid_disable	286475989	1			T1	65110		T2	41136		T3	12490
sram_ifetch_enable	34572891	1			T18	81602		T21	106590		T31	21930

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	334311762	1			T1	65110		T2	41136		T3	12490
hw_debug_en_valid_off	287119695	1			T1	65110		T2	41136		T3	12490
hw_debug_en_on	28471965	1			T18	167506		T21	194400		T31	86

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	286475989	1			T1	65110		T2	41136		T3	12490
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	268804788	1			T1	65110		T2	41136		T3	12490
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	12928585	1			T18	41858		T21	92332		T31	27352
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3916620	1			T31	6558		T15	37518		T6	42650
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1417046	1			T31	6558		T127	3882		T135	29048
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1871480	1			T15	37518		T6	42650		T28	47926
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	6924488	1			T18	63622		T21	53154		T31	86
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1813770	1			T18	24920		T21	50776		T136	20286
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	4036056	1			T18	38702		T31	86		T15	74
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	12827130	1			T18	46504		T21	130954		T15	48602
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6192304	1			T18	44734		T21	88232		T15	40994
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4823244	1			T21	42722		T15	7608		T6	102492

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	18761181	1			T18	14576		T21	83830		T31	6558
lc_exec_en	8720347	1			T18	57380		T21	10292		T15	116290
valid_exec_dis	274724674	1			T1	65110		T2	41136		T3	12490
invalid_exec_dis	47835773	1			T18	158374		T21	165882		T31	44240