Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.06 99.81 96.99 100.00 100.00 98.60 99.70 98.33


Total tests in report: 1033
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.27 87.27 97.47 97.47 84.68 84.68 94.42 94.42 71.43 71.43 91.55 91.55 95.10 95.10 76.25 76.25 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1294214814
94.32 7.04 99.06 1.59 90.13 5.45 95.85 1.42 100.00 28.57 96.62 5.07 95.25 0.15 83.30 7.05 /workspace/coverage/default/11.sram_ctrl_stress_all.3730920058
95.37 1.05 99.25 0.19 91.04 0.91 96.06 0.21 100.00 0.00 97.46 0.85 95.25 0.00 88.50 5.19 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3271190035
96.14 0.77 99.53 0.28 91.43 0.39 97.48 1.42 100.00 0.00 97.75 0.28 96.43 1.19 90.35 1.86 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.69078902
96.79 0.65 99.72 0.19 93.64 2.21 97.83 0.36 100.00 0.00 98.59 0.85 97.03 0.59 90.72 0.37 /workspace/coverage/default/0.sram_ctrl_sec_cm.3655933578
97.16 0.37 99.72 0.00 93.64 0.00 97.83 0.00 100.00 0.00 98.59 0.00 97.03 0.00 93.32 2.60 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2690231157
97.49 0.33 99.72 0.00 93.64 0.00 98.30 0.46 100.00 0.00 98.59 0.00 97.03 0.00 95.18 1.86 /workspace/coverage/default/20.sram_ctrl_executable.1954191488
97.73 0.24 99.72 0.00 94.03 0.39 98.72 0.43 100.00 0.00 98.87 0.28 97.03 0.00 95.73 0.56 /workspace/coverage/default/14.sram_ctrl_alert_test.1657373553
97.91 0.18 99.72 0.00 94.03 0.00 98.79 0.07 100.00 0.00 98.87 0.00 98.22 1.19 95.73 0.00 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2080109198
98.06 0.16 99.72 0.00 94.16 0.13 98.86 0.07 100.00 0.00 98.87 0.00 99.11 0.89 95.73 0.00 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3380147969
98.19 0.12 99.72 0.00 94.16 0.00 99.29 0.43 100.00 0.00 98.87 0.00 99.55 0.45 95.73 0.00 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.72390631
98.30 0.11 99.81 0.09 94.16 0.00 100.00 0.71 100.00 0.00 98.87 0.00 99.55 0.00 95.73 0.00 /workspace/coverage/default/11.sram_ctrl_ram_cfg.904863153
98.41 0.11 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.55 0.00 96.47 0.74 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3425255421
98.52 0.11 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.55 0.00 97.22 0.74 /workspace/coverage/default/24.sram_ctrl_stress_all.733516761
98.57 0.05 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.55 0.00 97.59 0.37 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3224273032
98.62 0.05 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.55 0.00 97.96 0.37 /workspace/coverage/default/28.sram_ctrl_executable.2794840627
98.65 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.55 0.00 98.14 0.19 /workspace/coverage/default/10.sram_ctrl_multiple_keys.3909673258
98.68 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.55 0.00 98.33 0.19 /workspace/coverage/default/20.sram_ctrl_lc_escalation.3100979008
98.70 0.02 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.15 98.33 0.00 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2172337296

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1328340755
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2939004478
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2784362515
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3564795059
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3458461161
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4273087066
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1079226636
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.734075493
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4149026539
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3706093983
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3754756784
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2898853595
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.736284105
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3012401529
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3444506051
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.939674120
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.530835727
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3748003990
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.935451684
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2562963852
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.246211941
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.854051466
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.556423694
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3512462076
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.534826380
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.659166724
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4096356880
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4195920774
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.730124164
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.404798147
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3702598695
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1862602338
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4083968695
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2680430662
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3646203748
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3927309248
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3621666977
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3572654931
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1410719193
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3307625880
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.574476535
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1885474242
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3086888339
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1111599385
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.962279890
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1429271225
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.877244667
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1076016024
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2627411630
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1652960759
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3397661653
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2838550164
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2143063995
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1277529694
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3500531079
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.181261802
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1819774030
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1224428140
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1608136075
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3530542160
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.924908933
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2602959865
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1813665263
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.20884755
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.527451919
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4021746315
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.588790654
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.43557112
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3962041670
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1920758173
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1927857296
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2030415291
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1409212468
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3099773851
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2188936706
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4027473132
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2647226173
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2176711160
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.897389995
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.20250573
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2894523614
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3114203060
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3997744955
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1055497139
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1987334641
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.93870026
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.443142456
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2478028220
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3656452599
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.676899364
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3611446568
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2105252433
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2506946304
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3204971126
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.111358829
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1982086973
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2638027024
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3297645182
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3921605650
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2524601068
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.649987823
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1661274842
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.469634359
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.812765944
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4138782589
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4030101577
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3913507137
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3183401450
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.746340720
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.798580811
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.499776746
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.488217292
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2941325311
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3538678616
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4142938627
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3395237239
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.813999626
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1338181047
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.526617145
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1353867699
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1729592718
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.873383456
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2345346496
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.330036857
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.756551646
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1965426949
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2190314715
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1618165783
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3332101974
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3528531319
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2553162857
/workspace/coverage/default/0.sram_ctrl_alert_test.3056565178
/workspace/coverage/default/0.sram_ctrl_bijection.336300671
/workspace/coverage/default/0.sram_ctrl_executable.3727300346
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2420440860
/workspace/coverage/default/0.sram_ctrl_max_throughput.2671541861
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2866635341
/workspace/coverage/default/0.sram_ctrl_mem_walk.477595352
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2844356680
/workspace/coverage/default/0.sram_ctrl_partial_access.1669823241
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.96722097
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3359633121
/workspace/coverage/default/0.sram_ctrl_regwen.3175622125
/workspace/coverage/default/0.sram_ctrl_smoke.199550476
/workspace/coverage/default/0.sram_ctrl_stress_all.1996453275
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.807206492
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2070900596
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1227464032
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.897349597
/workspace/coverage/default/1.sram_ctrl_alert_test.2344789191
/workspace/coverage/default/1.sram_ctrl_bijection.2937536227
/workspace/coverage/default/1.sram_ctrl_executable.1915572123
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1562804663
/workspace/coverage/default/1.sram_ctrl_max_throughput.1102354882
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1606204780
/workspace/coverage/default/1.sram_ctrl_mem_walk.2229335636
/workspace/coverage/default/1.sram_ctrl_multiple_keys.602592428
/workspace/coverage/default/1.sram_ctrl_partial_access.2491991801
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2954394357
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1124719304
/workspace/coverage/default/1.sram_ctrl_regwen.2927145301
/workspace/coverage/default/1.sram_ctrl_sec_cm.1644184164
/workspace/coverage/default/1.sram_ctrl_smoke.3559545178
/workspace/coverage/default/1.sram_ctrl_stress_all.1138520183
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2978166242
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3578749962
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1745086605
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.4175880993
/workspace/coverage/default/10.sram_ctrl_alert_test.900864023
/workspace/coverage/default/10.sram_ctrl_bijection.1313319719
/workspace/coverage/default/10.sram_ctrl_executable.2299783513
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2991138029
/workspace/coverage/default/10.sram_ctrl_max_throughput.874742307
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.246384917
/workspace/coverage/default/10.sram_ctrl_mem_walk.664718757
/workspace/coverage/default/10.sram_ctrl_partial_access.1736689034
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3344452233
/workspace/coverage/default/10.sram_ctrl_ram_cfg.3590205474
/workspace/coverage/default/10.sram_ctrl_regwen.3248964093
/workspace/coverage/default/10.sram_ctrl_smoke.1271352774
/workspace/coverage/default/10.sram_ctrl_stress_all.1623261977
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3652660397
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3402912580
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2484565180
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.4157767194
/workspace/coverage/default/11.sram_ctrl_alert_test.2408466191
/workspace/coverage/default/11.sram_ctrl_bijection.335207430
/workspace/coverage/default/11.sram_ctrl_executable.396348348
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3534904526
/workspace/coverage/default/11.sram_ctrl_max_throughput.2199106439
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1875998231
/workspace/coverage/default/11.sram_ctrl_mem_walk.3902010906
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3022645214
/workspace/coverage/default/11.sram_ctrl_partial_access.2162730527
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2443667319
/workspace/coverage/default/11.sram_ctrl_regwen.1626756002
/workspace/coverage/default/11.sram_ctrl_smoke.3381491304
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2087479172
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.403285912
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.851410972
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1775257171
/workspace/coverage/default/12.sram_ctrl_alert_test.112603921
/workspace/coverage/default/12.sram_ctrl_bijection.279503890
/workspace/coverage/default/12.sram_ctrl_executable.2664639119
/workspace/coverage/default/12.sram_ctrl_lc_escalation.4122792278
/workspace/coverage/default/12.sram_ctrl_max_throughput.860045931
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/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3833716060
/workspace/coverage/default/43.sram_ctrl_alert_test.1020542035
/workspace/coverage/default/43.sram_ctrl_bijection.4027280114
/workspace/coverage/default/43.sram_ctrl_executable.257281110
/workspace/coverage/default/43.sram_ctrl_lc_escalation.1769280246
/workspace/coverage/default/43.sram_ctrl_max_throughput.4152506673
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1830460835
/workspace/coverage/default/43.sram_ctrl_mem_walk.3334787614
/workspace/coverage/default/43.sram_ctrl_multiple_keys.848623989
/workspace/coverage/default/43.sram_ctrl_partial_access.844425347
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3466695402
/workspace/coverage/default/43.sram_ctrl_ram_cfg.725384776
/workspace/coverage/default/43.sram_ctrl_regwen.477714375
/workspace/coverage/default/43.sram_ctrl_smoke.625974789
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3638824548
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1943162774
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3125752006
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1599580164
/workspace/coverage/default/44.sram_ctrl_alert_test.1548690149
/workspace/coverage/default/44.sram_ctrl_bijection.3975648667
/workspace/coverage/default/44.sram_ctrl_executable.3896427596
/workspace/coverage/default/44.sram_ctrl_lc_escalation.880828527
/workspace/coverage/default/44.sram_ctrl_max_throughput.1475230635
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1127269981
/workspace/coverage/default/44.sram_ctrl_mem_walk.2909062975
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3928109749
/workspace/coverage/default/44.sram_ctrl_partial_access.337319009
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1708423480
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3411398982
/workspace/coverage/default/44.sram_ctrl_regwen.4282685895
/workspace/coverage/default/44.sram_ctrl_smoke.2260493560
/workspace/coverage/default/44.sram_ctrl_stress_all.3176468355
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2235777630
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2996347165
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3477428592
/workspace/coverage/default/45.sram_ctrl_alert_test.1385832992
/workspace/coverage/default/45.sram_ctrl_bijection.401383595
/workspace/coverage/default/45.sram_ctrl_executable.4003886726
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1730011292
/workspace/coverage/default/45.sram_ctrl_max_throughput.123828514
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1968161498
/workspace/coverage/default/45.sram_ctrl_mem_walk.263144231
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3252131043
/workspace/coverage/default/45.sram_ctrl_partial_access.2098595449
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1173919342
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2642006105
/workspace/coverage/default/45.sram_ctrl_regwen.981982999
/workspace/coverage/default/45.sram_ctrl_smoke.243500003
/workspace/coverage/default/45.sram_ctrl_stress_all.2790483359
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2481083090
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3656246340
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3048710427
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3686732883
/workspace/coverage/default/46.sram_ctrl_alert_test.1432228089
/workspace/coverage/default/46.sram_ctrl_bijection.3652251339
/workspace/coverage/default/46.sram_ctrl_executable.800430139
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2823995798
/workspace/coverage/default/46.sram_ctrl_max_throughput.3030134582
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.877841124
/workspace/coverage/default/46.sram_ctrl_mem_walk.2155772935
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2789581978
/workspace/coverage/default/46.sram_ctrl_partial_access.3532836489
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1002356964
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3285018064
/workspace/coverage/default/46.sram_ctrl_regwen.2446510513
/workspace/coverage/default/46.sram_ctrl_smoke.4286651372
/workspace/coverage/default/46.sram_ctrl_stress_all.1903824886
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1869660352
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.5129988
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.436116048
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3900443611
/workspace/coverage/default/47.sram_ctrl_alert_test.3666779681
/workspace/coverage/default/47.sram_ctrl_bijection.2705138821
/workspace/coverage/default/47.sram_ctrl_executable.686464650
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3567141974
/workspace/coverage/default/47.sram_ctrl_max_throughput.4216454054
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3372327179
/workspace/coverage/default/47.sram_ctrl_mem_walk.2894762186
/workspace/coverage/default/47.sram_ctrl_multiple_keys.4158683006
/workspace/coverage/default/47.sram_ctrl_partial_access.142094103
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.4082202990
/workspace/coverage/default/47.sram_ctrl_ram_cfg.4212738819
/workspace/coverage/default/47.sram_ctrl_regwen.2016634353
/workspace/coverage/default/47.sram_ctrl_smoke.1924451484
/workspace/coverage/default/47.sram_ctrl_stress_all.2106048703
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.861973642
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1212561364
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2678389860
/workspace/coverage/default/48.sram_ctrl_alert_test.4017551076
/workspace/coverage/default/48.sram_ctrl_bijection.1082447418
/workspace/coverage/default/48.sram_ctrl_executable.3635973874
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2565127904
/workspace/coverage/default/48.sram_ctrl_max_throughput.1443832626
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1741585948
/workspace/coverage/default/48.sram_ctrl_mem_walk.3401385931
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3596240285
/workspace/coverage/default/48.sram_ctrl_partial_access.2776375109
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2163358403
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3367657901
/workspace/coverage/default/48.sram_ctrl_regwen.2080692732
/workspace/coverage/default/48.sram_ctrl_smoke.1697531835
/workspace/coverage/default/48.sram_ctrl_stress_all.3522894296
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1912036775
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2265649115
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3605210436
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1614634064
/workspace/coverage/default/49.sram_ctrl_alert_test.1808054669
/workspace/coverage/default/49.sram_ctrl_bijection.3899977366
/workspace/coverage/default/49.sram_ctrl_executable.3600592162
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1724703340
/workspace/coverage/default/49.sram_ctrl_max_throughput.1683950866
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2126535696
/workspace/coverage/default/49.sram_ctrl_mem_walk.1827531604
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3403131532
/workspace/coverage/default/49.sram_ctrl_partial_access.163463689
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3574067110
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1790250657
/workspace/coverage/default/49.sram_ctrl_regwen.685167456
/workspace/coverage/default/49.sram_ctrl_smoke.4162828908
/workspace/coverage/default/49.sram_ctrl_stress_all.2626726282
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4028462718
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1451869345
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2569016090
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1196393025
/workspace/coverage/default/5.sram_ctrl_alert_test.4141874565
/workspace/coverage/default/5.sram_ctrl_bijection.3221090086
/workspace/coverage/default/5.sram_ctrl_executable.3107213726
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3386848511
/workspace/coverage/default/5.sram_ctrl_max_throughput.3584158163
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1914908714
/workspace/coverage/default/5.sram_ctrl_mem_walk.2282291336
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1653952159
/workspace/coverage/default/5.sram_ctrl_partial_access.3939793869
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4043228267
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3165390485
/workspace/coverage/default/5.sram_ctrl_regwen.3114846883
/workspace/coverage/default/5.sram_ctrl_smoke.344345577
/workspace/coverage/default/5.sram_ctrl_stress_all.2323474196
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.314304273
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.103834032
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1654972505
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.245824916
/workspace/coverage/default/6.sram_ctrl_alert_test.243404537
/workspace/coverage/default/6.sram_ctrl_bijection.971799401
/workspace/coverage/default/6.sram_ctrl_executable.3981613767
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3769882663
/workspace/coverage/default/6.sram_ctrl_max_throughput.1132804288
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.218446185
/workspace/coverage/default/6.sram_ctrl_mem_walk.677145665
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1692428115
/workspace/coverage/default/6.sram_ctrl_partial_access.1266260333
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2840001996
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1771118090
/workspace/coverage/default/6.sram_ctrl_regwen.2357753692
/workspace/coverage/default/6.sram_ctrl_smoke.1954529147
/workspace/coverage/default/6.sram_ctrl_stress_all.663905710
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.823615667
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2053149966
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3099491116
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1151643392
/workspace/coverage/default/7.sram_ctrl_alert_test.2538469593
/workspace/coverage/default/7.sram_ctrl_bijection.2480864955
/workspace/coverage/default/7.sram_ctrl_executable.761639846
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3317724954
/workspace/coverage/default/7.sram_ctrl_max_throughput.40510427
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2932753383
/workspace/coverage/default/7.sram_ctrl_mem_walk.2895007293
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1036070631
/workspace/coverage/default/7.sram_ctrl_partial_access.1357310570
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3352492888
/workspace/coverage/default/7.sram_ctrl_ram_cfg.921647184
/workspace/coverage/default/7.sram_ctrl_regwen.317840997
/workspace/coverage/default/7.sram_ctrl_smoke.3423581135
/workspace/coverage/default/7.sram_ctrl_stress_all.260851815
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1802495636
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1680058582
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3845175946
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1795549863
/workspace/coverage/default/8.sram_ctrl_alert_test.79230379
/workspace/coverage/default/8.sram_ctrl_bijection.3788188705
/workspace/coverage/default/8.sram_ctrl_executable.319801526
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1421463087
/workspace/coverage/default/8.sram_ctrl_max_throughput.1947348570
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3439442028
/workspace/coverage/default/8.sram_ctrl_mem_walk.244790034
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3791239429
/workspace/coverage/default/8.sram_ctrl_partial_access.3238539433
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4273217851
/workspace/coverage/default/8.sram_ctrl_ram_cfg.724503577
/workspace/coverage/default/8.sram_ctrl_regwen.2800181258
/workspace/coverage/default/8.sram_ctrl_smoke.286624502
/workspace/coverage/default/8.sram_ctrl_stress_all.3455689779
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3467503209
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4253129060
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2461806305
/workspace/coverage/default/9.sram_ctrl_alert_test.1022912252
/workspace/coverage/default/9.sram_ctrl_bijection.2422474500
/workspace/coverage/default/9.sram_ctrl_executable.3820929220
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1947830468
/workspace/coverage/default/9.sram_ctrl_max_throughput.602414040
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1042816143
/workspace/coverage/default/9.sram_ctrl_mem_walk.3892163445
/workspace/coverage/default/9.sram_ctrl_multiple_keys.682518923
/workspace/coverage/default/9.sram_ctrl_partial_access.410382942
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.892198096
/workspace/coverage/default/9.sram_ctrl_ram_cfg.234748515
/workspace/coverage/default/9.sram_ctrl_regwen.2614787514
/workspace/coverage/default/9.sram_ctrl_smoke.2243268874
/workspace/coverage/default/9.sram_ctrl_stress_all.438676180
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.982903556
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2868818175
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.907160848



Total test records in report: 1033
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2370830219 May 02 01:51:57 PM PDT 24 May 02 01:53:13 PM PDT 24 2449994246 ps
T2 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1294214814 May 02 01:56:46 PM PDT 24 May 02 01:57:45 PM PDT 24 8786252105 ps
T3 /workspace/coverage/default/26.sram_ctrl_partial_access.2443043945 May 02 01:53:09 PM PDT 24 May 02 01:53:55 PM PDT 24 2847069346 ps
T7 /workspace/coverage/default/26.sram_ctrl_smoke.2009593834 May 02 01:53:27 PM PDT 24 May 02 01:53:34 PM PDT 24 1667694071 ps
T8 /workspace/coverage/default/17.sram_ctrl_bijection.3079708335 May 02 01:52:10 PM PDT 24 May 02 02:26:49 PM PDT 24 131112666939 ps
T9 /workspace/coverage/default/14.sram_ctrl_alert_test.1657373553 May 02 01:52:11 PM PDT 24 May 02 01:52:13 PM PDT 24 16365951 ps
T10 /workspace/coverage/default/38.sram_ctrl_alert_test.4035499777 May 02 01:55:07 PM PDT 24 May 02 01:55:09 PM PDT 24 16235386 ps
T11 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2457598289 May 02 01:51:26 PM PDT 24 May 02 01:57:19 PM PDT 24 6009927212 ps
T12 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.69078902 May 02 01:52:34 PM PDT 24 May 02 01:58:14 PM PDT 24 10735338014 ps
T13 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2868818175 May 02 01:51:45 PM PDT 24 May 02 01:54:41 PM PDT 24 11468713552 ps
T17 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2348820415 May 02 01:53:54 PM PDT 24 May 02 01:56:38 PM PDT 24 791576665 ps
T18 /workspace/coverage/default/38.sram_ctrl_executable.3822678868 May 02 01:54:51 PM PDT 24 May 02 02:08:53 PM PDT 24 14177040515 ps
T25 /workspace/coverage/default/22.sram_ctrl_alert_test.1025443916 May 02 01:52:42 PM PDT 24 May 02 01:52:44 PM PDT 24 22711835 ps
T19 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1127269981 May 02 01:56:00 PM PDT 24 May 02 01:58:29 PM PDT 24 4529744673 ps
T21 /workspace/coverage/default/20.sram_ctrl_executable.1954191488 May 02 01:52:28 PM PDT 24 May 02 02:14:09 PM PDT 24 18435207649 ps
T92 /workspace/coverage/default/22.sram_ctrl_multiple_keys.282142725 May 02 01:52:30 PM PDT 24 May 02 01:54:02 PM PDT 24 8726864921 ps
T31 /workspace/coverage/default/12.sram_ctrl_executable.2664639119 May 02 01:51:57 PM PDT 24 May 02 01:54:31 PM PDT 24 8949289047 ps
T20 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.4157767194 May 02 01:51:56 PM PDT 24 May 02 01:55:35 PM PDT 24 6650866764 ps
T73 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1684468996 May 02 01:54:12 PM PDT 24 May 02 01:55:16 PM PDT 24 1929137363 ps
T137 /workspace/coverage/default/14.sram_ctrl_mem_walk.2404595324 May 02 01:52:08 PM PDT 24 May 02 01:54:10 PM PDT 24 16439328168 ps
T26 /workspace/coverage/default/41.sram_ctrl_bijection.1780197514 May 02 01:55:16 PM PDT 24 May 02 02:24:03 PM PDT 24 163202179085 ps
T4 /workspace/coverage/default/5.sram_ctrl_lc_escalation.3386848511 May 02 01:51:37 PM PDT 24 May 02 01:52:33 PM PDT 24 8621673823 ps
T59 /workspace/coverage/default/32.sram_ctrl_bijection.22896890 May 02 01:53:46 PM PDT 24 May 02 02:21:36 PM PDT 24 77627423895 ps
T60 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1739865544 May 02 01:54:46 PM PDT 24 May 02 01:55:01 PM PDT 24 717658055 ps
T5 /workspace/coverage/default/32.sram_ctrl_lc_escalation.2308362677 May 02 01:53:54 PM PDT 24 May 02 01:54:31 PM PDT 24 36325539112 ps
T61 /workspace/coverage/default/6.sram_ctrl_partial_access.1266260333 May 02 01:51:39 PM PDT 24 May 02 01:52:01 PM PDT 24 956031771 ps
T14 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2644529758 May 02 01:55:18 PM PDT 24 May 02 02:04:09 PM PDT 24 162525918585 ps
T16 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.72390631 May 02 01:53:25 PM PDT 24 May 02 01:53:44 PM PDT 24 1358949585 ps
T32 /workspace/coverage/default/29.sram_ctrl_ram_cfg.523478267 May 02 01:53:25 PM PDT 24 May 02 01:53:31 PM PDT 24 712845684 ps
T46 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3380147969 May 02 01:56:11 PM PDT 24 May 02 02:16:34 PM PDT 24 14825209548 ps
T62 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.4038281550 May 02 01:52:46 PM PDT 24 May 02 01:57:56 PM PDT 24 5272545663 ps
T113 /workspace/coverage/default/29.sram_ctrl_partial_access.64338483 May 02 01:53:39 PM PDT 24 May 02 01:54:08 PM PDT 24 7456349401 ps
T30 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1587049899 May 02 01:53:49 PM PDT 24 May 02 01:55:19 PM PDT 24 3347224371 ps
T33 /workspace/coverage/default/3.sram_ctrl_ram_cfg.1375772446 May 02 01:51:32 PM PDT 24 May 02 01:51:36 PM PDT 24 1411126047 ps
T49 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2007514380 May 02 01:53:00 PM PDT 24 May 02 01:53:17 PM PDT 24 2255589606 ps
T114 /workspace/coverage/default/45.sram_ctrl_bijection.401383595 May 02 01:56:04 PM PDT 24 May 02 02:10:51 PM PDT 24 80885022235 ps
T15 /workspace/coverage/default/44.sram_ctrl_executable.3896427596 May 02 01:55:56 PM PDT 24 May 02 02:20:56 PM PDT 24 23769757132 ps
T97 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2690231157 May 02 01:53:22 PM PDT 24 May 02 01:59:02 PM PDT 24 17074911318 ps
T47 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.897349597 May 02 01:51:25 PM PDT 24 May 02 02:16:28 PM PDT 24 17645589289 ps
T27 /workspace/coverage/default/27.sram_ctrl_regwen.3366613894 May 02 01:53:14 PM PDT 24 May 02 01:53:40 PM PDT 24 5068595556 ps
T98 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.4082202990 May 02 01:56:33 PM PDT 24 May 02 02:01:21 PM PDT 24 5333192551 ps
T6 /workspace/coverage/default/11.sram_ctrl_stress_all.3730920058 May 02 01:51:56 PM PDT 24 May 02 03:42:35 PM PDT 24 778565244519 ps
T78 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.182937835 May 02 01:52:35 PM PDT 24 May 02 02:02:13 PM PDT 24 45988662105 ps
T28 /workspace/coverage/default/36.sram_ctrl_stress_all.2613192073 May 02 01:54:35 PM PDT 24 May 02 02:47:12 PM PDT 24 101935804637 ps
T48 /workspace/coverage/default/24.sram_ctrl_regwen.1510727506 May 02 01:52:49 PM PDT 24 May 02 01:55:06 PM PDT 24 54862286019 ps
T138 /workspace/coverage/default/31.sram_ctrl_max_throughput.3490493694 May 02 01:53:39 PM PDT 24 May 02 01:53:55 PM PDT 24 759530515 ps
T50 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2087479172 May 02 01:51:54 PM PDT 24 May 02 01:52:14 PM PDT 24 1267633804 ps
T132 /workspace/coverage/default/7.sram_ctrl_executable.761639846 May 02 01:51:48 PM PDT 24 May 02 02:00:57 PM PDT 24 26917337158 ps
T51 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1097638957 May 02 01:55:03 PM PDT 24 May 02 01:56:07 PM PDT 24 4131175511 ps
T52 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2299396391 May 02 01:55:24 PM PDT 24 May 02 01:55:34 PM PDT 24 1002363553 ps
T139 /workspace/coverage/default/23.sram_ctrl_max_throughput.1220912329 May 02 01:52:36 PM PDT 24 May 02 01:53:06 PM PDT 24 3286855691 ps
T34 /workspace/coverage/default/28.sram_ctrl_ram_cfg.3807147435 May 02 01:53:26 PM PDT 24 May 02 01:53:32 PM PDT 24 2102958029 ps
T140 /workspace/coverage/default/19.sram_ctrl_smoke.4073643710 May 02 01:52:18 PM PDT 24 May 02 01:52:32 PM PDT 24 1904116982 ps
T79 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.54430537 May 02 01:51:36 PM PDT 24 May 02 01:54:02 PM PDT 24 4685837342 ps
T56 /workspace/coverage/default/10.sram_ctrl_lc_escalation.2991138029 May 02 01:51:46 PM PDT 24 May 02 01:52:29 PM PDT 24 13107735835 ps
T133 /workspace/coverage/default/15.sram_ctrl_multiple_keys.1972515786 May 02 01:52:06 PM PDT 24 May 02 02:15:10 PM PDT 24 27496211687 ps
T141 /workspace/coverage/default/23.sram_ctrl_alert_test.3393825618 May 02 01:52:46 PM PDT 24 May 02 01:52:48 PM PDT 24 30326898 ps
T29 /workspace/coverage/default/8.sram_ctrl_stress_all.3455689779 May 02 01:51:44 PM PDT 24 May 02 02:21:43 PM PDT 24 21123291212 ps
T142 /workspace/coverage/default/20.sram_ctrl_alert_test.692459219 May 02 01:52:35 PM PDT 24 May 02 01:52:38 PM PDT 24 21298516 ps
T143 /workspace/coverage/default/39.sram_ctrl_multiple_keys.2694446409 May 02 01:55:07 PM PDT 24 May 02 02:12:30 PM PDT 24 20612869497 ps
T80 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2866635341 May 02 01:51:19 PM PDT 24 May 02 01:52:38 PM PDT 24 9055166228 ps
T57 /workspace/coverage/default/47.sram_ctrl_lc_escalation.3567141974 May 02 01:56:43 PM PDT 24 May 02 01:58:06 PM PDT 24 13647753159 ps
T144 /workspace/coverage/default/49.sram_ctrl_bijection.3899977366 May 02 01:56:55 PM PDT 24 May 02 02:22:22 PM PDT 24 43564203356 ps
T145 /workspace/coverage/default/9.sram_ctrl_partial_access.410382942 May 02 01:51:45 PM PDT 24 May 02 01:52:07 PM PDT 24 1281295221 ps
T146 /workspace/coverage/default/12.sram_ctrl_bijection.279503890 May 02 01:51:55 PM PDT 24 May 02 02:19:33 PM PDT 24 460980576429 ps
T147 /workspace/coverage/default/47.sram_ctrl_ram_cfg.4212738819 May 02 01:56:43 PM PDT 24 May 02 01:56:48 PM PDT 24 737271088 ps
T58 /workspace/coverage/default/49.sram_ctrl_lc_escalation.1724703340 May 02 01:57:06 PM PDT 24 May 02 01:58:18 PM PDT 24 55577028745 ps
T127 /workspace/coverage/default/40.sram_ctrl_executable.3083312461 May 02 01:55:16 PM PDT 24 May 02 02:00:21 PM PDT 24 45901000100 ps
T148 /workspace/coverage/default/36.sram_ctrl_lc_escalation.2686503874 May 02 01:54:37 PM PDT 24 May 02 01:55:16 PM PDT 24 42046174612 ps
T128 /workspace/coverage/default/32.sram_ctrl_regwen.379118205 May 02 01:53:54 PM PDT 24 May 02 02:15:17 PM PDT 24 25195653709 ps
T149 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.327504483 May 02 01:51:28 PM PDT 24 May 02 01:51:44 PM PDT 24 2699743868 ps
T150 /workspace/coverage/default/0.sram_ctrl_partial_access.1669823241 May 02 01:51:26 PM PDT 24 May 02 01:52:49 PM PDT 24 3361835936 ps
T151 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.644944761 May 02 01:51:36 PM PDT 24 May 02 01:55:04 PM PDT 24 10792587294 ps
T129 /workspace/coverage/default/18.sram_ctrl_regwen.2645212721 May 02 01:52:18 PM PDT 24 May 02 02:08:49 PM PDT 24 11303121906 ps
T131 /workspace/coverage/default/5.sram_ctrl_executable.3107213726 May 02 01:51:40 PM PDT 24 May 02 01:53:41 PM PDT 24 6360645714 ps
T152 /workspace/coverage/default/35.sram_ctrl_max_throughput.1516259301 May 02 01:54:23 PM PDT 24 May 02 01:54:31 PM PDT 24 13338354704 ps
T153 /workspace/coverage/default/22.sram_ctrl_bijection.2018687634 May 02 01:52:35 PM PDT 24 May 02 02:32:51 PM PDT 24 113869460423 ps
T154 /workspace/coverage/default/42.sram_ctrl_max_throughput.544808844 May 02 01:55:31 PM PDT 24 May 02 01:57:05 PM PDT 24 3889464828 ps
T155 /workspace/coverage/default/1.sram_ctrl_max_throughput.1102354882 May 02 01:51:27 PM PDT 24 May 02 01:52:17 PM PDT 24 8060514689 ps
T81 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.3014939532 May 02 01:55:16 PM PDT 24 May 02 01:57:22 PM PDT 24 6456561229 ps
T156 /workspace/coverage/default/6.sram_ctrl_lc_escalation.3769882663 May 02 01:51:38 PM PDT 24 May 02 01:52:43 PM PDT 24 46876109322 ps
T157 /workspace/coverage/default/37.sram_ctrl_alert_test.1414191505 May 02 01:54:54 PM PDT 24 May 02 01:54:56 PM PDT 24 166711328 ps
T158 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.405564890 May 02 01:53:01 PM PDT 24 May 02 01:53:24 PM PDT 24 730951372 ps
T159 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1800456267 May 02 01:54:52 PM PDT 24 May 02 02:15:00 PM PDT 24 19316128108 ps
T160 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2105764217 May 02 01:52:36 PM PDT 24 May 02 01:57:49 PM PDT 24 20887144293 ps
T161 /workspace/coverage/default/22.sram_ctrl_ram_cfg.222931788 May 02 01:52:37 PM PDT 24 May 02 01:52:42 PM PDT 24 355548455 ps
T162 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2816188192 May 02 01:55:14 PM PDT 24 May 02 01:57:16 PM PDT 24 1599384482 ps
T163 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.403285912 May 02 01:51:55 PM PDT 24 May 02 01:57:20 PM PDT 24 5305369633 ps
T164 /workspace/coverage/default/28.sram_ctrl_stress_all.2697227613 May 02 01:53:19 PM PDT 24 May 02 02:23:58 PM PDT 24 179241352995 ps
T165 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.334962137 May 02 01:55:39 PM PDT 24 May 02 01:56:44 PM PDT 24 2380088027 ps
T166 /workspace/coverage/default/8.sram_ctrl_partial_access.3238539433 May 02 01:51:45 PM PDT 24 May 02 01:52:03 PM PDT 24 1658106318 ps
T167 /workspace/coverage/default/29.sram_ctrl_mem_walk.3033371059 May 02 01:53:26 PM PDT 24 May 02 01:57:29 PM PDT 24 8044066563 ps
T53 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2399568816 May 02 01:52:05 PM PDT 24 May 02 01:52:44 PM PDT 24 2565261621 ps
T130 /workspace/coverage/default/8.sram_ctrl_regwen.2800181258 May 02 01:51:43 PM PDT 24 May 02 02:09:50 PM PDT 24 9328991071 ps
T168 /workspace/coverage/default/46.sram_ctrl_smoke.4286651372 May 02 01:56:11 PM PDT 24 May 02 01:56:55 PM PDT 24 2736121054 ps
T169 /workspace/coverage/default/31.sram_ctrl_ram_cfg.1374252770 May 02 01:53:41 PM PDT 24 May 02 01:53:46 PM PDT 24 360020362 ps
T170 /workspace/coverage/default/18.sram_ctrl_lc_escalation.578791761 May 02 01:52:15 PM PDT 24 May 02 01:53:06 PM PDT 24 47598941970 ps
T171 /workspace/coverage/default/10.sram_ctrl_multiple_keys.3909673258 May 02 01:51:49 PM PDT 24 May 02 01:55:15 PM PDT 24 9024275066 ps
T172 /workspace/coverage/default/46.sram_ctrl_alert_test.1432228089 May 02 01:56:25 PM PDT 24 May 02 01:56:27 PM PDT 24 21838851 ps
T173 /workspace/coverage/default/9.sram_ctrl_alert_test.1022912252 May 02 01:51:45 PM PDT 24 May 02 01:51:47 PM PDT 24 37202713 ps
T134 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.722388405 May 02 01:52:36 PM PDT 24 May 02 01:59:38 PM PDT 24 65340174830 ps
T174 /workspace/coverage/default/13.sram_ctrl_max_throughput.514738871 May 02 01:51:53 PM PDT 24 May 02 01:53:43 PM PDT 24 3055145819 ps
T175 /workspace/coverage/default/36.sram_ctrl_mem_walk.259693843 May 02 01:54:34 PM PDT 24 May 02 01:59:55 PM PDT 24 42156670846 ps
T54 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.4099037366 May 02 01:52:18 PM PDT 24 May 02 01:52:36 PM PDT 24 12374453196 ps
T176 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1914908714 May 02 01:51:35 PM PDT 24 May 02 01:53:01 PM PDT 24 4907998805 ps
T177 /workspace/coverage/default/40.sram_ctrl_ram_cfg.1489855400 May 02 01:55:18 PM PDT 24 May 02 01:55:24 PM PDT 24 6691853647 ps
T178 /workspace/coverage/default/34.sram_ctrl_smoke.2014113537 May 02 01:54:11 PM PDT 24 May 02 01:54:25 PM PDT 24 4395534154 ps
T179 /workspace/coverage/default/27.sram_ctrl_mem_walk.3540082098 May 02 01:53:19 PM PDT 24 May 02 01:55:58 PM PDT 24 21545767905 ps
T180 /workspace/coverage/default/6.sram_ctrl_regwen.2357753692 May 02 01:51:37 PM PDT 24 May 02 01:57:23 PM PDT 24 33204087194 ps
T181 /workspace/coverage/default/39.sram_ctrl_lc_escalation.716086628 May 02 01:55:10 PM PDT 24 May 02 01:56:34 PM PDT 24 13181101354 ps
T182 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.1169313356 May 02 01:54:50 PM PDT 24 May 02 01:58:51 PM PDT 24 24291418347 ps
T183 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1775257171 May 02 01:51:54 PM PDT 24 May 02 02:05:36 PM PDT 24 34234689258 ps
T136 /workspace/coverage/default/27.sram_ctrl_stress_all.2295959725 May 02 01:53:18 PM PDT 24 May 02 02:52:39 PM PDT 24 104500550200 ps
T184 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3833716060 May 02 01:55:48 PM PDT 24 May 02 02:11:02 PM PDT 24 12350251700 ps
T185 /workspace/coverage/default/20.sram_ctrl_lc_escalation.3100979008 May 02 01:52:34 PM PDT 24 May 02 01:53:50 PM PDT 24 46761837980 ps
T186 /workspace/coverage/default/14.sram_ctrl_regwen.1902888362 May 02 01:52:05 PM PDT 24 May 02 02:10:29 PM PDT 24 20218955427 ps
T187 /workspace/coverage/default/40.sram_ctrl_lc_escalation.3187407146 May 02 01:55:10 PM PDT 24 May 02 01:56:17 PM PDT 24 37606205520 ps
T188 /workspace/coverage/default/44.sram_ctrl_smoke.2260493560 May 02 01:55:57 PM PDT 24 May 02 01:56:22 PM PDT 24 3372894341 ps
T189 /workspace/coverage/default/7.sram_ctrl_multiple_keys.1036070631 May 02 01:51:39 PM PDT 24 May 02 02:12:34 PM PDT 24 90405894104 ps
T190 /workspace/coverage/default/22.sram_ctrl_partial_access.1461687191 May 02 01:52:26 PM PDT 24 May 02 01:54:41 PM PDT 24 953954392 ps
T191 /workspace/coverage/default/15.sram_ctrl_mem_walk.1790759865 May 02 01:52:11 PM PDT 24 May 02 01:56:15 PM PDT 24 4108345412 ps
T192 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3019952858 May 02 01:52:02 PM PDT 24 May 02 01:59:23 PM PDT 24 22971700431 ps
T193 /workspace/coverage/default/30.sram_ctrl_multiple_keys.3244164425 May 02 01:53:25 PM PDT 24 May 02 02:12:21 PM PDT 24 82158013318 ps
T194 /workspace/coverage/default/41.sram_ctrl_mem_walk.3354204367 May 02 01:55:22 PM PDT 24 May 02 01:57:53 PM PDT 24 13516108951 ps
T195 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3467331268 May 02 01:51:38 PM PDT 24 May 02 02:06:43 PM PDT 24 10026800239 ps
T55 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1410661719 May 02 01:52:15 PM PDT 24 May 02 01:52:40 PM PDT 24 786244469 ps
T196 /workspace/coverage/default/41.sram_ctrl_multiple_keys.566414519 May 02 01:55:17 PM PDT 24 May 02 02:24:55 PM PDT 24 88629651407 ps
T197 /workspace/coverage/default/46.sram_ctrl_bijection.3652251339 May 02 01:56:20 PM PDT 24 May 02 02:30:23 PM PDT 24 828272156889 ps
T198 /workspace/coverage/default/29.sram_ctrl_smoke.3096644957 May 02 01:53:26 PM PDT 24 May 02 01:53:36 PM PDT 24 575214687 ps
T199 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.2339354347 May 02 01:54:29 PM PDT 24 May 02 02:00:38 PM PDT 24 25313059588 ps
T200 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3265002912 May 02 01:51:55 PM PDT 24 May 02 02:02:52 PM PDT 24 43208969539 ps
T105 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3986392698 May 02 01:55:15 PM PDT 24 May 02 01:55:48 PM PDT 24 2854540135 ps
T201 /workspace/coverage/default/28.sram_ctrl_bijection.2198233918 May 02 01:53:16 PM PDT 24 May 02 02:32:22 PM PDT 24 530303919804 ps
T202 /workspace/coverage/default/28.sram_ctrl_executable.2794840627 May 02 01:53:16 PM PDT 24 May 02 02:04:40 PM PDT 24 57015355507 ps
T203 /workspace/coverage/default/27.sram_ctrl_lc_escalation.587809042 May 02 01:53:10 PM PDT 24 May 02 01:54:12 PM PDT 24 10212064457 ps
T204 /workspace/coverage/default/21.sram_ctrl_regwen.3754764371 May 02 01:52:34 PM PDT 24 May 02 01:52:51 PM PDT 24 1686818533 ps
T205 /workspace/coverage/default/27.sram_ctrl_max_throughput.900092439 May 02 01:53:09 PM PDT 24 May 02 01:55:10 PM PDT 24 1522884280 ps
T206 /workspace/coverage/default/0.sram_ctrl_executable.3727300346 May 02 01:51:23 PM PDT 24 May 02 01:57:13 PM PDT 24 51933385800 ps
T207 /workspace/coverage/default/7.sram_ctrl_bijection.2480864955 May 02 01:51:37 PM PDT 24 May 02 02:20:30 PM PDT 24 107918241011 ps
T208 /workspace/coverage/default/6.sram_ctrl_alert_test.243404537 May 02 01:51:38 PM PDT 24 May 02 01:51:40 PM PDT 24 13893388 ps
T209 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.1655210199 May 02 01:53:16 PM PDT 24 May 02 01:55:43 PM PDT 24 16751901101 ps
T210 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3336151208 May 02 01:52:10 PM PDT 24 May 02 01:58:40 PM PDT 24 7168617200 ps
T211 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1721151471 May 02 01:55:41 PM PDT 24 May 02 02:17:34 PM PDT 24 28738107678 ps
T212 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1667756220 May 02 01:54:19 PM PDT 24 May 02 01:56:19 PM PDT 24 1647649925 ps
T213 /workspace/coverage/default/25.sram_ctrl_alert_test.1369000451 May 02 01:52:59 PM PDT 24 May 02 01:53:01 PM PDT 24 13203642 ps
T214 /workspace/coverage/default/8.sram_ctrl_lc_escalation.1421463087 May 02 01:51:50 PM PDT 24 May 02 01:53:39 PM PDT 24 17067249834 ps
T215 /workspace/coverage/default/21.sram_ctrl_lc_escalation.3440510436 May 02 01:52:26 PM PDT 24 May 02 01:53:15 PM PDT 24 7420546928 ps
T216 /workspace/coverage/default/13.sram_ctrl_alert_test.4233202074 May 02 01:52:06 PM PDT 24 May 02 01:52:09 PM PDT 24 23901173 ps
T217 /workspace/coverage/default/45.sram_ctrl_regwen.981982999 May 02 01:56:12 PM PDT 24 May 02 02:19:21 PM PDT 24 30465113571 ps
T218 /workspace/coverage/default/15.sram_ctrl_bijection.730823740 May 02 01:52:06 PM PDT 24 May 02 02:15:33 PM PDT 24 66731057301 ps
T219 /workspace/coverage/default/32.sram_ctrl_multiple_keys.2222207160 May 02 01:53:48 PM PDT 24 May 02 02:11:07 PM PDT 24 84914726941 ps
T220 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.4105395179 May 02 01:52:07 PM PDT 24 May 02 01:54:32 PM PDT 24 9792915852 ps
T221 /workspace/coverage/default/41.sram_ctrl_executable.1501172441 May 02 01:55:24 PM PDT 24 May 02 02:01:42 PM PDT 24 3480782573 ps
T222 /workspace/coverage/default/38.sram_ctrl_smoke.1087259347 May 02 01:54:51 PM PDT 24 May 02 01:55:00 PM PDT 24 416530497 ps
T223 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.695835933 May 02 01:52:48 PM PDT 24 May 02 01:56:02 PM PDT 24 24901764671 ps
T224 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.1494788645 May 02 01:51:30 PM PDT 24 May 02 02:21:30 PM PDT 24 255925046028 ps
T225 /workspace/coverage/default/33.sram_ctrl_multiple_keys.2602694007 May 02 01:54:03 PM PDT 24 May 02 02:11:44 PM PDT 24 15269746002 ps
T226 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3324440719 May 02 01:51:57 PM PDT 24 May 02 01:54:34 PM PDT 24 5139407230 ps
T227 /workspace/coverage/default/40.sram_ctrl_partial_access.1194697917 May 02 01:55:07 PM PDT 24 May 02 01:55:30 PM PDT 24 1495681392 ps
T228 /workspace/coverage/default/13.sram_ctrl_multiple_keys.3767496813 May 02 01:51:56 PM PDT 24 May 02 02:11:06 PM PDT 24 28917625330 ps
T229 /workspace/coverage/default/40.sram_ctrl_smoke.2399800352 May 02 01:55:08 PM PDT 24 May 02 01:55:18 PM PDT 24 1418959565 ps
T230 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3900443611 May 02 01:56:42 PM PDT 24 May 02 02:05:20 PM PDT 24 18066569545 ps
T231 /workspace/coverage/default/11.sram_ctrl_ram_cfg.904863153 May 02 01:51:57 PM PDT 24 May 02 01:52:02 PM PDT 24 1535202195 ps
T232 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.335981470 May 02 01:54:03 PM PDT 24 May 02 01:55:36 PM PDT 24 757850861 ps
T233 /workspace/coverage/default/42.sram_ctrl_executable.1458823011 May 02 01:55:39 PM PDT 24 May 02 02:03:08 PM PDT 24 6671924358 ps
T234 /workspace/coverage/default/35.sram_ctrl_executable.1108484742 May 02 01:54:34 PM PDT 24 May 02 02:11:14 PM PDT 24 15916595585 ps
T235 /workspace/coverage/default/0.sram_ctrl_smoke.199550476 May 02 01:51:19 PM PDT 24 May 02 01:51:36 PM PDT 24 1037910791 ps
T236 /workspace/coverage/default/46.sram_ctrl_max_throughput.3030134582 May 02 01:56:20 PM PDT 24 May 02 01:56:43 PM PDT 24 1416168175 ps
T237 /workspace/coverage/default/37.sram_ctrl_bijection.2272133521 May 02 01:54:43 PM PDT 24 May 02 02:31:06 PM PDT 24 196029112123 ps
T238 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2176096963 May 02 01:52:07 PM PDT 24 May 02 01:52:27 PM PDT 24 1836854965 ps
T239 /workspace/coverage/default/8.sram_ctrl_alert_test.79230379 May 02 01:51:50 PM PDT 24 May 02 01:51:51 PM PDT 24 38390283 ps
T240 /workspace/coverage/default/12.sram_ctrl_regwen.4104084222 May 02 01:51:56 PM PDT 24 May 02 02:04:00 PM PDT 24 17531419970 ps
T241 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.103834032 May 02 01:51:39 PM PDT 24 May 02 01:54:47 PM PDT 24 6782113669 ps
T242 /workspace/coverage/default/1.sram_ctrl_regwen.2927145301 May 02 01:51:37 PM PDT 24 May 02 02:04:58 PM PDT 24 13318900483 ps
T135 /workspace/coverage/default/24.sram_ctrl_stress_all.733516761 May 02 01:52:47 PM PDT 24 May 02 04:14:30 PM PDT 24 94619632354 ps
T243 /workspace/coverage/default/43.sram_ctrl_executable.257281110 May 02 01:55:46 PM PDT 24 May 02 02:14:56 PM PDT 24 32710789661 ps
T244 /workspace/coverage/default/2.sram_ctrl_executable.1203345916 May 02 01:51:31 PM PDT 24 May 02 01:57:59 PM PDT 24 29814522773 ps
T245 /workspace/coverage/default/34.sram_ctrl_bijection.2003876908 May 02 01:54:14 PM PDT 24 May 02 02:35:27 PM PDT 24 216232335811 ps
T246 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2519331496 May 02 01:55:30 PM PDT 24 May 02 02:01:48 PM PDT 24 7063318014 ps
T247 /workspace/coverage/default/46.sram_ctrl_partial_access.3532836489 May 02 01:56:22 PM PDT 24 May 02 01:56:35 PM PDT 24 524883399 ps
T248 /workspace/coverage/default/17.sram_ctrl_multiple_keys.786433847 May 02 01:52:10 PM PDT 24 May 02 02:03:08 PM PDT 24 45889297018 ps
T249 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3421544164 May 02 01:52:08 PM PDT 24 May 02 01:58:56 PM PDT 24 61745551659 ps
T250 /workspace/coverage/default/13.sram_ctrl_bijection.2018475389 May 02 01:51:58 PM PDT 24 May 02 02:30:15 PM PDT 24 105479021632 ps
T251 /workspace/coverage/default/18.sram_ctrl_mem_walk.1917622008 May 02 01:52:16 PM PDT 24 May 02 01:56:50 PM PDT 24 14650916144 ps
T252 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.1593120321 May 02 01:52:26 PM PDT 24 May 02 01:53:48 PM PDT 24 23455758219 ps
T253 /workspace/coverage/default/33.sram_ctrl_alert_test.3776453709 May 02 01:54:13 PM PDT 24 May 02 01:54:15 PM PDT 24 19853028 ps
T254 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3099491116 May 02 01:51:39 PM PDT 24 May 02 01:52:18 PM PDT 24 736920777 ps
T255 /workspace/coverage/default/42.sram_ctrl_alert_test.1841500827 May 02 01:55:39 PM PDT 24 May 02 01:55:40 PM PDT 24 61284139 ps
T256 /workspace/coverage/default/46.sram_ctrl_regwen.2446510513 May 02 01:56:26 PM PDT 24 May 02 02:13:56 PM PDT 24 66849427432 ps
T257 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3765776710 May 02 01:53:54 PM PDT 24 May 02 01:57:06 PM PDT 24 3137120281 ps
T258 /workspace/coverage/default/10.sram_ctrl_bijection.1313319719 May 02 01:51:46 PM PDT 24 May 02 02:00:54 PM PDT 24 46519156055 ps
T259 /workspace/coverage/default/13.sram_ctrl_regwen.559845468 May 02 01:51:56 PM PDT 24 May 02 02:01:28 PM PDT 24 2462382624 ps
T260 /workspace/coverage/default/32.sram_ctrl_executable.1892288507 May 02 01:53:54 PM PDT 24 May 02 02:13:52 PM PDT 24 144123321174 ps
T261 /workspace/coverage/default/47.sram_ctrl_bijection.2705138821 May 02 01:56:32 PM PDT 24 May 02 02:21:15 PM PDT 24 352926915855 ps
T262 /workspace/coverage/default/45.sram_ctrl_executable.4003886726 May 02 01:56:09 PM PDT 24 May 02 02:08:59 PM PDT 24 28432029705 ps
T263 /workspace/coverage/default/19.sram_ctrl_mem_walk.3264539959 May 02 01:52:15 PM PDT 24 May 02 01:56:12 PM PDT 24 4107119604 ps
T264 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.4025680174 May 02 01:54:53 PM PDT 24 May 02 01:57:43 PM PDT 24 1650155109 ps
T265 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3574067110 May 02 01:57:06 PM PDT 24 May 02 02:03:21 PM PDT 24 17396490992 ps
T266 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1464728670 May 02 01:52:14 PM PDT 24 May 02 01:57:17 PM PDT 24 13762221617 ps
T115 /workspace/coverage/default/26.sram_ctrl_stress_all.1178126270 May 02 01:53:12 PM PDT 24 May 02 03:34:53 PM PDT 24 643352354291 ps
T267 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2053149966 May 02 01:51:36 PM PDT 24 May 02 01:55:51 PM PDT 24 8301907896 ps
T268 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.218446185 May 02 01:51:38 PM PDT 24 May 02 01:54:06 PM PDT 24 10363482239 ps
T269 /workspace/coverage/default/10.sram_ctrl_mem_walk.664718757 May 02 01:51:54 PM PDT 24 May 02 01:54:25 PM PDT 24 27576346587 ps
T270 /workspace/coverage/default/16.sram_ctrl_alert_test.3824959536 May 02 01:52:12 PM PDT 24 May 02 01:52:14 PM PDT 24 39252089 ps
T271 /workspace/coverage/default/20.sram_ctrl_mem_walk.2003334210 May 02 01:52:35 PM PDT 24 May 02 01:57:57 PM PDT 24 21734582828 ps
T106 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3793346705 May 02 01:53:15 PM PDT 24 May 02 01:53:34 PM PDT 24 2777351926 ps
T272 /workspace/coverage/default/24.sram_ctrl_mem_walk.3686574428 May 02 01:52:48 PM PDT 24 May 02 01:57:28 PM PDT 24 78796690475 ps
T273 /workspace/coverage/default/39.sram_ctrl_stress_all.198607221 May 02 01:55:10 PM PDT 24 May 02 03:07:48 PM PDT 24 191880318730 ps
T274 /workspace/coverage/default/38.sram_ctrl_ram_cfg.2322010055 May 02 01:54:58 PM PDT 24 May 02 01:55:02 PM PDT 24 360772834 ps
T275 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.4041395678 May 02 01:55:09 PM PDT 24 May 02 01:57:18 PM PDT 24 805947325 ps
T276 /workspace/coverage/default/22.sram_ctrl_max_throughput.3720454276 May 02 01:52:35 PM PDT 24 May 02 01:55:04 PM PDT 24 800296574 ps
T277 /workspace/coverage/default/36.sram_ctrl_multiple_keys.2518056947 May 02 01:54:31 PM PDT 24 May 02 02:19:58 PM PDT 24 17363502341 ps
T278 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1802495636 May 02 01:51:47 PM PDT 24 May 02 01:55:03 PM PDT 24 1876382746 ps
T279 /workspace/coverage/default/32.sram_ctrl_max_throughput.2446477145 May 02 01:53:53 PM PDT 24 May 02 01:54:00 PM PDT 24 698277288 ps
T280 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1002356964 May 02 01:56:19 PM PDT 24 May 02 02:04:13 PM PDT 24 37581913610 ps
T116 /workspace/coverage/default/30.sram_ctrl_lc_escalation.768369321 May 02 01:53:34 PM PDT 24 May 02 01:54:54 PM PDT 24 22899089378 ps
T281 /workspace/coverage/default/43.sram_ctrl_smoke.625974789 May 02 01:55:40 PM PDT 24 May 02 01:56:00 PM PDT 24 5242223483 ps
T282 /workspace/coverage/default/4.sram_ctrl_multiple_keys.3104731698 May 02 01:51:28 PM PDT 24 May 02 01:52:34 PM PDT 24 3401114007 ps
T283 /workspace/coverage/default/5.sram_ctrl_mem_walk.2282291336 May 02 01:51:35 PM PDT 24 May 02 01:55:38 PM PDT 24 32839776612 ps
T284 /workspace/coverage/default/29.sram_ctrl_executable.3566611610 May 02 01:53:30 PM PDT 24 May 02 01:55:20 PM PDT 24 5094291605 ps
T285 /workspace/coverage/default/27.sram_ctrl_alert_test.1602762146 May 02 01:53:18 PM PDT 24 May 02 01:53:21 PM PDT 24 31732943 ps
T286 /workspace/coverage/default/40.sram_ctrl_regwen.2590205419 May 02 01:55:15 PM PDT 24 May 02 02:03:02 PM PDT 24 3650500344 ps
T287 /workspace/coverage/default/11.sram_ctrl_lc_escalation.3534904526 May 02 01:51:55 PM PDT 24 May 02 01:53:03 PM PDT 24 45195384163 ps
T288 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.787706697 May 02 01:53:16 PM PDT 24 May 02 01:54:37 PM PDT 24 2444616761 ps
T289 /workspace/coverage/default/43.sram_ctrl_lc_escalation.1769280246 May 02 01:55:47 PM PDT 24 May 02 01:56:36 PM PDT 24 8206391076 ps
T290 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2850660106 May 02 01:51:36 PM PDT 24 May 02 01:52:31 PM PDT 24 1930942841 ps
T291 /workspace/coverage/default/7.sram_ctrl_stress_all.260851815 May 02 01:51:44 PM PDT 24 May 02 02:04:55 PM PDT 24 23566899155 ps
T292 /workspace/coverage/default/33.sram_ctrl_executable.2305804288 May 02 01:54:12 PM PDT 24 May 02 02:10:50 PM PDT 24 21245983300 ps
T293 /workspace/coverage/default/40.sram_ctrl_max_throughput.370986832 May 02 01:55:12 PM PDT 24 May 02 01:56:26 PM PDT 24 768288610 ps
T294 /workspace/coverage/default/15.sram_ctrl_lc_escalation.2239190864 May 02 01:52:12 PM PDT 24 May 02 01:53:00 PM PDT 24 13999379812 ps
T295 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2308334474 May 02 01:52:08 PM PDT 24 May 02 01:53:29 PM PDT 24 10110372682 ps
T296 /workspace/coverage/default/19.sram_ctrl_max_throughput.859799889 May 02 01:52:16 PM PDT 24 May 02 01:53:47 PM PDT 24 783814550 ps
T297 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2569016090 May 02 01:57:09 PM PDT 24 May 02 01:57:51 PM PDT 24 2733245238 ps
T298 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2481083090 May 02 01:56:10 PM PDT 24 May 02 01:57:01 PM PDT 24 1390967608 ps
T299 /workspace/coverage/default/24.sram_ctrl_lc_escalation.2758976867 May 02 01:52:51 PM PDT 24 May 02 01:54:02 PM PDT 24 37263829248 ps
T300 /workspace/coverage/default/39.sram_ctrl_regwen.83655301 May 02 01:55:10 PM PDT 24 May 02 02:11:15 PM PDT 24 70103234553 ps
T301 /workspace/coverage/default/24.sram_ctrl_multiple_keys.2071026040 May 02 01:52:44 PM PDT 24 May 02 02:02:07 PM PDT 24 4662065092 ps
T302 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.245824916 May 02 01:51:35 PM PDT 24 May 02 01:53:33 PM PDT 24 3315031222 ps
T303 /workspace/coverage/default/29.sram_ctrl_multiple_keys.1642665581 May 02 01:53:27 PM PDT 24 May 02 02:18:01 PM PDT 24 128097832750 ps
T304 /workspace/coverage/default/9.sram_ctrl_bijection.2422474500 May 02 01:51:50 PM PDT 24 May 02 02:10:43 PM PDT 24 71245721180 ps
T305 /workspace/coverage/default/16.sram_ctrl_bijection.4100326320 May 02 01:52:07 PM PDT 24 May 02 02:17:10 PM PDT 24 360458776181 ps
T306 /workspace/coverage/default/26.sram_ctrl_alert_test.2848816067 May 02 01:53:10 PM PDT 24 May 02 01:53:13 PM PDT 24 14502812 ps
T307 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.22809380 May 02 01:53:12 PM PDT 24 May 02 01:59:09 PM PDT 24 15386275156 ps
T117 /workspace/coverage/default/22.sram_ctrl_stress_all.1579888805 May 02 01:52:37 PM PDT 24 May 02 02:08:47 PM PDT 24 30248451412 ps
T308 /workspace/coverage/default/9.sram_ctrl_regwen.2614787514 May 02 01:51:45 PM PDT 24 May 02 02:13:41 PM PDT 24 14213327580 ps
T309 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.44410395 May 02 01:53:41 PM PDT 24 May 02 01:54:03 PM PDT 24 927094574 ps
T310 /workspace/coverage/default/7.sram_ctrl_max_throughput.40510427 May 02 01:51:38 PM PDT 24 May 02 01:51:51 PM PDT 24 694756006 ps
T311 /workspace/coverage/default/6.sram_ctrl_smoke.1954529147 May 02 01:51:41 PM PDT 24 May 02 01:52:01 PM PDT 24 2371269963 ps
T312 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.652740375 May 02 01:53:08 PM PDT 24 May 02 01:59:49 PM PDT 24 37394801815 ps
T313 /workspace/coverage/default/15.sram_ctrl_max_throughput.1942156269 May 02 01:52:05 PM PDT 24 May 02 01:52:22 PM PDT 24 7706533286 ps
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