Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	136928786	1			T1	1662		T2	1348		T3	1136
triple_byte_access	2890591	1			T1	3708		T2	34		T3	1050
halfword_access	4421013	1			T1	6905		T2	41		T3	1505
byte_access	6160795	1			T1	12769		T2	58		T3	2025
zero_access	1840337	1			T1	7511		T2	16		T3	529

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76048937

1

T1

16057

T2

741

T3

3172

auto[1]

76192585

1

T1

16498

T2

756

T3

3073

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	68246788	1			T1	129		T2	667		T3	582
auto[0]	triple_byte_access	1387249	1			T1	729		T2	19		T3	551
auto[0]	halfword_access	2167938	1			T1	2348		T2	20		T3	754
auto[0]	byte_access	3156986	1			T1	6796		T2	27		T3	1022
auto[0]	zero_access	1089976	1			T1	6055		T2	8		T3	263
auto[1]	word_access	68681998	1			T1	1533		T2	681		T3	554
auto[1]	triple_byte_access	1503342	1			T1	2979		T2	15		T3	499
auto[1]	halfword_access	2253075	1			T1	4557		T2	21		T3	751
auto[1]	byte_access	3003809	1			T1	5973		T2	31		T3	1003
auto[1]	zero_access	750361	1			T1	1456		T2	8		T3	266