Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	334888608	1			T1	3098		T2	393982		T3	18668
instr_valid_dis	293669213	1			T1	3098		T2	180282		T3	18668
instr_en	31275609	1			T2	206722		T8	9915		T10	16042

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	14096280	1			T2	98858		T26	3484		T127	32330
sram_ifetch_valid_disable	295161401	1			T1	3098		T2	190178		T3	18668
sram_ifetch_enable	25630927	1			T2	104946		T10	45410		T26	77974

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	334888608	1			T1	3098		T2	393982		T3	18668
hw_debug_en_valid_off	290696707	1			T1	3098		T2	104730		T3	18668
hw_debug_en_on	28538265	1			T2	139068		T8	9914		T10	21000

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	295161401	1			T1	3098		T2	190178		T3	18668
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	279493040	1			T1	3098		T2	83156		T3	18668
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	12197357	1			T2	107022		T8	9915		T10	16042
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5046824	1			T2	10322		T127	20000		T126	12596
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2333162	1			T2	10322		T46	55238		T20	15132
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1846590	1			T127	20000		T126	12596		T46	15752
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4443494	1			T2	88536		T129	6730		T46	5362
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1658250	1			T129	6730		T46	5362		T20	164238
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1794014	1			T2	88536		T125	21796		T47	7752
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	13785870	1			T2	18790		T8	9914		T10	21000
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6153450	1			T2	18790		T10	21000		T126	16110
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	6406206	1			T8	9914		T26	5936		T127	19608

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12051974	1			T2	11164		T127	2158		T129	17866
lc_exec_en	10308901	1			T2	31742		T26	77974		T127	29496
valid_exec_dis	285246602	1			T1	3098		T2	167372		T3	18668
invalid_exec_dis	39727207	1			T2	203804		T10	45410		T26	81458