Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	96.99	100.00	100.00	98.60	99.70	98.52

Total tests in report: 1035

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
85.56	85.56	97.75	97.75	77.27	77.27	87.07	87.07	100.00	100.00	93.24	93.24	94.95	94.95	48.61	48.61	/workspace/coverage/default/12.sram_ctrl_lc_escalation.2658355167
93.18	7.62	98.78	1.03	87.01	9.74	96.98	9.91	100.00	0.00	94.65	1.41	96.73	1.78	78.11	29.50	/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2857164218
94.92	1.74	99.06	0.28	89.87	2.86	98.12	1.14	100.00	0.00	96.62	1.97	96.73	0.00	84.04	5.94	/workspace/coverage/default/49.sram_ctrl_regwen.637039659
95.94	1.02	99.25	0.19	90.78	0.91	98.33	0.21	100.00	0.00	97.46	0.85	96.73	0.00	89.05	5.01	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.332280587
96.59	0.64	99.44	0.19	92.73	1.95	98.69	0.36	100.00	0.00	98.31	0.85	97.33	0.59	89.61	0.56	/workspace/coverage/default/2.sram_ctrl_sec_cm.1042144967
97.06	0.47	99.44	0.00	92.73	0.00	98.69	0.00	100.00	0.00	98.31	0.00	97.47	0.15	92.76	3.15	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.668026468
97.48	0.42	99.72	0.28	92.99	0.26	98.79	0.11	100.00	0.00	98.59	0.28	97.47	0.00	94.81	2.04	/workspace/coverage/default/16.sram_ctrl_executable.636386134
97.71	0.23	99.72	0.00	93.38	0.39	98.79	0.00	100.00	0.00	98.87	0.28	97.47	0.00	95.73	0.93	/workspace/coverage/default/40.sram_ctrl_executable.2035263170
97.91	0.20	99.72	0.00	93.38	0.00	98.86	0.07	100.00	0.00	98.87	0.00	98.81	1.34	95.73	0.00	/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3709284418
98.11	0.20	99.72	0.00	93.77	0.39	99.29	0.43	100.00	0.00	98.87	0.00	98.81	0.00	96.29	0.56	/workspace/coverage/default/11.sram_ctrl_alert_test.4294285918
98.27	0.16	99.72	0.00	94.03	0.26	99.29	0.00	100.00	0.00	98.87	0.00	99.70	0.89	96.29	0.00	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.2255335617
98.39	0.11	99.81	0.09	94.03	0.00	100.00	0.71	100.00	0.00	98.87	0.00	99.70	0.00	96.29	0.00	/workspace/coverage/default/0.sram_ctrl_ram_cfg.751959828
98.49	0.11	99.81	0.00	94.03	0.00	100.00	0.00	100.00	0.00	98.87	0.00	99.70	0.00	97.03	0.74	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3022969072
98.57	0.08	99.81	0.00	94.03	0.00	100.00	0.00	100.00	0.00	98.87	0.00	99.70	0.00	97.59	0.56	/workspace/coverage/default/43.sram_ctrl_executable.2678898210
98.62	0.05	99.81	0.00	94.03	0.00	100.00	0.00	100.00	0.00	98.87	0.00	99.70	0.00	97.96	0.37	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3566439169
98.67	0.05	99.81	0.00	94.16	0.13	100.00	0.00	100.00	0.00	98.87	0.00	99.70	0.00	98.14	0.19	/workspace/coverage/default/26.sram_ctrl_stress_all.1646384338
98.70	0.03	99.81	0.00	94.16	0.00	100.00	0.00	100.00	0.00	98.87	0.00	99.70	0.00	98.33	0.19	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2025382508
98.72	0.03	99.81	0.00	94.16	0.00	100.00	0.00	100.00	0.00	98.87	0.00	99.70	0.00	98.52	0.19	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1623301423

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.580119001
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1291901662
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2938614370
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2252200049
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3673047145
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.317713941
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3619577881
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3898668934
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1306032649
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2022374508
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1241966652
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4246970302
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3686561483
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4149547504
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1747353911
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1739026095
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2169239598
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1482957870
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.792768797
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3776543887
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2019864883
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1777859588
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.214225398
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2337614940
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1409893646
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2303596400
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1444313070
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.93758846
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.537657937
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4187495066
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2527721238
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3358664179
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3121359458
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1774484609
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.881745575
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.212329949
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1953876175
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1728813317
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1658050607
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2927361914
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2171768954
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3824736057
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.712771331
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2118092731
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2953098163
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2198953368
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3994321136
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3980733197
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3851993844
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3531302963
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.265923301
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2814000734
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3926660643
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2731591213
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4254998230
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1886777697
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2376501142
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2843695226
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1266663179
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3582432464
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.217282710
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.299408030
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.752667112
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1908880175
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.727624502
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4091519393
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3289601612
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4285525157
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.860147435
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.399259882
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1092951775
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2478685084
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1052961890
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1771344509
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1324875510
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2563562184
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2190682720
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2416385379
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2881127377
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3960973567
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2169502570
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2829534700
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.643304145
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.859841397
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2845284441
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3641304312
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2576653206
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2194077866
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3652929181
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3681269781
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1740335739
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2747080682
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1115614406
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2090901420
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.785076929
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1778145276
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1828611248
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2415791868
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2790998593
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4134256336
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3431520177
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.643598303
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3179973422
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1958025138
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3895625780
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2765528087
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2261338084
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3686191855
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3632329226
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2580556070
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1948816766
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1311358047
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.660123596
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1561560637
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.526183958
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2405044681
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2391328217
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1564392039
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3996334136
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.179162999
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.607329829
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1594645970
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3958779996
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2152100292
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3803908623
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2009667540
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.139223090
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2151726916
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4140918622
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2162337163
/workspace/coverage/default/0.sram_ctrl_alert_test.3417165830
/workspace/coverage/default/0.sram_ctrl_bijection.1230214635
/workspace/coverage/default/0.sram_ctrl_executable.1112664702
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2393502028
/workspace/coverage/default/0.sram_ctrl_max_throughput.616533799
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.4095584681
/workspace/coverage/default/0.sram_ctrl_mem_walk.3257008630
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2670405781
/workspace/coverage/default/0.sram_ctrl_partial_access.2615904343
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2296429797
/workspace/coverage/default/0.sram_ctrl_regwen.3232365675
/workspace/coverage/default/0.sram_ctrl_sec_cm.3477311182
/workspace/coverage/default/0.sram_ctrl_smoke.1061426957
/workspace/coverage/default/0.sram_ctrl_stress_all.1391198925
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1983282603
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.787086602
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.114186408
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1120818019
/workspace/coverage/default/1.sram_ctrl_alert_test.3350803002
/workspace/coverage/default/1.sram_ctrl_bijection.2590385426
/workspace/coverage/default/1.sram_ctrl_executable.942901583
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1046136729
/workspace/coverage/default/1.sram_ctrl_max_throughput.2684848475
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2001905508
/workspace/coverage/default/1.sram_ctrl_mem_walk.1366462770
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1122768366
/workspace/coverage/default/1.sram_ctrl_partial_access.3194416915
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4214339163
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1786922213
/workspace/coverage/default/1.sram_ctrl_regwen.260197398
/workspace/coverage/default/1.sram_ctrl_sec_cm.4155986561
/workspace/coverage/default/1.sram_ctrl_smoke.3420299546
/workspace/coverage/default/1.sram_ctrl_stress_all.572449000
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3235458478
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3287577626
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.695505224
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.846210634
/workspace/coverage/default/10.sram_ctrl_alert_test.3318418410
/workspace/coverage/default/10.sram_ctrl_bijection.1229987497
/workspace/coverage/default/10.sram_ctrl_executable.1902045305
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2580102876
/workspace/coverage/default/10.sram_ctrl_max_throughput.276904078
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3336892799
/workspace/coverage/default/10.sram_ctrl_mem_walk.1052811679
/workspace/coverage/default/10.sram_ctrl_multiple_keys.175525811
/workspace/coverage/default/10.sram_ctrl_partial_access.2207729176
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3784401596
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1648080220
/workspace/coverage/default/10.sram_ctrl_regwen.1645402116
/workspace/coverage/default/10.sram_ctrl_smoke.4200833301
/workspace/coverage/default/10.sram_ctrl_stress_all.2723596666
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3183917373
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1696128950
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.707257418
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.4228754637
/workspace/coverage/default/11.sram_ctrl_executable.200963685
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1343944221
/workspace/coverage/default/11.sram_ctrl_max_throughput.4177112446
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3001719021
/workspace/coverage/default/11.sram_ctrl_mem_walk.1538853501
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1123188253
/workspace/coverage/default/11.sram_ctrl_partial_access.3584305990
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3209053765
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3866590683
/workspace/coverage/default/11.sram_ctrl_regwen.2744849303
/workspace/coverage/default/11.sram_ctrl_smoke.3569717877
/workspace/coverage/default/11.sram_ctrl_stress_all.3740150090
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/workspace/coverage/default/42.sram_ctrl_multiple_keys.1053819369
/workspace/coverage/default/42.sram_ctrl_partial_access.3211170989
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.4131706856
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3250120899
/workspace/coverage/default/42.sram_ctrl_regwen.2865896588
/workspace/coverage/default/42.sram_ctrl_smoke.2437331747
/workspace/coverage/default/42.sram_ctrl_stress_all.4041103222
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.807466832
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.686895459
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3846305374
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1133488992
/workspace/coverage/default/43.sram_ctrl_alert_test.4084492706
/workspace/coverage/default/43.sram_ctrl_bijection.3774276603
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3854962006
/workspace/coverage/default/43.sram_ctrl_max_throughput.2129231533
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.555687826
/workspace/coverage/default/43.sram_ctrl_mem_walk.328218151
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2526385597
/workspace/coverage/default/43.sram_ctrl_partial_access.2151408435
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3861418880
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1975328068
/workspace/coverage/default/43.sram_ctrl_regwen.496114076
/workspace/coverage/default/43.sram_ctrl_smoke.310443141
/workspace/coverage/default/43.sram_ctrl_stress_all.3963191498
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3697572156
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.4063796846
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.553375098
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2091691979
/workspace/coverage/default/44.sram_ctrl_alert_test.2008239460
/workspace/coverage/default/44.sram_ctrl_bijection.2927638160
/workspace/coverage/default/44.sram_ctrl_executable.62280621
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1413113675
/workspace/coverage/default/44.sram_ctrl_max_throughput.725964970
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3399729070
/workspace/coverage/default/44.sram_ctrl_mem_walk.258975020
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2482009614
/workspace/coverage/default/44.sram_ctrl_partial_access.3224164044
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.866397518
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1701969354
/workspace/coverage/default/44.sram_ctrl_regwen.910892219
/workspace/coverage/default/44.sram_ctrl_smoke.686163768
/workspace/coverage/default/44.sram_ctrl_stress_all.3149971907
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3657919488
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2754302161
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2483374629
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3450459914
/workspace/coverage/default/45.sram_ctrl_alert_test.2225504305
/workspace/coverage/default/45.sram_ctrl_bijection.317377325
/workspace/coverage/default/45.sram_ctrl_executable.849911530
/workspace/coverage/default/45.sram_ctrl_lc_escalation.196074869
/workspace/coverage/default/45.sram_ctrl_max_throughput.2942784965
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3238645435
/workspace/coverage/default/45.sram_ctrl_mem_walk.393494488
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2718768596
/workspace/coverage/default/45.sram_ctrl_partial_access.2376938625
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2741378590
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2296490102
/workspace/coverage/default/45.sram_ctrl_regwen.4230233030
/workspace/coverage/default/45.sram_ctrl_smoke.800271493
/workspace/coverage/default/45.sram_ctrl_stress_all.792055374
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2962465931
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.525104610
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2221986293
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.135274099
/workspace/coverage/default/46.sram_ctrl_alert_test.1616703769
/workspace/coverage/default/46.sram_ctrl_bijection.3369578433
/workspace/coverage/default/46.sram_ctrl_executable.4094083598
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1970991561
/workspace/coverage/default/46.sram_ctrl_max_throughput.1852086873
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1996971341
/workspace/coverage/default/46.sram_ctrl_mem_walk.700968374
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2802367605
/workspace/coverage/default/46.sram_ctrl_partial_access.917179409
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2398166854
/workspace/coverage/default/46.sram_ctrl_ram_cfg.4071451117
/workspace/coverage/default/46.sram_ctrl_regwen.3197377610
/workspace/coverage/default/46.sram_ctrl_smoke.3646129073
/workspace/coverage/default/46.sram_ctrl_stress_all.1276405764
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3232651590
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3852674237
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2462802116
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2056989104
/workspace/coverage/default/47.sram_ctrl_alert_test.3320657821
/workspace/coverage/default/47.sram_ctrl_bijection.3330883243
/workspace/coverage/default/47.sram_ctrl_executable.413239844
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3958316361
/workspace/coverage/default/47.sram_ctrl_max_throughput.588409057
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1455324059
/workspace/coverage/default/47.sram_ctrl_mem_walk.2500998170
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1964588847
/workspace/coverage/default/47.sram_ctrl_partial_access.1103722738
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2995762782
/workspace/coverage/default/47.sram_ctrl_ram_cfg.26477489
/workspace/coverage/default/47.sram_ctrl_regwen.2204249646
/workspace/coverage/default/47.sram_ctrl_smoke.4245997712
/workspace/coverage/default/47.sram_ctrl_stress_all.1408075022
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1239507332
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.154641765
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1162392078
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.977252989
/workspace/coverage/default/48.sram_ctrl_alert_test.477590564
/workspace/coverage/default/48.sram_ctrl_bijection.3297399824
/workspace/coverage/default/48.sram_ctrl_executable.95150213
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1567641328
/workspace/coverage/default/48.sram_ctrl_max_throughput.4064144670
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3312596272
/workspace/coverage/default/48.sram_ctrl_mem_walk.843902338
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2265989634
/workspace/coverage/default/48.sram_ctrl_partial_access.953703063
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1243577229
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1300891514
/workspace/coverage/default/48.sram_ctrl_regwen.1701860703
/workspace/coverage/default/48.sram_ctrl_smoke.197695431
/workspace/coverage/default/48.sram_ctrl_stress_all.154198745
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3031867138
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3512396691
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1768816735
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.999194412
/workspace/coverage/default/49.sram_ctrl_alert_test.1437895945
/workspace/coverage/default/49.sram_ctrl_bijection.1667846853
/workspace/coverage/default/49.sram_ctrl_executable.3560488264
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3272001591
/workspace/coverage/default/49.sram_ctrl_max_throughput.2666823153
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2980265341
/workspace/coverage/default/49.sram_ctrl_mem_walk.4225988778
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2510075117
/workspace/coverage/default/49.sram_ctrl_partial_access.2592956323
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3150912194
/workspace/coverage/default/49.sram_ctrl_ram_cfg.928117148
/workspace/coverage/default/49.sram_ctrl_smoke.2066503651
/workspace/coverage/default/49.sram_ctrl_stress_all.4184474773
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3838730841
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2647875270
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3591795087
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.4070371459
/workspace/coverage/default/5.sram_ctrl_alert_test.925051025
/workspace/coverage/default/5.sram_ctrl_bijection.1813317549
/workspace/coverage/default/5.sram_ctrl_executable.3665744495
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2615623365
/workspace/coverage/default/5.sram_ctrl_max_throughput.3646424306
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2736894649
/workspace/coverage/default/5.sram_ctrl_mem_walk.487476933
/workspace/coverage/default/5.sram_ctrl_multiple_keys.3468866128
/workspace/coverage/default/5.sram_ctrl_partial_access.985128631
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.704763297
/workspace/coverage/default/5.sram_ctrl_ram_cfg.36576178
/workspace/coverage/default/5.sram_ctrl_regwen.4121249447
/workspace/coverage/default/5.sram_ctrl_smoke.4112108267
/workspace/coverage/default/5.sram_ctrl_stress_all.2638218607
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.767550561
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.990094176
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1445350957
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3222673854
/workspace/coverage/default/6.sram_ctrl_alert_test.2150828453
/workspace/coverage/default/6.sram_ctrl_bijection.1702494341
/workspace/coverage/default/6.sram_ctrl_executable.1611127027
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1754933666
/workspace/coverage/default/6.sram_ctrl_max_throughput.1132810834
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.4076304565
/workspace/coverage/default/6.sram_ctrl_mem_walk.58407629
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1265269911
/workspace/coverage/default/6.sram_ctrl_partial_access.2486618572
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.130149346
/workspace/coverage/default/6.sram_ctrl_ram_cfg.564828687
/workspace/coverage/default/6.sram_ctrl_regwen.983451370
/workspace/coverage/default/6.sram_ctrl_smoke.3188005852
/workspace/coverage/default/6.sram_ctrl_stress_all.3697927974
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3083067485
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1179148356
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3259775051
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2204561230
/workspace/coverage/default/7.sram_ctrl_alert_test.1038904777
/workspace/coverage/default/7.sram_ctrl_bijection.3941017720
/workspace/coverage/default/7.sram_ctrl_executable.1504734897
/workspace/coverage/default/7.sram_ctrl_lc_escalation.677174333
/workspace/coverage/default/7.sram_ctrl_max_throughput.214561860
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3834174360
/workspace/coverage/default/7.sram_ctrl_mem_walk.1236840863
/workspace/coverage/default/7.sram_ctrl_multiple_keys.277563654
/workspace/coverage/default/7.sram_ctrl_partial_access.1886978121
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1306538685
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2635085341
/workspace/coverage/default/7.sram_ctrl_regwen.1756721011
/workspace/coverage/default/7.sram_ctrl_smoke.869546331
/workspace/coverage/default/7.sram_ctrl_stress_all.812771135
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2610693981
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3401014767
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.962132923
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3054415252
/workspace/coverage/default/8.sram_ctrl_alert_test.1448578386
/workspace/coverage/default/8.sram_ctrl_bijection.2751071470
/workspace/coverage/default/8.sram_ctrl_executable.3813824041
/workspace/coverage/default/8.sram_ctrl_lc_escalation.4073370394
/workspace/coverage/default/8.sram_ctrl_max_throughput.1556111000
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.292431324
/workspace/coverage/default/8.sram_ctrl_mem_walk.2288093943
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2066297652
/workspace/coverage/default/8.sram_ctrl_partial_access.595796659
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2895284132
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3160415057
/workspace/coverage/default/8.sram_ctrl_regwen.724770879
/workspace/coverage/default/8.sram_ctrl_smoke.3360782673
/workspace/coverage/default/8.sram_ctrl_stress_all.410545818
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1900925106
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1040205823
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4065817192
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2428510502
/workspace/coverage/default/9.sram_ctrl_alert_test.3935955111
/workspace/coverage/default/9.sram_ctrl_bijection.1234859013
/workspace/coverage/default/9.sram_ctrl_executable.2696585390
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2260933335
/workspace/coverage/default/9.sram_ctrl_max_throughput.2189874450
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.4208591280
/workspace/coverage/default/9.sram_ctrl_mem_walk.2858804910
/workspace/coverage/default/9.sram_ctrl_multiple_keys.76995878
/workspace/coverage/default/9.sram_ctrl_partial_access.2247265267
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2919779809
/workspace/coverage/default/9.sram_ctrl_ram_cfg.281849322
/workspace/coverage/default/9.sram_ctrl_regwen.3175021129
/workspace/coverage/default/9.sram_ctrl_smoke.4179406597
/workspace/coverage/default/9.sram_ctrl_stress_all.1872290587
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1609215253
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1789710815
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3754976145

Total test records in report: 1035

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/43.sram_ctrl_smoke.310443141	May 05 12:55:08 PM PDT 24	May 05 12:55:19 PM PDT 24	2867441053 ps
T2	/workspace/coverage/default/16.sram_ctrl_executable.636386134	May 05 12:49:10 PM PDT 24	May 05 01:04:42 PM PDT 24	8408631888 ps
T3	/workspace/coverage/default/17.sram_ctrl_smoke.768563471	May 05 12:49:17 PM PDT 24	May 05 12:50:48 PM PDT 24	5456314992 ps
T4	/workspace/coverage/default/10.sram_ctrl_lc_escalation.2580102876	May 05 12:48:31 PM PDT 24	May 05 12:49:17 PM PDT 24	11997256339 ps
T7	/workspace/coverage/default/20.sram_ctrl_partial_access.3388306225	May 05 12:49:48 PM PDT 24	May 05 12:50:03 PM PDT 24	544942644 ps
T5	/workspace/coverage/default/12.sram_ctrl_lc_escalation.2658355167	May 05 12:48:40 PM PDT 24	May 05 12:49:54 PM PDT 24	13114707377 ps
T8	/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2610693981	May 05 12:48:13 PM PDT 24	May 05 12:49:16 PM PDT 24	2441565337 ps
T9	/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3031867138	May 05 12:56:32 PM PDT 24	May 05 12:56:50 PM PDT 24	531002927 ps
T10	/workspace/coverage/default/6.sram_ctrl_executable.1611127027	May 05 12:48:19 PM PDT 24	May 05 12:52:25 PM PDT 24	18926837925 ps
T11	/workspace/coverage/default/25.sram_ctrl_mem_walk.888126838	May 05 12:50:57 PM PDT 24	May 05 12:55:33 PM PDT 24	57287864712 ps
T12	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3150912194	May 05 12:56:40 PM PDT 24	May 05 01:01:57 PM PDT 24	50679334908 ps
T13	/workspace/coverage/default/15.sram_ctrl_partial_access.2059186674	May 05 12:48:58 PM PDT 24	May 05 12:49:22 PM PDT 24	1242913671 ps
T42	/workspace/coverage/default/5.sram_ctrl_bijection.1813317549	May 05 12:48:06 PM PDT 24	May 05 01:11:48 PM PDT 24	22099061940 ps
T27	/workspace/coverage/default/44.sram_ctrl_ram_cfg.1701969354	May 05 12:55:32 PM PDT 24	May 05 12:55:36 PM PDT 24	1346861080 ps
T17	/workspace/coverage/default/31.sram_ctrl_alert_test.3917951277	May 05 12:52:27 PM PDT 24	May 05 12:52:28 PM PDT 24	19138173 ps
T43	/workspace/coverage/default/27.sram_ctrl_stress_pipeline.4081532609	May 05 12:51:15 PM PDT 24	May 05 12:55:15 PM PDT 24	2735479148 ps
T94	/workspace/coverage/default/27.sram_ctrl_partial_access.407957623	May 05 12:51:19 PM PDT 24	May 05 12:53:05 PM PDT 24	1310906151 ps
T95	/workspace/coverage/default/35.sram_ctrl_stress_pipeline.3565641728	May 05 12:53:20 PM PDT 24	May 05 12:56:58 PM PDT 24	11420903003 ps
T69	/workspace/coverage/default/23.sram_ctrl_stress_pipeline.1087395895	May 05 12:50:23 PM PDT 24	May 05 12:54:42 PM PDT 24	5181060770 ps
T70	/workspace/coverage/default/34.sram_ctrl_partial_access.216290543	May 05 12:52:58 PM PDT 24	May 05 12:54:51 PM PDT 24	2184562260 ps
T26	/workspace/coverage/default/2.sram_ctrl_executable.2296436201	May 05 12:47:58 PM PDT 24	May 05 12:52:54 PM PDT 24	4126651190 ps
T136	/workspace/coverage/default/33.sram_ctrl_max_throughput.1069967246	May 05 12:52:53 PM PDT 24	May 05 12:53:12 PM PDT 24	1443048361 ps
T137	/workspace/coverage/default/21.sram_ctrl_mem_walk.146165004	May 05 12:50:07 PM PDT 24	May 05 12:52:08 PM PDT 24	4116597800 ps
T71	/workspace/coverage/default/46.sram_ctrl_smoke.3646129073	May 05 12:55:50 PM PDT 24	May 05 12:56:42 PM PDT 24	5796277585 ps
T72	/workspace/coverage/default/37.sram_ctrl_mem_partial_access.507350656	May 05 12:53:56 PM PDT 24	May 05 12:55:11 PM PDT 24	2673607357 ps
T73	/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2341735696	May 05 12:49:11 PM PDT 24	May 05 12:55:57 PM PDT 24	15961249549 ps
T74	/workspace/coverage/default/18.sram_ctrl_mem_walk.4087619180	May 05 12:49:32 PM PDT 24	May 05 12:51:32 PM PDT 24	4290670760 ps
T18	/workspace/coverage/default/36.sram_ctrl_alert_test.1900903952	May 05 12:53:40 PM PDT 24	May 05 12:53:41 PM PDT 24	15452944 ps
T28	/workspace/coverage/default/11.sram_ctrl_ram_cfg.3866590683	May 05 12:48:40 PM PDT 24	May 05 12:48:44 PM PDT 24	369903466 ps
T75	/workspace/coverage/default/5.sram_ctrl_mem_walk.487476933	May 05 12:48:04 PM PDT 24	May 05 12:52:38 PM PDT 24	28697838885 ps
T25	/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2857164218	May 05 12:50:00 PM PDT 24	May 05 12:50:25 PM PDT 24	1004654746 ps
T76	/workspace/coverage/default/41.sram_ctrl_max_throughput.2882256765	May 05 12:54:44 PM PDT 24	May 05 12:56:06 PM PDT 24	3002582243 ps
T29	/workspace/coverage/default/38.sram_ctrl_ram_cfg.754496777	May 05 12:54:06 PM PDT 24	May 05 12:54:10 PM PDT 24	348133346 ps
T19	/workspace/coverage/default/25.sram_ctrl_alert_test.1221850276	May 05 12:51:00 PM PDT 24	May 05 12:51:02 PM PDT 24	53668079 ps
T138	/workspace/coverage/default/0.sram_ctrl_ram_cfg.751959828	May 05 12:47:53 PM PDT 24	May 05 12:47:57 PM PDT 24	347947249 ps
T41	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1963701295	May 05 12:54:46 PM PDT 24	May 05 01:02:56 PM PDT 24	3403823124 ps
T127	/workspace/coverage/default/43.sram_ctrl_executable.2678898210	May 05 12:55:17 PM PDT 24	May 05 01:09:00 PM PDT 24	25106639958 ps
T6	/workspace/coverage/default/42.sram_ctrl_lc_escalation.17376386	May 05 12:54:56 PM PDT 24	May 05 12:55:55 PM PDT 24	48988757457 ps
T139	/workspace/coverage/default/35.sram_ctrl_max_throughput.2778567525	May 05 12:53:20 PM PDT 24	May 05 12:53:26 PM PDT 24	691004285 ps
T44	/workspace/coverage/default/34.sram_ctrl_access_during_key_req.2358651000	May 05 12:53:04 PM PDT 24	May 05 12:58:51 PM PDT 24	4826135347 ps
T135	/workspace/coverage/default/34.sram_ctrl_smoke.695785736	May 05 12:53:00 PM PDT 24	May 05 12:54:16 PM PDT 24	446629090 ps
T140	/workspace/coverage/default/4.sram_ctrl_bijection.1813098487	May 05 12:48:06 PM PDT 24	May 05 01:16:15 PM PDT 24	29082600663 ps
T133	/workspace/coverage/default/23.sram_ctrl_bijection.3878206205	May 05 12:50:22 PM PDT 24	May 05 01:01:29 PM PDT 24	43364890381 ps
T141	/workspace/coverage/default/18.sram_ctrl_multiple_keys.3336262571	May 05 12:49:28 PM PDT 24	May 05 12:53:28 PM PDT 24	19984029987 ps
T142	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.325342969	May 05 12:53:36 PM PDT 24	May 05 12:54:55 PM PDT 24	12723373400 ps
T143	/workspace/coverage/default/6.sram_ctrl_ram_cfg.564828687	May 05 12:48:13 PM PDT 24	May 05 12:48:16 PM PDT 24	712545102 ps
T144	/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1171269116	May 05 12:49:48 PM PDT 24	May 05 12:50:33 PM PDT 24	765264066 ps
T45	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.2255335617	May 05 12:49:10 PM PDT 24	May 05 12:55:50 PM PDT 24	7078768385 ps
T134	/workspace/coverage/default/40.sram_ctrl_multiple_keys.2660280120	May 05 12:54:26 PM PDT 24	May 05 01:00:27 PM PDT 24	16053236659 ps
T145	/workspace/coverage/default/3.sram_ctrl_mem_walk.1053304318	May 05 12:48:08 PM PDT 24	May 05 12:52:59 PM PDT 24	18669169253 ps
T129	/workspace/coverage/default/4.sram_ctrl_executable.2219502898	May 05 12:48:03 PM PDT 24	May 05 12:50:02 PM PDT 24	2699759358 ps
T79	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.4199535407	May 05 12:48:48 PM PDT 24	May 05 12:50:50 PM PDT 24	6770544845 ps
T80	/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2980265341	May 05 12:56:48 PM PDT 24	May 05 12:58:00 PM PDT 24	2475151356 ps
T146	/workspace/coverage/default/41.sram_ctrl_mem_walk.1558897952	May 05 12:54:49 PM PDT 24	May 05 12:58:56 PM PDT 24	65677136065 ps
T126	/workspace/coverage/default/14.sram_ctrl_executable.3666321508	May 05 12:48:58 PM PDT 24	May 05 01:00:39 PM PDT 24	5798319336 ps
T147	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3846305374	May 05 12:54:55 PM PDT 24	May 05 12:55:38 PM PDT 24	3194802049 ps
T99	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.668026468	May 05 12:52:30 PM PDT 24	May 05 12:59:26 PM PDT 24	21277736091 ps
T46	/workspace/coverage/default/41.sram_ctrl_executable.1391903406	May 05 12:54:45 PM PDT 24	May 05 01:09:53 PM PDT 24	29326096851 ps
T125	/workspace/coverage/default/33.sram_ctrl_executable.1005283893	May 05 12:52:59 PM PDT 24	May 05 01:21:14 PM PDT 24	15982358208 ps
T148	/workspace/coverage/default/10.sram_ctrl_mem_walk.1052811679	May 05 12:48:28 PM PDT 24	May 05 12:50:55 PM PDT 24	10663102625 ps
T149	/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3794160531	May 05 12:53:52 PM PDT 24	May 05 12:55:59 PM PDT 24	3133304296 ps
T150	/workspace/coverage/default/10.sram_ctrl_smoke.4200833301	May 05 12:48:26 PM PDT 24	May 05 12:48:38 PM PDT 24	791648265 ps
T81	/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1566608805	May 05 12:47:59 PM PDT 24	May 05 12:49:16 PM PDT 24	11075545378 ps
T151	/workspace/coverage/default/34.sram_ctrl_max_throughput.3890868382	May 05 12:52:58 PM PDT 24	May 05 12:54:46 PM PDT 24	3324982970 ps
T20	/workspace/coverage/default/49.sram_ctrl_regwen.637039659	May 05 12:56:50 PM PDT 24	May 05 01:18:59 PM PDT 24	39786962202 ps
T152	/workspace/coverage/default/38.sram_ctrl_smoke.713185792	May 05 12:53:57 PM PDT 24	May 05 12:55:28 PM PDT 24	1863896071 ps
T153	/workspace/coverage/default/13.sram_ctrl_max_throughput.1254580850	May 05 12:48:43 PM PDT 24	May 05 12:48:54 PM PDT 24	2746682669 ps
T49	/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.702666750	May 05 12:49:01 PM PDT 24	May 05 12:49:51 PM PDT 24	7279156627 ps
T82	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3312596272	May 05 12:56:31 PM PDT 24	May 05 12:58:23 PM PDT 24	3094274987 ps
T154	/workspace/coverage/default/29.sram_ctrl_alert_test.1152887256	May 05 12:51:54 PM PDT 24	May 05 12:51:55 PM PDT 24	44498609 ps
T47	/workspace/coverage/default/40.sram_ctrl_executable.2035263170	May 05 12:54:34 PM PDT 24	May 05 01:15:12 PM PDT 24	89998559482 ps
T132	/workspace/coverage/default/12.sram_ctrl_multiple_keys.4172310537	May 05 12:48:38 PM PDT 24	May 05 01:03:53 PM PDT 24	27611778199 ps
T21	/workspace/coverage/default/2.sram_ctrl_regwen.2714261056	May 05 12:48:02 PM PDT 24	May 05 01:03:07 PM PDT 24	3340537397 ps
T22	/workspace/coverage/default/27.sram_ctrl_lc_escalation.301678594	May 05 12:51:17 PM PDT 24	May 05 12:52:55 PM PDT 24	15898458862 ps
T83	/workspace/coverage/default/19.sram_ctrl_access_during_key_req.2493014058	May 05 12:49:46 PM PDT 24	May 05 12:57:16 PM PDT 24	25082246020 ps
T155	/workspace/coverage/default/16.sram_ctrl_ram_cfg.3532226924	May 05 12:49:11 PM PDT 24	May 05 12:49:14 PM PDT 24	350725015 ps
T84	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2680626463	May 05 12:49:22 PM PDT 24	May 05 12:50:35 PM PDT 24	2453477307 ps
T156	/workspace/coverage/default/25.sram_ctrl_smoke.1942305881	May 05 12:50:50 PM PDT 24	May 05 12:51:44 PM PDT 24	1151728632 ps
T55	/workspace/coverage/default/9.sram_ctrl_regwen.3175021129	May 05 12:48:27 PM PDT 24	May 05 01:03:41 PM PDT 24	34406813392 ps
T100	/workspace/coverage/default/28.sram_ctrl_stress_pipeline.602081159	May 05 12:51:27 PM PDT 24	May 05 12:53:28 PM PDT 24	3210992810 ps
T157	/workspace/coverage/default/16.sram_ctrl_smoke.3468616932	May 05 12:49:06 PM PDT 24	May 05 12:49:11 PM PDT 24	2466018564 ps
T158	/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1445350957	May 05 12:48:10 PM PDT 24	May 05 12:49:07 PM PDT 24	1584510383 ps
T159	/workspace/coverage/default/24.sram_ctrl_mem_partial_access.506974375	May 05 12:50:44 PM PDT 24	May 05 12:52:03 PM PDT 24	15595239122 ps
T48	/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1288507190	May 05 12:51:37 PM PDT 24	May 05 12:52:42 PM PDT 24	6058237420 ps
T160	/workspace/coverage/default/47.sram_ctrl_bijection.3330883243	May 05 12:56:08 PM PDT 24	May 05 01:12:48 PM PDT 24	15719103231 ps
T161	/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3669861482	May 05 12:50:27 PM PDT 24	May 05 12:51:04 PM PDT 24	775361479 ps
T162	/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3336892799	May 05 12:48:34 PM PDT 24	May 05 12:49:37 PM PDT 24	3813401017 ps
T163	/workspace/coverage/default/28.sram_ctrl_alert_test.1029268898	May 05 12:51:37 PM PDT 24	May 05 12:51:38 PM PDT 24	14130984 ps
T130	/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2065962235	May 05 12:51:16 PM PDT 24	May 05 12:57:28 PM PDT 24	18343296275 ps
T164	/workspace/coverage/default/28.sram_ctrl_ram_cfg.3376890407	May 05 12:51:39 PM PDT 24	May 05 12:51:43 PM PDT 24	1353563114 ps
T165	/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2635328983	May 05 12:49:06 PM PDT 24	May 05 01:05:51 PM PDT 24	69927949619 ps
T166	/workspace/coverage/default/30.sram_ctrl_bijection.1474568100	May 05 12:51:54 PM PDT 24	May 05 01:23:54 PM PDT 24	28149215712 ps
T167	/workspace/coverage/default/15.sram_ctrl_mem_walk.1871940913	May 05 12:49:07 PM PDT 24	May 05 12:51:47 PM PDT 24	43072136970 ps
T168	/workspace/coverage/default/11.sram_ctrl_alert_test.4294285918	May 05 12:48:41 PM PDT 24	May 05 12:48:42 PM PDT 24	35498614 ps
T128	/workspace/coverage/default/49.sram_ctrl_executable.3560488264	May 05 12:56:44 PM PDT 24	May 05 01:09:12 PM PDT 24	34922310570 ps
T169	/workspace/coverage/default/17.sram_ctrl_executable.635937840	May 05 12:49:18 PM PDT 24	May 05 01:04:58 PM PDT 24	110667998385 ps
T56	/workspace/coverage/default/4.sram_ctrl_stress_all.3482358979	May 05 12:48:07 PM PDT 24	May 05 01:59:19 PM PDT 24	50452460807 ps
T170	/workspace/coverage/default/25.sram_ctrl_partial_access.3654932360	May 05 12:50:50 PM PDT 24	May 05 12:51:06 PM PDT 24	1168954743 ps
T171	/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.4158551713	May 05 12:54:28 PM PDT 24	May 05 01:02:24 PM PDT 24	77538283134 ps
T131	/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3164589658	May 05 12:53:35 PM PDT 24	May 05 01:00:55 PM PDT 24	77562259988 ps
T172	/workspace/coverage/default/8.sram_ctrl_max_throughput.1556111000	May 05 12:48:19 PM PDT 24	May 05 12:48:33 PM PDT 24	751226318 ps
T173	/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3001476157	May 05 12:54:50 PM PDT 24	May 05 12:56:03 PM PDT 24	781814757 ps
T174	/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2483374629	May 05 12:55:29 PM PDT 24	May 05 12:56:40 PM PDT 24	810330232 ps
T175	/workspace/coverage/default/39.sram_ctrl_executable.3518011208	May 05 12:54:17 PM PDT 24	May 05 01:10:57 PM PDT 24	49953585427 ps
T57	/workspace/coverage/default/43.sram_ctrl_lc_escalation.3854962006	May 05 12:55:18 PM PDT 24	May 05 12:55:42 PM PDT 24	3140167134 ps
T176	/workspace/coverage/default/39.sram_ctrl_ram_cfg.15936370	May 05 12:54:22 PM PDT 24	May 05 12:54:26 PM PDT 24	1353525124 ps
T177	/workspace/coverage/default/44.sram_ctrl_alert_test.2008239460	May 05 12:55:39 PM PDT 24	May 05 12:55:40 PM PDT 24	12429798 ps
T178	/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.4000635331	May 05 12:52:58 PM PDT 24	May 05 12:53:38 PM PDT 24	744398250 ps
T179	/workspace/coverage/default/20.sram_ctrl_ram_cfg.799660543	May 05 12:49:56 PM PDT 24	May 05 12:50:00 PM PDT 24	1988620009 ps
T180	/workspace/coverage/default/10.sram_ctrl_ram_cfg.1648080220	May 05 12:48:30 PM PDT 24	May 05 12:48:35 PM PDT 24	1397446472 ps
T181	/workspace/coverage/default/23.sram_ctrl_alert_test.2443450739	May 05 12:50:32 PM PDT 24	May 05 12:50:34 PM PDT 24	15140176 ps
T50	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3183917373	May 05 12:48:28 PM PDT 24	May 05 12:49:36 PM PDT 24	6641745992 ps
T182	/workspace/coverage/default/21.sram_ctrl_ram_cfg.3666878535	May 05 12:50:05 PM PDT 24	May 05 12:50:09 PM PDT 24	1875650777 ps
T58	/workspace/coverage/default/41.sram_ctrl_lc_escalation.519548162	May 05 12:54:45 PM PDT 24	May 05 12:56:33 PM PDT 24	63517136082 ps
T183	/workspace/coverage/default/24.sram_ctrl_bijection.964630951	May 05 12:50:38 PM PDT 24	May 05 01:00:23 PM PDT 24	151081563823 ps
T184	/workspace/coverage/default/46.sram_ctrl_executable.4094083598	May 05 12:55:57 PM PDT 24	May 05 01:03:03 PM PDT 24	10267894480 ps
T185	/workspace/coverage/default/18.sram_ctrl_max_throughput.2694807916	May 05 12:49:27 PM PDT 24	May 05 12:49:47 PM PDT 24	741943669 ps
T186	/workspace/coverage/default/45.sram_ctrl_smoke.800271493	May 05 12:55:40 PM PDT 24	May 05 12:56:01 PM PDT 24	901078355 ps
T187	/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.112639986	May 05 12:51:00 PM PDT 24	May 05 12:55:39 PM PDT 24	22045426053 ps
T188	/workspace/coverage/default/32.sram_ctrl_max_throughput.4098065249	May 05 12:52:29 PM PDT 24	May 05 12:53:46 PM PDT 24	2289560709 ps
T189	/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2162337163	May 05 12:47:54 PM PDT 24	May 05 01:03:24 PM PDT 24	43511016420 ps
T190	/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3754976145	May 05 12:48:23 PM PDT 24	May 05 12:48:31 PM PDT 24	1692202826 ps
T191	/workspace/coverage/default/18.sram_ctrl_ram_cfg.1394823510	May 05 12:49:34 PM PDT 24	May 05 12:49:37 PM PDT 24	361358653 ps
T192	/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.598857848	May 05 12:50:39 PM PDT 24	May 05 12:50:46 PM PDT 24	677190700 ps
T193	/workspace/coverage/default/47.sram_ctrl_ram_cfg.26477489	May 05 12:56:13 PM PDT 24	May 05 12:56:16 PM PDT 24	1345390900 ps
T194	/workspace/coverage/default/30.sram_ctrl_ram_cfg.1850718753	May 05 12:52:04 PM PDT 24	May 05 12:52:07 PM PDT 24	404440504 ps
T195	/workspace/coverage/default/19.sram_ctrl_bijection.1362520078	May 05 12:49:44 PM PDT 24	May 05 01:11:05 PM PDT 24	152006994374 ps
T23	/workspace/coverage/default/26.sram_ctrl_stress_all.1646384338	May 05 12:51:10 PM PDT 24	May 05 02:19:27 PM PDT 24	211250559848 ps
T196	/workspace/coverage/default/42.sram_ctrl_max_throughput.3593954168	May 05 12:54:56 PM PDT 24	May 05 12:55:21 PM PDT 24	752470674 ps
T197	/workspace/coverage/default/39.sram_ctrl_mem_walk.478290494	May 05 12:54:23 PM PDT 24	May 05 12:56:21 PM PDT 24	4031533629 ps
T198	/workspace/coverage/default/4.sram_ctrl_max_throughput.2276337516	May 05 12:48:05 PM PDT 24	May 05 12:48:35 PM PDT 24	2851308081 ps
T199	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.838178650	May 05 12:50:13 PM PDT 24	May 05 12:54:27 PM PDT 24	4306305336 ps
T200	/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2091691979	May 05 12:55:33 PM PDT 24	May 05 12:57:59 PM PDT 24	3417948560 ps
T201	/workspace/coverage/default/8.sram_ctrl_alert_test.1448578386	May 05 12:48:20 PM PDT 24	May 05 12:48:21 PM PDT 24	35549510 ps
T202	/workspace/coverage/default/49.sram_ctrl_smoke.2066503651	May 05 12:56:38 PM PDT 24	May 05 12:56:44 PM PDT 24	821109225 ps
T203	/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.4026169558	May 05 12:52:52 PM PDT 24	May 05 12:58:19 PM PDT 24	52407857750 ps
T204	/workspace/coverage/default/12.sram_ctrl_ram_cfg.1730883098	May 05 12:48:40 PM PDT 24	May 05 12:48:43 PM PDT 24	348037745 ps
T205	/workspace/coverage/default/36.sram_ctrl_smoke.3487590807	May 05 12:53:29 PM PDT 24	May 05 12:53:43 PM PDT 24	3792687679 ps
T206	/workspace/coverage/default/4.sram_ctrl_ram_cfg.1841613634	May 05 12:48:04 PM PDT 24	May 05 12:48:08 PM PDT 24	347989907 ps
T207	/workspace/coverage/default/14.sram_ctrl_max_throughput.4003427631	May 05 12:48:55 PM PDT 24	May 05 12:50:42 PM PDT 24	773944813 ps
T208	/workspace/coverage/default/19.sram_ctrl_mem_partial_access.2235950272	May 05 12:49:50 PM PDT 24	May 05 12:50:50 PM PDT 24	8596538048 ps
T209	/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.707257418	May 05 12:48:28 PM PDT 24	May 05 12:48:36 PM PDT 24	2800814917 ps
T51	/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1900925106	May 05 12:48:21 PM PDT 24	May 05 12:48:40 PM PDT 24	1335334947 ps
T210	/workspace/coverage/default/21.sram_ctrl_alert_test.3833006107	May 05 12:50:12 PM PDT 24	May 05 12:50:13 PM PDT 24	45224176 ps
T211	/workspace/coverage/default/4.sram_ctrl_smoke.2615781722	May 05 12:48:01 PM PDT 24	May 05 12:48:43 PM PDT 24	432432049 ps
T212	/workspace/coverage/default/43.sram_ctrl_alert_test.4084492706	May 05 12:55:24 PM PDT 24	May 05 12:55:25 PM PDT 24	20545753 ps
T213	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1832731756	May 05 12:48:40 PM PDT 24	May 05 12:51:42 PM PDT 24	3151659198 ps
T214	/workspace/coverage/default/41.sram_ctrl_bijection.44517222	May 05 12:54:37 PM PDT 24	May 05 01:03:50 PM PDT 24	16755588986 ps
T215	/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1133488992	May 05 12:55:19 PM PDT 24	May 05 01:09:29 PM PDT 24	71279035406 ps
T216	/workspace/coverage/default/14.sram_ctrl_access_during_key_req.322930913	May 05 12:48:54 PM PDT 24	May 05 12:59:09 PM PDT 24	7764374881 ps
T217	/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.243611162	May 05 12:48:41 PM PDT 24	May 05 12:55:22 PM PDT 24	17028886574 ps
T218	/workspace/coverage/default/34.sram_ctrl_alert_test.1470110186	May 05 12:53:15 PM PDT 24	May 05 12:53:17 PM PDT 24	18612800 ps
T219	/workspace/coverage/default/2.sram_ctrl_partial_access.937606449	May 05 12:47:54 PM PDT 24	May 05 12:48:12 PM PDT 24	826125899 ps
T220	/workspace/coverage/default/44.sram_ctrl_bijection.2927638160	May 05 12:55:23 PM PDT 24	May 05 01:18:45 PM PDT 24	21748561479 ps
T221	/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2895284132	May 05 12:48:18 PM PDT 24	May 05 12:52:28 PM PDT 24	5004096619 ps
T222	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2202238933	May 05 12:50:00 PM PDT 24	May 05 12:55:41 PM PDT 24	6311705346 ps
T223	/workspace/coverage/default/35.sram_ctrl_bijection.3429761692	May 05 12:53:18 PM PDT 24	May 05 01:20:52 PM PDT 24	246098409632 ps
T224	/workspace/coverage/default/12.sram_ctrl_stress_pipeline.520845375	May 05 12:48:41 PM PDT 24	May 05 12:52:47 PM PDT 24	3198190375 ps
T225	/workspace/coverage/default/41.sram_ctrl_ram_cfg.78077177	May 05 12:54:51 PM PDT 24	May 05 12:54:55 PM PDT 24	1397727550 ps
T226	/workspace/coverage/default/26.sram_ctrl_max_throughput.984896170	May 05 12:50:59 PM PDT 24	May 05 12:52:23 PM PDT 24	803098806 ps
T52	/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3657919488	May 05 12:55:33 PM PDT 24	May 05 12:55:56 PM PDT 24	790497842 ps
T227	/workspace/coverage/default/14.sram_ctrl_bijection.4231535903	May 05 12:48:55 PM PDT 24	May 05 01:01:10 PM PDT 24	32936543917 ps
T53	/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.185368768	May 05 12:48:01 PM PDT 24	May 05 12:48:10 PM PDT 24	235475474 ps
T228	/workspace/coverage/default/15.sram_ctrl_ram_cfg.2386393937	May 05 12:49:06 PM PDT 24	May 05 12:49:09 PM PDT 24	437763612 ps
T229	/workspace/coverage/default/20.sram_ctrl_mem_walk.2448257636	May 05 12:49:53 PM PDT 24	May 05 12:52:10 PM PDT 24	14073008509 ps
T230	/workspace/coverage/default/46.sram_ctrl_regwen.3197377610	May 05 12:55:56 PM PDT 24	May 05 01:11:08 PM PDT 24	3987188768 ps
T231	/workspace/coverage/default/34.sram_ctrl_multiple_keys.588146068	May 05 12:52:58 PM PDT 24	May 05 12:59:19 PM PDT 24	17135212730 ps
T232	/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.695505224	May 05 12:47:55 PM PDT 24	May 05 12:48:25 PM PDT 24	728640086 ps
T233	/workspace/coverage/default/6.sram_ctrl_smoke.3188005852	May 05 12:48:14 PM PDT 24	May 05 12:48:23 PM PDT 24	433654383 ps
T234	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2584115199	May 05 12:52:29 PM PDT 24	May 05 12:53:50 PM PDT 24	787650851 ps
T235	/workspace/coverage/default/39.sram_ctrl_multiple_keys.2470193615	May 05 12:54:15 PM PDT 24	May 05 01:09:03 PM PDT 24	26756387030 ps
T236	/workspace/coverage/default/38.sram_ctrl_multiple_keys.3442196228	May 05 12:54:02 PM PDT 24	May 05 01:06:17 PM PDT 24	17547818666 ps
T237	/workspace/coverage/default/32.sram_ctrl_access_during_key_req.257088918	May 05 12:52:38 PM PDT 24	May 05 12:55:37 PM PDT 24	8442335973 ps
T238	/workspace/coverage/default/30.sram_ctrl_multiple_keys.1913380792	May 05 12:51:53 PM PDT 24	May 05 01:08:25 PM PDT 24	19329857075 ps
T239	/workspace/coverage/default/13.sram_ctrl_multiple_keys.1498244640	May 05 12:48:41 PM PDT 24	May 05 12:59:46 PM PDT 24	14403103768 ps
T240	/workspace/coverage/default/28.sram_ctrl_multiple_keys.3218003642	May 05 12:51:28 PM PDT 24	May 05 01:14:28 PM PDT 24	28763862458 ps
T241	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1179148356	May 05 12:48:11 PM PDT 24	May 05 12:51:21 PM PDT 24	10512214324 ps
T242	/workspace/coverage/default/25.sram_ctrl_multiple_keys.3526464182	May 05 12:50:49 PM PDT 24	May 05 01:05:08 PM PDT 24	51452169291 ps
T243	/workspace/coverage/default/6.sram_ctrl_regwen.983451370	May 05 12:48:19 PM PDT 24	May 05 12:53:58 PM PDT 24	2325916597 ps
T54	/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.569263414	May 05 12:50:32 PM PDT 24	May 05 12:51:01 PM PDT 24	745281361 ps
T244	/workspace/coverage/default/37.sram_ctrl_smoke.4087167826	May 05 12:53:47 PM PDT 24	May 05 12:55:34 PM PDT 24	2787106117 ps
T245	/workspace/coverage/default/0.sram_ctrl_bijection.1230214635	May 05 12:47:51 PM PDT 24	May 05 01:30:12 PM PDT 24	318323300421 ps
T24	/workspace/coverage/default/14.sram_ctrl_lc_escalation.1435264282	May 05 12:48:55 PM PDT 24	May 05 12:49:26 PM PDT 24	17400168643 ps
T246	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3287169322	May 05 12:52:59 PM PDT 24	May 05 12:56:56 PM PDT 24	2135009801 ps
T247	/workspace/coverage/default/0.sram_ctrl_stress_pipeline.787086602	May 05 12:47:50 PM PDT 24	May 05 12:51:00 PM PDT 24	3914503217 ps
T248	/workspace/coverage/default/11.sram_ctrl_executable.200963685	May 05 12:48:33 PM PDT 24	May 05 12:55:24 PM PDT 24	25214270658 ps
T14	/workspace/coverage/default/2.sram_ctrl_sec_cm.1042144967	May 05 12:48:08 PM PDT 24	May 05 12:48:11 PM PDT 24	203549971 ps
T32	/workspace/coverage/default/15.sram_ctrl_alert_test.1532071208	May 05 12:49:09 PM PDT 24	May 05 12:49:10 PM PDT 24	14489443 ps
T33	/workspace/coverage/default/42.sram_ctrl_partial_access.3211170989	May 05 12:54:56 PM PDT 24	May 05 12:55:19 PM PDT 24	3649096764 ps
T34	/workspace/coverage/default/49.sram_ctrl_alert_test.1437895945	May 05 12:56:48 PM PDT 24	May 05 12:56:49 PM PDT 24	113874429 ps
T35	/workspace/coverage/default/48.sram_ctrl_alert_test.477590564	May 05 12:56:33 PM PDT 24	May 05 12:56:34 PM PDT 24	27778933 ps
T36	/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2595971064	May 05 12:49:36 PM PDT 24	May 05 12:51:16 PM PDT 24	6355729056 ps
T37	/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1999399723	May 05 12:51:43 PM PDT 24	May 05 12:52:48 PM PDT 24	918396574 ps
T38	/workspace/coverage/default/45.sram_ctrl_regwen.4230233030	May 05 12:55:50 PM PDT 24	May 05 01:01:29 PM PDT 24	16820785821 ps
T39	/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1239507332	May 05 12:56:12 PM PDT 24	May 05 12:56:53 PM PDT 24	6167066132 ps
T40	/workspace/coverage/default/33.sram_ctrl_stress_all.537209035	May 05 12:52:58 PM PDT 24	May 05 01:08:46 PM PDT 24	33359918041 ps
T249	/workspace/coverage/default/38.sram_ctrl_regwen.1664879627	May 05 12:54:06 PM PDT 24	May 05 12:55:58 PM PDT 24	1324091551 ps
T250	/workspace/coverage/default/36.sram_ctrl_partial_access.1201890532	May 05 12:53:37 PM PDT 24	May 05 12:54:03 PM PDT 24	6049160396 ps
T251	/workspace/coverage/default/42.sram_ctrl_bijection.2101236617	May 05 12:54:56 PM PDT 24	May 05 01:08:26 PM PDT 24	210870561733 ps
T252	/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.866397518	May 05 12:55:29 PM PDT 24	May 05 12:59:11 PM PDT 24	90149651894 ps
T253	/workspace/coverage/default/31.sram_ctrl_multiple_keys.2728048422	May 05 12:52:09 PM PDT 24	May 05 01:08:18 PM PDT 24	71458305790 ps
T106	/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3992707254	May 05 12:48:48 PM PDT 24	May 05 12:49:00 PM PDT 24	463086760 ps
T254	/workspace/coverage/default/21.sram_ctrl_stress_all.3758117195	May 05 12:50:04 PM PDT 24	May 05 12:56:52 PM PDT 24	12181471454 ps
T255	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.2284505638	May 05 12:48:58 PM PDT 24	May 05 12:50:08 PM PDT 24	4718434839 ps
T15	/workspace/coverage/default/3.sram_ctrl_sec_cm.607966418	May 05 12:48:00 PM PDT 24	May 05 12:48:04 PM PDT 24	743119616 ps
T256	/workspace/coverage/default/0.sram_ctrl_multiple_keys.2670405781	May 05 12:47:54 PM PDT 24	May 05 12:52:37 PM PDT 24	15352020983 ps
T257	/workspace/coverage/default/25.sram_ctrl_stress_all.3983631268	May 05 12:50:58 PM PDT 24	May 05 01:52:40 PM PDT 24	340800352395 ps
T16	/workspace/coverage/default/0.sram_ctrl_sec_cm.3477311182	May 05 12:47:57 PM PDT 24	May 05 12:48:00 PM PDT 24	138178936 ps
T258	/workspace/coverage/default/45.sram_ctrl_stress_pipeline.525104610	May 05 12:55:40 PM PDT 24	May 05 12:59:45 PM PDT 24	4258623060 ps
T259	/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1587296161	May 05 12:53:03 PM PDT 24	May 05 12:53:22 PM PDT 24	711428567 ps
T260	/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2055192578	May 05 12:52:06 PM PDT 24	May 05 12:52:20 PM PDT 24	856030549 ps
T261	/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1306538685	May 05 12:48:21 PM PDT 24	May 05 12:56:36 PM PDT 24	86423277605 ps
T262	/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3834174360	May 05 12:48:13 PM PDT 24	May 05 12:49:31 PM PDT 24	26492471832 ps
T263	/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3553775607	May 05 12:49:27 PM PDT 24	May 05 12:55:20 PM PDT 24	31206351884 ps
T264	/workspace/coverage/default/48.sram_ctrl_stress_all.154198745	May 05 12:56:31 PM PDT 24	May 05 01:22:14 PM PDT 24	52097183489 ps
T265	/workspace/coverage/default/18.sram_ctrl_regwen.2518176069	May 05 12:49:33 PM PDT 24	May 05 12:57:40 PM PDT 24	19960554331 ps
T266	/workspace/coverage/default/30.sram_ctrl_max_throughput.3676523425	May 05 12:51:59 PM PDT 24	May 05 12:53:25 PM PDT 24	773643989 ps
T267	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.2025292455	May 05 12:51:31 PM PDT 24	May 05 12:53:13 PM PDT 24	13748420739 ps
T268	/workspace/coverage/default/9.sram_ctrl_max_throughput.2189874450	May 05 12:48:23 PM PDT 24	May 05 12:49:09 PM PDT 24	733128130 ps
T269	/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2666718796	May 05 12:54:46 PM PDT 24	May 05 12:58:08 PM PDT 24	11819443070 ps
T270	/workspace/coverage/default/8.sram_ctrl_ram_cfg.3160415057	May 05 12:48:19 PM PDT 24	May 05 12:48:23 PM PDT 24	706137484 ps
T271	/workspace/coverage/default/44.sram_ctrl_executable.62280621	May 05 12:55:33 PM PDT 24	May 05 01:17:44 PM PDT 24	12114216736 ps
T272	/workspace/coverage/default/38.sram_ctrl_partial_access.946213231	May 05 12:54:02 PM PDT 24	May 05 12:54:21 PM PDT 24	618783746 ps
T273	/workspace/coverage/default/5.sram_ctrl_access_during_key_req.4070371459	May 05 12:48:07 PM PDT 24	May 05 01:12:51 PM PDT 24	82527233758 ps
T274	/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3697572156	May 05 12:55:16 PM PDT 24	May 05 12:55:28 PM PDT 24	316514367 ps
T275	/workspace/coverage/default/43.sram_ctrl_multiple_keys.2526385597	May 05 12:55:12 PM PDT 24	May 05 01:05:29 PM PDT 24	81096631748 ps
T276	/workspace/coverage/default/3.sram_ctrl_regwen.2275994939	May 05 12:47:59 PM PDT 24	May 05 12:57:54 PM PDT 24	11373240311 ps
T277	/workspace/coverage/default/29.sram_ctrl_regwen.2833463525	May 05 12:51:47 PM PDT 24	May 05 01:03:30 PM PDT 24	4120480243 ps
T278	/workspace/coverage/default/8.sram_ctrl_partial_access.595796659	May 05 12:48:20 PM PDT 24	May 05 12:48:31 PM PDT 24	1579356713 ps
T279	/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1186065400	May 05 12:53:20 PM PDT 24	May 05 12:53:31 PM PDT 24	760536599 ps
T280	/workspace/coverage/default/32.sram_ctrl_lc_escalation.3941769788	May 05 12:52:30 PM PDT 24	May 05 12:53:34 PM PDT 24	19579495113 ps
T281	/workspace/coverage/default/6.sram_ctrl_multiple_keys.1265269911	May 05 12:48:11 PM PDT 24	May 05 01:26:31 PM PDT 24	30849602421 ps
T282	/workspace/coverage/default/47.sram_ctrl_alert_test.3320657821	May 05 12:56:17 PM PDT 24	May 05 12:56:18 PM PDT 24	17680781 ps
T283	/workspace/coverage/default/37.sram_ctrl_executable.1928652680	May 05 12:53:51 PM PDT 24	May 05 01:07:55 PM PDT 24	15541059432 ps
T284	/workspace/coverage/default/1.sram_ctrl_ram_cfg.1786922213	May 05 12:47:58 PM PDT 24	May 05 12:48:03 PM PDT 24	4221294054 ps
T285	/workspace/coverage/default/35.sram_ctrl_multiple_keys.668044022	May 05 12:53:20 PM PDT 24	May 05 01:12:39 PM PDT 24	63043152577 ps
T286	/workspace/coverage/default/17.sram_ctrl_ram_cfg.2558919228	May 05 12:49:22 PM PDT 24	May 05 12:49:27 PM PDT 24	1402530322 ps
T287	/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3784401596	May 05 12:48:28 PM PDT 24	May 05 12:56:31 PM PDT 24	84110592648 ps
T288	/workspace/coverage/default/46.sram_ctrl_access_during_key_req.135274099	May 05 12:55:56 PM PDT 24	May 05 01:03:42 PM PDT 24	7855858425 ps
T289	/workspace/coverage/default/0.sram_ctrl_stress_all.1391198925	May 05 12:47:55 PM PDT 24	May 05 02:26:09 PM PDT 24	149202493608 ps
T290	/workspace/coverage/default/12.sram_ctrl_access_during_key_req.261503330	May 05 12:48:38 PM PDT 24	May 05 12:52:24 PM PDT 24	3591052983 ps
T291	/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2604201445	May 05 12:48:54 PM PDT 24	May 05 12:53:09 PM PDT 24	12293897426 ps
T292	/workspace/coverage/default/2.sram_ctrl_max_throughput.667184289	May 05 12:48:06 PM PDT 24	May 05 12:48:29 PM PDT 24	747143250 ps
T293	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2462802116	May 05 12:55:57 PM PDT 24	May 05 12:56:30 PM PDT 24	755407325 ps
T294	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.1054598328	May 05 12:54:18 PM PDT 24	May 05 01:02:08 PM PDT 24	39311835120 ps
T295	/workspace/coverage/default/5.sram_ctrl_max_throughput.3646424306	May 05 12:48:06 PM PDT 24	May 05 12:48:23 PM PDT 24	731611246 ps
T296	/workspace/coverage/default/17.sram_ctrl_regwen.736033456	May 05 12:49:21 PM PDT 24	May 05 01:02:12 PM PDT 24	13759580363 ps
T297	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.130888814	May 05 12:49:28 PM PDT 24	May 05 12:49:35 PM PDT 24	1398109553 ps
T298	/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3419148443	May 05 12:48:07 PM PDT 24	May 05 12:50:25 PM PDT 24	1014377834 ps
T299	/workspace/coverage/default/27.sram_ctrl_multiple_keys.443043526	May 05 12:51:16 PM PDT 24	May 05 01:09:45 PM PDT 24	21328033440 ps