Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	135298886	1			T1	1411		T2	82572		T3	8492
triple_byte_access	2891598	1			T1	31		T2	1646		T3	160
halfword_access	4423234	1			T1	50		T2	2456		T3	261
byte_access	6162535	1			T1	39		T2	3215		T3	340
zero_access	1834098	1			T1	18		T2	885		T3	81

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75243604

1

T1

772

T2

51423

T3

4675

auto[1]

75366747

1

T1

777

T2

39351

T3

4659

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	67433941	1			T1	707		T2	46713		T3	4249
auto[0]	triple_byte_access	1389748	1			T1	11		T2	960		T3	80
auto[0]	halfword_access	2173707	1			T1	27		T2	1400		T3	122
auto[0]	byte_access	3161546	1			T1	19		T2	1847		T3	188
auto[0]	zero_access	1084662	1			T1	8		T2	503		T3	36
auto[1]	word_access	67864945	1			T1	704		T2	35859		T3	4243
auto[1]	triple_byte_access	1501850	1			T1	20		T2	686		T3	80
auto[1]	halfword_access	2249527	1			T1	23		T2	1056		T3	139
auto[1]	byte_access	3000989	1			T1	20		T2	1368		T3	152
auto[1]	zero_access	749436	1			T1	10		T2	382		T3	45