Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	360627562	1			T1	490985		T2	12220		T3	293961
instr_valid_dis	322549332	1			T1	479230		T2	12220		T3	276485
instr_en	27084461	1			T1	74698		T3	160458		T5	227124

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	17889282	1			T1	101456		T3	188108		T13	948
sram_ifetch_valid_disable	320919080	1			T1	446520		T2	12220		T3	267598
sram_ifetch_enable	21819200	1			T1	343190		T3	75524		T25	140434

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	360627562	1			T1	490985		T2	12220		T3	293961
hw_debug_en_valid_off	321260064	1			T1	462474		T2	12220		T3	245239
hw_debug_en_on	30067080	1			T1	144178		T3	249502		T13	68782

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	320919080	1			T1	446520		T2	12220		T3	267598
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	302857942	1			T1	441564		T2	12220		T3	266378
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13244801	1			T1	9558		T5	227124		T13	87368
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5835516	1			T1	79444		T3	16226		T25	11926
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	3697964	1			T1	79444		T3	16226		T21	12806
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1292952	1			T25	11926		T21	43892		T59	91946
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	10144086	1			T1	7778		T3	119146		T21	14272
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	4369804	1			T1	7778		T3	80020		T21	1364
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	4569874	1			T3	39126		T41	29436		T59	16020
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11525830	1			T1	97388		T3	117626		T13	68782
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3511180	1			T1	97388		T3	117626		T21	176650
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	6369508	1			T25	41890		T21	6478		T41	27706

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7370200	1			T1	65140		T3	68596		T25	52310
lc_exec_en	8397164	1			T1	39012		T3	12730		T25	30742
valid_exec_dis	316123918	1			T1	458497		T2	12220		T3	244099
invalid_exec_dis	39708482	1			T1	444646		T3	263632		T13	948