Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	151888099	1			T1	224430		T2	5538		T3	132005
triple_byte_access	2726548	1			T1	3014		T2	120		T3	2868
halfword_access	4185481	1			T1	4315		T2	185		T3	4345
byte_access	5862876	1			T1	5771		T2	215		T3	5731
zero_access	1786168	1			T1	1472		T2	52		T3	1459

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82881154

1

T1

113778

T2

3090

T3

682737

auto[1]

83568018

1

T1

112108

T2

3020

T3

651723

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	75471250	1			T1	112959		T2	2828		T3	674246
auto[0]	triple_byte_access	1296514	1			T1	1679		T2	53		T3	1698
auto[0]	halfword_access	2039020	1			T1	2435		T2	86		T3	2560
auto[0]	byte_access	3002698	1			T1	3226		T2	95		T3	3407
auto[0]	zero_access	1071672	1			T1	852		T2	28		T3	826
auto[1]	word_access	76416849	1			T1	111470		T2	2710		T3	645811
auto[1]	triple_byte_access	1430034	1			T1	1335		T2	67		T3	1170
auto[1]	halfword_access	2146461	1			T1	1880		T2	99		T3	1785
auto[1]	byte_access	2860178	1			T1	2545		T2	120		T3	2324
auto[1]	zero_access	714496	1			T1	620		T2	24		T3	633