Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	351136332	1			T1	65120		T2	282604		T3	14672
instr_valid_dis	305827303	1			T1	65120		T3	14672		T8	327680
instr_en	27124233	1			T4	597364		T13	24218		T57	64682

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	14614418	1			T2	66290		T4	235270		T13	15004
sram_ifetch_valid_disable	309869753	1			T1	65120		T2	56736		T3	14672
sram_ifetch_enable	26652161	1			T2	159578		T4	465518		T22	50462

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	351136332	1			T1	65120		T2	282604		T3	14672
hw_debug_en_valid_off	309545683	1			T1	65120		T2	122000		T3	14672
hw_debug_en_on	29226194	1			T2	160604		T4	436012		T13	55422

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	309869753	1			T1	65120		T2	56736		T3	14672
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	293042443	1			T1	65120		T3	14672		T8	327680
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9982778	1			T4	206712		T13	24218		T57	6994
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3981468	1			T2	66290		T4	96208		T58	14096
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1701538	1			T23	638		T24	96		T46	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1568976	1			T4	96208		T60	13692		T129	9476
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7928656	1			T4	100324		T13	15004		T59	129636
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2230690	1			T4	45714		T13	15004		T59	36400
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	4996156	1			T4	24594		T59	73236		T60	74454
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10804096	1			T2	56736		T4	143282		T13	40418
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3413806	1			T4	38716		T13	16200		T57	70464
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3952292	1			T4	104566		T13	24218		T57	6994

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9534951	1			T4	269850		T57	57688		T59	533838
lc_exec_en	10493442	1			T2	103868		T4	192406		T57	15018
valid_exec_dis	302241117	1			T1	65120		T3	14672		T8	327680
invalid_exec_dis	41266579	1			T2	225868		T4	700788		T13	15004