Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52


Total tests in report: 1037
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
82.44 82.44 96.82 96.82 80.52 80.52 94.60 94.60 71.43 71.43 90.42 90.42 94.65 94.65 48.61 48.61 /workspace/coverage/default/32.sram_ctrl_stress_all.65998718
90.02 7.58 98.13 1.31 84.29 3.77 95.24 0.64 100.00 28.57 94.65 4.23 94.95 0.30 62.89 14.29 /workspace/coverage/default/16.sram_ctrl_stress_all.580329106
94.42 4.40 98.88 0.75 88.44 4.16 96.16 0.92 100.00 0.00 95.77 1.13 96.73 1.78 84.97 22.08 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3877601959
95.47 1.05 99.06 0.19 89.35 0.91 96.38 0.21 100.00 0.00 96.62 0.85 96.73 0.00 90.17 5.19 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1846122116
96.26 0.79 99.25 0.19 91.17 1.82 98.22 1.85 100.00 0.00 97.75 1.13 96.73 0.00 90.72 0.56 /workspace/coverage/default/0.sram_ctrl_regwen.3364223666
96.92 0.65 99.44 0.19 93.38 2.21 98.58 0.36 100.00 0.00 98.59 0.85 97.33 0.59 91.09 0.37 /workspace/coverage/default/3.sram_ctrl_sec_cm.473777298
97.25 0.33 99.72 0.28 93.51 0.13 98.58 0.00 100.00 0.00 98.87 0.28 97.47 0.15 92.58 1.48 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.465307294
97.55 0.30 99.72 0.00 93.51 0.00 98.65 0.07 100.00 0.00 98.87 0.00 97.47 0.00 94.62 2.04 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.955105879
97.77 0.22 99.72 0.00 93.64 0.13 98.79 0.14 100.00 0.00 98.87 0.00 97.47 0.00 95.92 1.30 /workspace/coverage/default/2.sram_ctrl_stress_all.494127206
97.97 0.20 99.72 0.00 93.64 0.00 98.86 0.07 100.00 0.00 98.87 0.00 98.81 1.34 95.92 0.00 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3543061496
98.17 0.20 99.72 0.00 94.03 0.39 99.29 0.43 100.00 0.00 98.87 0.00 98.81 0.00 96.47 0.56 /workspace/coverage/default/0.sram_ctrl_alert_test.4247163511
98.32 0.15 99.72 0.00 94.16 0.13 99.29 0.00 100.00 0.00 98.87 0.00 99.70 0.89 96.47 0.00 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3982102578
98.43 0.11 99.81 0.09 94.16 0.00 100.00 0.71 100.00 0.00 98.87 0.00 99.70 0.00 96.47 0.00 /workspace/coverage/default/11.sram_ctrl_ram_cfg.2653635530
98.51 0.08 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.00 97.03 0.56 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2634134998
98.59 0.08 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.00 97.59 0.56 /workspace/coverage/default/14.sram_ctrl_stress_all.3478312594
98.64 0.05 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.00 97.96 0.37 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1867418657
98.67 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.00 98.14 0.19 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1598332887
98.70 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.00 98.33 0.19 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.888182862
98.72 0.03 99.81 0.00 94.16 0.00 100.00 0.00 100.00 0.00 98.87 0.00 99.70 0.00 98.52 0.19 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.327536850

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1864436960
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3216526154
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4087115234
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2784155575
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2311785580
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.793754889
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.824045609
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3641873562
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.126268814
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3089400005
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3541541172
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1637113771
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3369780915
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.692114415
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3511420147
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1546294968
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.366340585
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2520113405
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4068962371
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3323327505
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3877909499
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2606373313
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1594302375
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1555366131
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2664733368
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1473336554
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3559577338
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3636617577
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2265316043
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3517690969
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3916597312
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.513689560
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.269786528
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.591524871
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3714037877
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2584540468
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.205954756
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.524708614
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1511665302
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.788717225
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.349587580
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2176388478
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1113343671
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2680070256
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1219816502
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1859326279
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.344094086
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4025237734
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2481022850
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2856354817
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2383989959
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1895988100
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3280042241
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1051663893
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3857218427
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3004368440
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1776913313
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2882076396
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4131410285
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3987452170
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3595077248
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.369705895
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1505340690
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1596330571
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4049933091
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3850830879
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4265893916
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1840553896
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2644726240
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4230261151
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3621563746
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2543193935
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.746196147
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2738736185
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.126974300
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2369393699
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2020754929
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2751562579
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3569254921
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2221846498
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2962101580
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3162834195
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2980310687
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2813089930
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3049827880
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1460547940
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.104334076
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2493098475
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.267207013
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1620287530
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2440627009
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.124138670
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2122807642
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2801693746
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2663515950
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1213337968
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3706615512
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2166214569
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2146858038
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.545498322
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1782582138
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3432337463
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.952697605
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.83409100
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1509046809
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.643667
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1332830027
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3091473729
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3317799689
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1542063972
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2044520333
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3233375142
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2083393086
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.249605134
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3822326028
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3160330126
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4039610842
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.230229489
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.842588469
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1410327910
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1609707783
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.952467867
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.100299987
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2123564452
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2253905011
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3730624893
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3548388434
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1495837355
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.338223840
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2849610823
/workspace/coverage/default/0.sram_ctrl_bijection.2700858672
/workspace/coverage/default/0.sram_ctrl_executable.3804903404
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3050789788
/workspace/coverage/default/0.sram_ctrl_max_throughput.416648248
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3780795707
/workspace/coverage/default/0.sram_ctrl_mem_walk.3903632115
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3560090984
/workspace/coverage/default/0.sram_ctrl_partial_access.3667120374
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.432379053
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1416800349
/workspace/coverage/default/0.sram_ctrl_sec_cm.2139738564
/workspace/coverage/default/0.sram_ctrl_smoke.231635104
/workspace/coverage/default/0.sram_ctrl_stress_all.3826766559
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.4251952226
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1241281130
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.307761540
/workspace/coverage/default/1.sram_ctrl_alert_test.3652377881
/workspace/coverage/default/1.sram_ctrl_bijection.2263555897
/workspace/coverage/default/1.sram_ctrl_executable.1615297187
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3903158709
/workspace/coverage/default/1.sram_ctrl_max_throughput.2197235499
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1821981602
/workspace/coverage/default/1.sram_ctrl_mem_walk.1205176412
/workspace/coverage/default/1.sram_ctrl_multiple_keys.4087992114
/workspace/coverage/default/1.sram_ctrl_partial_access.117808043
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2446067661
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1760787248
/workspace/coverage/default/1.sram_ctrl_regwen.683472596
/workspace/coverage/default/1.sram_ctrl_sec_cm.2602462047
/workspace/coverage/default/1.sram_ctrl_smoke.3393417986
/workspace/coverage/default/1.sram_ctrl_stress_all.3086244827
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1849672444
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.645049244
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1630607657
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3105190006
/workspace/coverage/default/10.sram_ctrl_alert_test.1750035191
/workspace/coverage/default/10.sram_ctrl_bijection.2215459665
/workspace/coverage/default/10.sram_ctrl_executable.2584882051
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3766539979
/workspace/coverage/default/10.sram_ctrl_max_throughput.1352678876
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.792049909
/workspace/coverage/default/10.sram_ctrl_mem_walk.2044546235
/workspace/coverage/default/10.sram_ctrl_multiple_keys.72886996
/workspace/coverage/default/10.sram_ctrl_partial_access.3493995143
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2216769410
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1488882394
/workspace/coverage/default/10.sram_ctrl_regwen.2515514344
/workspace/coverage/default/10.sram_ctrl_smoke.1127337034
/workspace/coverage/default/10.sram_ctrl_stress_all.3101417251
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2867148694
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.4285870681
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2338930131
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3520879172
/workspace/coverage/default/11.sram_ctrl_alert_test.2607042249
/workspace/coverage/default/11.sram_ctrl_bijection.2712968349
/workspace/coverage/default/11.sram_ctrl_executable.800885550
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1526683438
/workspace/coverage/default/11.sram_ctrl_max_throughput.2097481565
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.166549686
/workspace/coverage/default/11.sram_ctrl_mem_walk.1594933625
/workspace/coverage/default/11.sram_ctrl_multiple_keys.4147215656
/workspace/coverage/default/11.sram_ctrl_partial_access.1752094896
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.804248444
/workspace/coverage/default/11.sram_ctrl_regwen.2403317074
/workspace/coverage/default/11.sram_ctrl_smoke.3847032687
/workspace/coverage/default/11.sram_ctrl_stress_all.3244289308
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1795879663
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1958657270
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.27207989
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1026311808
/workspace/coverage/default/12.sram_ctrl_alert_test.292378572
/workspace/coverage/default/12.sram_ctrl_bijection.1669178821
/workspace/coverage/default/12.sram_ctrl_executable.2157106203
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1762539859
/workspace/coverage/default/12.sram_ctrl_max_throughput.1883782310
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.973734993
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/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2714965000
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.883488896
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.600316191
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3076214706
/workspace/coverage/default/43.sram_ctrl_alert_test.24064489
/workspace/coverage/default/43.sram_ctrl_bijection.2623538872
/workspace/coverage/default/43.sram_ctrl_executable.3546842564
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3183807047
/workspace/coverage/default/43.sram_ctrl_max_throughput.2516174345
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.15409907
/workspace/coverage/default/43.sram_ctrl_mem_walk.1443731054
/workspace/coverage/default/43.sram_ctrl_multiple_keys.143445220
/workspace/coverage/default/43.sram_ctrl_partial_access.2716029698
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2729918233
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1960900386
/workspace/coverage/default/43.sram_ctrl_regwen.508550090
/workspace/coverage/default/43.sram_ctrl_smoke.128784327
/workspace/coverage/default/43.sram_ctrl_stress_all.1975457862
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.244694924
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3336522519
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.279102208
/workspace/coverage/default/44.sram_ctrl_alert_test.1370807208
/workspace/coverage/default/44.sram_ctrl_bijection.1285714939
/workspace/coverage/default/44.sram_ctrl_executable.532873531
/workspace/coverage/default/44.sram_ctrl_lc_escalation.4221458920
/workspace/coverage/default/44.sram_ctrl_max_throughput.196752281
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3699534134
/workspace/coverage/default/44.sram_ctrl_mem_walk.2453438567
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1213273493
/workspace/coverage/default/44.sram_ctrl_partial_access.3552930643
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.679912127
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3545756924
/workspace/coverage/default/44.sram_ctrl_regwen.3250054967
/workspace/coverage/default/44.sram_ctrl_smoke.4143786652
/workspace/coverage/default/44.sram_ctrl_stress_all.605832234
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3273307760
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.622660663
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.455991886
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.332336802
/workspace/coverage/default/45.sram_ctrl_alert_test.4255616041
/workspace/coverage/default/45.sram_ctrl_bijection.1507631021
/workspace/coverage/default/45.sram_ctrl_executable.941011395
/workspace/coverage/default/45.sram_ctrl_lc_escalation.155081575
/workspace/coverage/default/45.sram_ctrl_max_throughput.287741588
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3842972490
/workspace/coverage/default/45.sram_ctrl_mem_walk.1322639803
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1076875813
/workspace/coverage/default/45.sram_ctrl_partial_access.3638456343
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2370512117
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1852048539
/workspace/coverage/default/45.sram_ctrl_regwen.2984096871
/workspace/coverage/default/45.sram_ctrl_smoke.1734108863
/workspace/coverage/default/45.sram_ctrl_stress_all.3968633256
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.725220353
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2040109889
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1719840742
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1204486715
/workspace/coverage/default/46.sram_ctrl_alert_test.1254618363
/workspace/coverage/default/46.sram_ctrl_bijection.1118507021
/workspace/coverage/default/46.sram_ctrl_executable.3956573273
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3375945163
/workspace/coverage/default/46.sram_ctrl_max_throughput.305319375
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.4016066753
/workspace/coverage/default/46.sram_ctrl_mem_walk.4216566951
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1926744733
/workspace/coverage/default/46.sram_ctrl_partial_access.2737754009
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1695236309
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3535057391
/workspace/coverage/default/46.sram_ctrl_regwen.898673596
/workspace/coverage/default/46.sram_ctrl_smoke.97060904
/workspace/coverage/default/46.sram_ctrl_stress_all.1353250347
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.4233109823
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1097753284
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2887286311
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1523176687
/workspace/coverage/default/47.sram_ctrl_alert_test.4237152820
/workspace/coverage/default/47.sram_ctrl_bijection.2173793939
/workspace/coverage/default/47.sram_ctrl_executable.2387803392
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3146142500
/workspace/coverage/default/47.sram_ctrl_max_throughput.740813957
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.4161607518
/workspace/coverage/default/47.sram_ctrl_mem_walk.367965364
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2606391247
/workspace/coverage/default/47.sram_ctrl_partial_access.2737635089
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3397355557
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3331585260
/workspace/coverage/default/47.sram_ctrl_regwen.468222585
/workspace/coverage/default/47.sram_ctrl_smoke.3800102256
/workspace/coverage/default/47.sram_ctrl_stress_all.1984354873
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2559769866
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2033324516
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3223094517
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1205942533
/workspace/coverage/default/48.sram_ctrl_alert_test.3687924873
/workspace/coverage/default/48.sram_ctrl_bijection.3352190307
/workspace/coverage/default/48.sram_ctrl_executable.1716530945
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2900427904
/workspace/coverage/default/48.sram_ctrl_max_throughput.1536629279
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1596104008
/workspace/coverage/default/48.sram_ctrl_mem_walk.3321286437
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3558252391
/workspace/coverage/default/48.sram_ctrl_partial_access.1620236712
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1149902505
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3746349917
/workspace/coverage/default/48.sram_ctrl_regwen.842614571
/workspace/coverage/default/48.sram_ctrl_smoke.2046485969
/workspace/coverage/default/48.sram_ctrl_stress_all.3090235743
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1609411797
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.616674236
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1539754742
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3733563918
/workspace/coverage/default/49.sram_ctrl_alert_test.759429240
/workspace/coverage/default/49.sram_ctrl_bijection.3583271352
/workspace/coverage/default/49.sram_ctrl_executable.3508786068
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2278275266
/workspace/coverage/default/49.sram_ctrl_max_throughput.3557258786
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2626216488
/workspace/coverage/default/49.sram_ctrl_mem_walk.2259612911
/workspace/coverage/default/49.sram_ctrl_multiple_keys.844348351
/workspace/coverage/default/49.sram_ctrl_partial_access.4083210795
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1717641822
/workspace/coverage/default/49.sram_ctrl_ram_cfg.463991071
/workspace/coverage/default/49.sram_ctrl_regwen.3420924147
/workspace/coverage/default/49.sram_ctrl_smoke.2389582858
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1384042407
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1047756860
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2963266881
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3106518608
/workspace/coverage/default/5.sram_ctrl_alert_test.2387686939
/workspace/coverage/default/5.sram_ctrl_executable.1599214163
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3953679006
/workspace/coverage/default/5.sram_ctrl_max_throughput.868184413
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1334517250
/workspace/coverage/default/5.sram_ctrl_mem_walk.656753416
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1006876571
/workspace/coverage/default/5.sram_ctrl_partial_access.3742070131
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2357968265
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2387388154
/workspace/coverage/default/5.sram_ctrl_regwen.2049097924
/workspace/coverage/default/5.sram_ctrl_smoke.2264896333
/workspace/coverage/default/5.sram_ctrl_stress_all.4028244878
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2491589037
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1600458467
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1523315276
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3671979296
/workspace/coverage/default/6.sram_ctrl_alert_test.1055685182
/workspace/coverage/default/6.sram_ctrl_bijection.1629402761
/workspace/coverage/default/6.sram_ctrl_executable.1656177581
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2070359672
/workspace/coverage/default/6.sram_ctrl_max_throughput.905710767
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.321304874
/workspace/coverage/default/6.sram_ctrl_mem_walk.3870688994
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3380753519
/workspace/coverage/default/6.sram_ctrl_partial_access.964687370
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.701172381
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1621183402
/workspace/coverage/default/6.sram_ctrl_regwen.3850425852
/workspace/coverage/default/6.sram_ctrl_smoke.3727168894
/workspace/coverage/default/6.sram_ctrl_stress_all.2109402441
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.956948442
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3316768299
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3513370606
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3266799430
/workspace/coverage/default/7.sram_ctrl_alert_test.1684039149
/workspace/coverage/default/7.sram_ctrl_bijection.3334609770
/workspace/coverage/default/7.sram_ctrl_executable.1399316460
/workspace/coverage/default/7.sram_ctrl_lc_escalation.626321278
/workspace/coverage/default/7.sram_ctrl_max_throughput.3576516418
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3443656865
/workspace/coverage/default/7.sram_ctrl_mem_walk.3105566250
/workspace/coverage/default/7.sram_ctrl_multiple_keys.4107090125
/workspace/coverage/default/7.sram_ctrl_partial_access.496947503
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1091238089
/workspace/coverage/default/7.sram_ctrl_ram_cfg.571108203
/workspace/coverage/default/7.sram_ctrl_regwen.358123742
/workspace/coverage/default/7.sram_ctrl_smoke.2212314834
/workspace/coverage/default/7.sram_ctrl_stress_all.4035805558
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.14671662
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2362935402
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2723259705
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.813126904
/workspace/coverage/default/8.sram_ctrl_alert_test.1362500059
/workspace/coverage/default/8.sram_ctrl_bijection.3374866384
/workspace/coverage/default/8.sram_ctrl_executable.1499301613
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3187601511
/workspace/coverage/default/8.sram_ctrl_max_throughput.1691717521
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3435702242
/workspace/coverage/default/8.sram_ctrl_mem_walk.588239265
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1723102533
/workspace/coverage/default/8.sram_ctrl_partial_access.2585371378
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.561182261
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3954755356
/workspace/coverage/default/8.sram_ctrl_regwen.1432504521
/workspace/coverage/default/8.sram_ctrl_smoke.121885908
/workspace/coverage/default/8.sram_ctrl_stress_all.2891120659
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2925923264
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1649510836
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3751213423
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2197604619
/workspace/coverage/default/9.sram_ctrl_alert_test.2683259295
/workspace/coverage/default/9.sram_ctrl_bijection.3107963490
/workspace/coverage/default/9.sram_ctrl_executable.2737329632
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2099460791
/workspace/coverage/default/9.sram_ctrl_max_throughput.1553747544
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3645745439
/workspace/coverage/default/9.sram_ctrl_mem_walk.984121372
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2176394910
/workspace/coverage/default/9.sram_ctrl_partial_access.3791198683
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.734856052
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1992170718
/workspace/coverage/default/9.sram_ctrl_regwen.3854499814
/workspace/coverage/default/9.sram_ctrl_smoke.1469716454
/workspace/coverage/default/9.sram_ctrl_stress_all.1374935737
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2539037101
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.968362735
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1650764523



Total test records in report: 1037
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.449679071 May 09 02:01:24 PM PDT 24 May 09 02:02:41 PM PDT 24 9794339023 ps
T2 /workspace/coverage/default/36.sram_ctrl_regwen.2609004629 May 09 01:59:42 PM PDT 24 May 09 02:08:02 PM PDT 24 20015786949 ps
T3 /workspace/coverage/default/25.sram_ctrl_smoke.1403264467 May 09 01:56:02 PM PDT 24 May 09 01:56:19 PM PDT 24 1157395665 ps
T8 /workspace/coverage/default/28.sram_ctrl_bijection.995672148 May 09 01:56:56 PM PDT 24 May 09 02:40:31 PM PDT 24 115056339662 ps
T4 /workspace/coverage/default/32.sram_ctrl_stress_all.65998718 May 09 01:58:41 PM PDT 24 May 09 03:01:47 PM PDT 24 282172554296 ps
T9 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.217861106 May 09 02:01:02 PM PDT 24 May 09 02:06:14 PM PDT 24 14152486271 ps
T10 /workspace/coverage/default/9.sram_ctrl_smoke.1469716454 May 09 01:51:44 PM PDT 24 May 09 01:51:58 PM PDT 24 2969684188 ps
T11 /workspace/coverage/default/36.sram_ctrl_mem_walk.406759409 May 09 01:59:53 PM PDT 24 May 09 02:03:59 PM PDT 24 7882744376 ps
T12 /workspace/coverage/default/44.sram_ctrl_partial_access.3552930643 May 09 02:02:02 PM PDT 24 May 09 02:02:25 PM PDT 24 1411327687 ps
T13 /workspace/coverage/default/36.sram_ctrl_executable.269851079 May 09 01:59:49 PM PDT 24 May 09 02:01:57 PM PDT 24 4972401728 ps
T14 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.561182261 May 09 01:51:34 PM PDT 24 May 09 01:57:49 PM PDT 24 15307693230 ps
T15 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3703613320 May 09 01:56:03 PM PDT 24 May 09 01:58:06 PM PDT 24 1581756791 ps
T26 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3877601959 May 09 02:01:46 PM PDT 24 May 09 02:01:54 PM PDT 24 212468362 ps
T22 /workspace/coverage/default/21.sram_ctrl_stress_all.867383242 May 09 01:55:10 PM PDT 24 May 09 02:58:25 PM PDT 24 261889583048 ps
T27 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.87543936 May 09 01:56:55 PM PDT 24 May 09 01:57:13 PM PDT 24 2360121827 ps
T54 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2723259705 May 09 01:51:21 PM PDT 24 May 09 01:51:59 PM PDT 24 733632692 ps
T55 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.244694924 May 09 02:01:36 PM PDT 24 May 09 02:06:16 PM PDT 24 14542622231 ps
T43 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3982102578 May 09 01:54:27 PM PDT 24 May 09 02:21:34 PM PDT 24 81330486279 ps
T56 /workspace/coverage/default/41.sram_ctrl_max_throughput.3934443738 May 09 02:01:02 PM PDT 24 May 09 02:01:09 PM PDT 24 680646840 ps
T19 /workspace/coverage/default/15.sram_ctrl_alert_test.1405335582 May 09 01:53:25 PM PDT 24 May 09 01:53:28 PM PDT 24 20892809 ps
T57 /workspace/coverage/default/46.sram_ctrl_executable.3956573273 May 09 02:02:42 PM PDT 24 May 09 02:17:44 PM PDT 24 8824860711 ps
T5 /workspace/coverage/default/47.sram_ctrl_lc_escalation.3146142500 May 09 02:03:17 PM PDT 24 May 09 02:04:20 PM PDT 24 17990719862 ps
T72 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.4209607093 May 09 03:03:37 PM PDT 24 May 09 03:04:39 PM PDT 24 952596452 ps
T147 /workspace/coverage/default/27.sram_ctrl_partial_access.2672849734 May 09 01:56:33 PM PDT 24 May 09 01:57:26 PM PDT 24 1521674221 ps
T77 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3435702242 May 09 01:51:39 PM PDT 24 May 09 01:52:55 PM PDT 24 11355435459 ps
T78 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.4046097933 May 09 01:54:28 PM PDT 24 May 09 01:57:05 PM PDT 24 19511365998 ps
T149 /workspace/coverage/default/20.sram_ctrl_bijection.741455860 May 09 01:54:38 PM PDT 24 May 09 02:13:05 PM PDT 24 16233527671 ps
T79 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1028912973 May 09 02:00:21 PM PDT 24 May 09 02:02:30 PM PDT 24 1565850656 ps
T139 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3800890694 May 09 02:00:40 PM PDT 24 May 09 02:01:04 PM PDT 24 1508727044 ps
T143 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1719840742 May 09 02:02:12 PM PDT 24 May 09 02:02:49 PM PDT 24 3306995429 ps
T58 /workspace/coverage/default/0.sram_ctrl_regwen.3364223666 May 09 01:49:42 PM PDT 24 May 09 02:05:32 PM PDT 24 73745606717 ps
T150 /workspace/coverage/default/33.sram_ctrl_mem_walk.2666404031 May 09 01:58:56 PM PDT 24 May 09 02:00:57 PM PDT 24 2017209198 ps
T20 /workspace/coverage/default/39.sram_ctrl_alert_test.2490277553 May 09 02:00:43 PM PDT 24 May 09 02:00:44 PM PDT 24 34737180 ps
T151 /workspace/coverage/default/37.sram_ctrl_partial_access.1510631774 May 09 02:00:04 PM PDT 24 May 09 02:00:27 PM PDT 24 4703047366 ps
T91 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3401167256 May 09 02:01:03 PM PDT 24 May 09 02:05:49 PM PDT 24 19234210016 ps
T152 /workspace/coverage/default/13.sram_ctrl_max_throughput.4213773907 May 09 01:52:41 PM PDT 24 May 09 01:53:46 PM PDT 24 1578012752 ps
T29 /workspace/coverage/default/26.sram_ctrl_ram_cfg.2664975995 May 09 01:56:35 PM PDT 24 May 09 01:56:41 PM PDT 24 361254944 ps
T92 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.465307294 May 09 01:54:49 PM PDT 24 May 09 02:00:36 PM PDT 24 6280172829 ps
T30 /workspace/coverage/default/44.sram_ctrl_ram_cfg.3545756924 May 09 02:02:05 PM PDT 24 May 09 02:02:09 PM PDT 24 544776734 ps
T59 /workspace/coverage/default/24.sram_ctrl_stress_all.4121669214 May 09 01:56:01 PM PDT 24 May 09 02:57:53 PM PDT 24 105443882603 ps
T144 /workspace/coverage/default/46.sram_ctrl_multiple_keys.1926744733 May 09 02:02:38 PM PDT 24 May 09 02:12:38 PM PDT 24 36853734756 ps
T122 /workspace/coverage/default/29.sram_ctrl_executable.2626057494 May 09 01:57:36 PM PDT 24 May 09 02:04:44 PM PDT 24 25511810146 ps
T21 /workspace/coverage/default/26.sram_ctrl_alert_test.4102497387 May 09 01:56:33 PM PDT 24 May 09 01:56:36 PM PDT 24 23193699 ps
T44 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.2774330049 May 09 01:57:05 PM PDT 24 May 09 02:04:14 PM PDT 24 6185824428 ps
T93 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.995037832 May 09 01:59:49 PM PDT 24 May 09 02:08:06 PM PDT 24 21202001298 ps
T31 /workspace/coverage/default/11.sram_ctrl_ram_cfg.2653635530 May 09 01:52:34 PM PDT 24 May 09 01:52:39 PM PDT 24 1529055431 ps
T23 /workspace/coverage/default/43.sram_ctrl_stress_all.1975457862 May 09 02:01:53 PM PDT 24 May 09 02:55:40 PM PDT 24 86121482038 ps
T24 /workspace/coverage/default/20.sram_ctrl_regwen.4076894841 May 09 01:54:36 PM PDT 24 May 09 02:02:45 PM PDT 24 9464965862 ps
T6 /workspace/coverage/default/16.sram_ctrl_stress_all.580329106 May 09 01:53:49 PM PDT 24 May 09 02:45:08 PM PDT 24 68085482781 ps
T46 /workspace/coverage/default/20.sram_ctrl_executable.3589609648 May 09 01:54:38 PM PDT 24 May 09 02:18:48 PM PDT 24 132311451544 ps
T153 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.954053195 May 09 01:53:57 PM PDT 24 May 09 01:56:59 PM PDT 24 3915665256 ps
T28 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1808401840 May 09 01:54:20 PM PDT 24 May 09 01:54:27 PM PDT 24 1039474231 ps
T60 /workspace/coverage/default/40.sram_ctrl_regwen.2030439636 May 09 02:00:49 PM PDT 24 May 09 02:24:44 PM PDT 24 47701130360 ps
T137 /workspace/coverage/default/37.sram_ctrl_multiple_keys.1878264963 May 09 01:59:52 PM PDT 24 May 09 02:13:41 PM PDT 24 18262865946 ps
T129 /workspace/coverage/default/2.sram_ctrl_executable.274779697 May 09 01:50:01 PM PDT 24 May 09 02:19:41 PM PDT 24 24285857576 ps
T154 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.4137340943 May 09 01:53:39 PM PDT 24 May 09 01:56:38 PM PDT 24 2895158870 ps
T132 /workspace/coverage/default/6.sram_ctrl_multiple_keys.3380753519 May 09 01:50:52 PM PDT 24 May 09 02:00:05 PM PDT 24 16837919418 ps
T155 /workspace/coverage/default/18.sram_ctrl_bijection.3971106972 May 09 01:53:57 PM PDT 24 May 09 02:04:57 PM PDT 24 39633753255 ps
T45 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2557138620 May 09 01:58:11 PM PDT 24 May 09 02:20:06 PM PDT 24 14782150306 ps
T135 /workspace/coverage/default/30.sram_ctrl_bijection.3290413037 May 09 01:57:50 PM PDT 24 May 09 02:28:20 PM PDT 24 315519991162 ps
T138 /workspace/coverage/default/0.sram_ctrl_alert_test.4247163511 May 09 01:49:54 PM PDT 24 May 09 01:49:57 PM PDT 24 22538941 ps
T61 /workspace/coverage/default/22.sram_ctrl_regwen.1268464070 May 09 01:55:22 PM PDT 24 May 09 02:08:24 PM PDT 24 12782414853 ps
T148 /workspace/coverage/default/15.sram_ctrl_executable.2513531601 May 09 01:53:25 PM PDT 24 May 09 02:03:18 PM PDT 24 12373217008 ps
T134 /workspace/coverage/default/32.sram_ctrl_ram_cfg.3145938231 May 09 01:58:42 PM PDT 24 May 09 01:58:46 PM PDT 24 743732588 ps
T156 /workspace/coverage/default/41.sram_ctrl_stress_all.1380085758 May 09 02:01:12 PM PDT 24 May 09 04:47:02 PM PDT 24 417071979456 ps
T157 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1682373577 May 09 01:56:35 PM PDT 24 May 09 02:01:53 PM PDT 24 28423857329 ps
T47 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2425670092 May 09 01:53:26 PM PDT 24 May 09 01:53:32 PM PDT 24 960832843 ps
T158 /workspace/coverage/default/12.sram_ctrl_partial_access.4004256985 May 09 01:52:34 PM PDT 24 May 09 01:52:41 PM PDT 24 444300633 ps
T80 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.203497884 May 09 01:56:24 PM PDT 24 May 09 01:59:01 PM PDT 24 18241486675 ps
T159 /workspace/coverage/default/39.sram_ctrl_partial_access.964145387 May 09 02:00:30 PM PDT 24 May 09 02:00:53 PM PDT 24 4426178877 ps
T160 /workspace/coverage/default/21.sram_ctrl_smoke.1663055937 May 09 01:54:49 PM PDT 24 May 09 01:55:09 PM PDT 24 1729591458 ps
T87 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.166549686 May 09 01:52:20 PM PDT 24 May 09 01:53:35 PM PDT 24 10678435252 ps
T161 /workspace/coverage/default/41.sram_ctrl_smoke.3621666059 May 09 02:00:52 PM PDT 24 May 09 02:01:35 PM PDT 24 756980022 ps
T162 /workspace/coverage/default/47.sram_ctrl_smoke.3800102256 May 09 02:02:54 PM PDT 24 May 09 02:03:10 PM PDT 24 2045998801 ps
T163 /workspace/coverage/default/15.sram_ctrl_partial_access.2758053708 May 09 01:53:13 PM PDT 24 May 09 01:53:35 PM PDT 24 663230738 ps
T164 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1523315276 May 09 01:50:41 PM PDT 24 May 09 01:51:57 PM PDT 24 4200703769 ps
T165 /workspace/coverage/default/49.sram_ctrl_partial_access.4083210795 May 09 02:03:44 PM PDT 24 May 09 02:03:50 PM PDT 24 1461886233 ps
T166 /workspace/coverage/default/22.sram_ctrl_bijection.3160529678 May 09 01:55:09 PM PDT 24 May 09 02:08:29 PM PDT 24 47053343383 ps
T167 /workspace/coverage/default/19.sram_ctrl_ram_cfg.1703200268 May 09 01:54:28 PM PDT 24 May 09 01:54:32 PM PDT 24 363040277 ps
T145 /workspace/coverage/default/41.sram_ctrl_executable.170028856 May 09 02:01:01 PM PDT 24 May 09 02:11:09 PM PDT 24 18994952650 ps
T168 /workspace/coverage/default/22.sram_ctrl_alert_test.3522816694 May 09 01:55:31 PM PDT 24 May 09 01:55:32 PM PDT 24 14435967 ps
T169 /workspace/coverage/default/7.sram_ctrl_smoke.2212314834 May 09 01:51:12 PM PDT 24 May 09 01:51:21 PM PDT 24 2953121149 ps
T121 /workspace/coverage/default/1.sram_ctrl_regwen.683472596 May 09 01:49:54 PM PDT 24 May 09 02:05:54 PM PDT 24 16407003341 ps
T170 /workspace/coverage/default/21.sram_ctrl_bijection.2622743748 May 09 01:54:49 PM PDT 24 May 09 02:21:43 PM PDT 24 931533088102 ps
T171 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3050345524 May 09 01:52:42 PM PDT 24 May 09 01:54:55 PM PDT 24 2852455145 ps
T7 /workspace/coverage/default/4.sram_ctrl_lc_escalation.2044555842 May 09 01:50:30 PM PDT 24 May 09 01:51:45 PM PDT 24 12554533522 ps
T172 /workspace/coverage/default/19.sram_ctrl_bijection.4235790266 May 09 01:54:18 PM PDT 24 May 09 02:26:05 PM PDT 24 210419004913 ps
T125 /workspace/coverage/default/40.sram_ctrl_multiple_keys.3512658536 May 09 02:00:40 PM PDT 24 May 09 02:26:12 PM PDT 24 46012680742 ps
T173 /workspace/coverage/default/28.sram_ctrl_partial_access.1820949020 May 09 01:57:05 PM PDT 24 May 09 01:59:11 PM PDT 24 1249389450 ps
T130 /workspace/coverage/default/14.sram_ctrl_stress_all.3478312594 May 09 01:53:14 PM PDT 24 May 09 03:29:20 PM PDT 24 134083790511 ps
T174 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3733563918 May 09 02:03:53 PM PDT 24 May 09 02:12:36 PM PDT 24 28313154018 ps
T25 /workspace/coverage/default/23.sram_ctrl_stress_all.749194239 May 09 01:55:41 PM PDT 24 May 09 02:23:01 PM PDT 24 197431929737 ps
T175 /workspace/coverage/default/2.sram_ctrl_lc_escalation.2405423767 May 09 01:50:02 PM PDT 24 May 09 01:51:24 PM PDT 24 14360213640 ps
T176 /workspace/coverage/default/48.sram_ctrl_multiple_keys.3558252391 May 09 02:03:18 PM PDT 24 May 09 02:32:28 PM PDT 24 20695629310 ps
T177 /workspace/coverage/default/30.sram_ctrl_executable.1313494416 May 09 01:58:00 PM PDT 24 May 09 02:03:44 PM PDT 24 39513602667 ps
T146 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1523176687 May 09 02:03:18 PM PDT 24 May 09 02:10:41 PM PDT 24 5040597172 ps
T178 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3195706911 May 09 01:55:46 PM PDT 24 May 09 01:58:17 PM PDT 24 4376309629 ps
T179 /workspace/coverage/default/37.sram_ctrl_ram_cfg.58600236 May 09 02:00:12 PM PDT 24 May 09 02:00:16 PM PDT 24 359118937 ps
T180 /workspace/coverage/default/46.sram_ctrl_smoke.97060904 May 09 02:02:36 PM PDT 24 May 09 02:02:53 PM PDT 24 1236648896 ps
T181 /workspace/coverage/default/13.sram_ctrl_alert_test.2410864760 May 09 01:52:51 PM PDT 24 May 09 01:52:53 PM PDT 24 31538645 ps
T182 /workspace/coverage/default/49.sram_ctrl_ram_cfg.463991071 May 09 02:03:52 PM PDT 24 May 09 02:03:57 PM PDT 24 700415908 ps
T183 /workspace/coverage/default/41.sram_ctrl_ram_cfg.1274685745 May 09 02:01:03 PM PDT 24 May 09 02:01:07 PM PDT 24 350782192 ps
T184 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2583582584 May 09 01:57:06 PM PDT 24 May 09 01:57:43 PM PDT 24 8949208150 ps
T185 /workspace/coverage/default/39.sram_ctrl_max_throughput.93977924 May 09 02:00:45 PM PDT 24 May 09 02:01:12 PM PDT 24 745373541 ps
T186 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.622660663 May 09 02:02:06 PM PDT 24 May 09 02:04:50 PM PDT 24 12855947078 ps
T131 /workspace/coverage/default/36.sram_ctrl_lc_escalation.1865049374 May 09 01:59:49 PM PDT 24 May 09 02:00:33 PM PDT 24 15666736101 ps
T187 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3546245183 May 09 01:50:00 PM PDT 24 May 09 01:52:38 PM PDT 24 2781318557 ps
T188 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1097753284 May 09 02:02:30 PM PDT 24 May 09 02:07:17 PM PDT 24 17814222841 ps
T136 /workspace/coverage/default/32.sram_ctrl_lc_escalation.2289796874 May 09 01:58:30 PM PDT 24 May 09 02:00:05 PM PDT 24 33282681955 ps
T189 /workspace/coverage/default/32.sram_ctrl_mem_walk.1716737505 May 09 01:58:38 PM PDT 24 May 09 02:03:43 PM PDT 24 27606439711 ps
T190 /workspace/coverage/default/21.sram_ctrl_multiple_keys.4100780523 May 09 01:54:48 PM PDT 24 May 09 02:05:50 PM PDT 24 10303882581 ps
T191 /workspace/coverage/default/11.sram_ctrl_bijection.2712968349 May 09 01:52:09 PM PDT 24 May 09 02:04:17 PM PDT 24 32816234537 ps
T192 /workspace/coverage/default/38.sram_ctrl_multiple_keys.1326302208 May 09 02:00:12 PM PDT 24 May 09 02:15:51 PM PDT 24 59765224219 ps
T140 /workspace/coverage/default/44.sram_ctrl_regwen.3250054967 May 09 02:02:02 PM PDT 24 May 09 02:14:01 PM PDT 24 97882581438 ps
T193 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2591525433 May 09 01:52:52 PM PDT 24 May 09 01:53:02 PM PDT 24 695583245 ps
T194 /workspace/coverage/default/41.sram_ctrl_multiple_keys.3046850840 May 09 02:00:54 PM PDT 24 May 09 02:01:16 PM PDT 24 3208008521 ps
T141 /workspace/coverage/default/13.sram_ctrl_lc_escalation.4067814163 May 09 01:52:40 PM PDT 24 May 09 01:53:42 PM PDT 24 17106492520 ps
T195 /workspace/coverage/default/3.sram_ctrl_smoke.1617605776 May 09 01:50:11 PM PDT 24 May 09 01:50:24 PM PDT 24 2053831209 ps
T196 /workspace/coverage/default/46.sram_ctrl_max_throughput.305319375 May 09 02:02:35 PM PDT 24 May 09 02:04:32 PM PDT 24 1565093957 ps
T197 /workspace/coverage/default/43.sram_ctrl_mem_walk.1443731054 May 09 02:01:43 PM PDT 24 May 09 02:03:43 PM PDT 24 2017878689 ps
T198 /workspace/coverage/default/48.sram_ctrl_mem_walk.3321286437 May 09 02:03:28 PM PDT 24 May 09 02:05:58 PM PDT 24 27579370651 ps
T199 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.248564416 May 09 01:57:38 PM PDT 24 May 09 02:15:57 PM PDT 24 16423959638 ps
T200 /workspace/coverage/default/1.sram_ctrl_max_throughput.2197235499 May 09 01:49:54 PM PDT 24 May 09 01:52:27 PM PDT 24 768345300 ps
T201 /workspace/coverage/default/9.sram_ctrl_multiple_keys.2176394910 May 09 01:51:45 PM PDT 24 May 09 02:03:12 PM PDT 24 4917016424 ps
T133 /workspace/coverage/default/2.sram_ctrl_stress_all.494127206 May 09 01:50:11 PM PDT 24 May 09 03:19:02 PM PDT 24 100253641865 ps
T142 /workspace/coverage/default/16.sram_ctrl_multiple_keys.4024205028 May 09 01:53:39 PM PDT 24 May 09 02:11:09 PM PDT 24 8394209291 ps
T202 /workspace/coverage/default/13.sram_ctrl_executable.1587134347 May 09 01:52:42 PM PDT 24 May 09 02:20:54 PM PDT 24 53151890225 ps
T203 /workspace/coverage/default/43.sram_ctrl_executable.3546842564 May 09 02:01:42 PM PDT 24 May 09 02:10:16 PM PDT 24 27913355554 ps
T204 /workspace/coverage/default/14.sram_ctrl_executable.1139738122 May 09 01:53:03 PM PDT 24 May 09 01:57:26 PM PDT 24 7596750410 ps
T205 /workspace/coverage/default/11.sram_ctrl_regwen.2403317074 May 09 01:52:19 PM PDT 24 May 09 02:12:13 PM PDT 24 10933188049 ps
T206 /workspace/coverage/default/25.sram_ctrl_regwen.372225007 May 09 01:56:24 PM PDT 24 May 09 02:07:35 PM PDT 24 25832673976 ps
T207 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.551515341 May 09 01:50:00 PM PDT 24 May 09 02:10:42 PM PDT 24 47509269679 ps
T208 /workspace/coverage/default/14.sram_ctrl_smoke.1671786920 May 09 01:52:52 PM PDT 24 May 09 01:52:59 PM PDT 24 358232844 ps
T209 /workspace/coverage/default/18.sram_ctrl_regwen.2234267269 May 09 01:54:20 PM PDT 24 May 09 02:00:47 PM PDT 24 3144638312 ps
T210 /workspace/coverage/default/5.sram_ctrl_max_throughput.868184413 May 09 01:50:43 PM PDT 24 May 09 01:52:07 PM PDT 24 779277290 ps
T211 /workspace/coverage/default/16.sram_ctrl_mem_walk.616572784 May 09 01:53:39 PM PDT 24 May 09 01:56:01 PM PDT 24 7891645351 ps
T212 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.1697951881 May 09 01:57:08 PM PDT 24 May 09 02:01:42 PM PDT 24 4700482069 ps
T213 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.4264493376 May 09 01:56:14 PM PDT 24 May 09 01:59:23 PM PDT 24 3853537676 ps
T214 /workspace/coverage/default/30.sram_ctrl_ram_cfg.2638021920 May 09 01:58:01 PM PDT 24 May 09 01:58:06 PM PDT 24 1425196589 ps
T48 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2110975436 May 09 01:53:57 PM PDT 24 May 09 01:54:23 PM PDT 24 641342348 ps
T215 /workspace/coverage/default/24.sram_ctrl_alert_test.827921616 May 09 01:56:01 PM PDT 24 May 09 01:56:03 PM PDT 24 13333303 ps
T216 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3223094517 May 09 02:03:18 PM PDT 24 May 09 02:03:41 PM PDT 24 3344844595 ps
T217 /workspace/coverage/default/43.sram_ctrl_lc_escalation.3183807047 May 09 02:01:43 PM PDT 24 May 09 02:02:49 PM PDT 24 38336661545 ps
T218 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3257291709 May 09 01:56:43 PM PDT 24 May 09 02:01:55 PM PDT 24 26889941167 ps
T219 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.4034867359 May 09 01:57:36 PM PDT 24 May 09 02:01:21 PM PDT 24 3627590310 ps
T220 /workspace/coverage/default/11.sram_ctrl_executable.800885550 May 09 01:52:18 PM PDT 24 May 09 01:59:03 PM PDT 24 17256077938 ps
T221 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3520879172 May 09 01:52:19 PM PDT 24 May 09 01:57:56 PM PDT 24 7537946769 ps
T126 /workspace/coverage/default/44.sram_ctrl_multiple_keys.1213273493 May 09 02:01:53 PM PDT 24 May 09 02:12:37 PM PDT 24 11256734314 ps
T222 /workspace/coverage/default/21.sram_ctrl_max_throughput.3811655946 May 09 01:54:59 PM PDT 24 May 09 01:55:17 PM PDT 24 727207032 ps
T223 /workspace/coverage/default/31.sram_ctrl_smoke.531400992 May 09 01:58:09 PM PDT 24 May 09 01:58:25 PM PDT 24 848813910 ps
T224 /workspace/coverage/default/16.sram_ctrl_partial_access.2046401141 May 09 01:53:37 PM PDT 24 May 09 01:53:45 PM PDT 24 2742427063 ps
T49 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.327536850 May 09 01:49:41 PM PDT 24 May 09 01:50:03 PM PDT 24 684850828 ps
T225 /workspace/coverage/default/41.sram_ctrl_bijection.1694992722 May 09 02:00:51 PM PDT 24 May 09 02:15:12 PM PDT 24 12647855966 ps
T226 /workspace/coverage/default/4.sram_ctrl_smoke.3471391609 May 09 01:50:22 PM PDT 24 May 09 01:50:39 PM PDT 24 3129132422 ps
T123 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.159681032 May 09 01:53:57 PM PDT 24 May 09 01:55:24 PM PDT 24 11388219942 ps
T227 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3751213423 May 09 01:51:34 PM PDT 24 May 09 01:52:04 PM PDT 24 731804177 ps
T228 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.4285870681 May 09 01:51:56 PM PDT 24 May 09 01:55:56 PM PDT 24 23714637380 ps
T229 /workspace/coverage/default/20.sram_ctrl_ram_cfg.1261604919 May 09 01:54:37 PM PDT 24 May 09 01:54:41 PM PDT 24 1410441068 ps
T230 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.129802506 May 09 01:53:37 PM PDT 24 May 09 01:57:43 PM PDT 24 7788254478 ps
T231 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.350112230 May 09 01:55:24 PM PDT 24 May 09 01:59:02 PM PDT 24 23615380813 ps
T232 /workspace/coverage/default/42.sram_ctrl_executable.4240953943 May 09 02:01:30 PM PDT 24 May 09 02:27:47 PM PDT 24 8157700545 ps
T233 /workspace/coverage/default/34.sram_ctrl_alert_test.4143629300 May 09 01:59:22 PM PDT 24 May 09 01:59:24 PM PDT 24 42266229 ps
T234 /workspace/coverage/default/39.sram_ctrl_lc_escalation.3743176372 May 09 02:00:41 PM PDT 24 May 09 02:02:21 PM PDT 24 63140822789 ps
T235 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3266799430 May 09 01:51:22 PM PDT 24 May 09 01:52:02 PM PDT 24 2025126205 ps
T236 /workspace/coverage/default/49.sram_ctrl_mem_walk.2259612911 May 09 02:03:54 PM PDT 24 May 09 02:08:38 PM PDT 24 27040927829 ps
T237 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.570580564 May 09 02:00:03 PM PDT 24 May 09 02:00:38 PM PDT 24 3296762335 ps
T124 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2964790965 May 09 01:53:49 PM PDT 24 May 09 01:57:38 PM PDT 24 10274330256 ps
T238 /workspace/coverage/default/29.sram_ctrl_partial_access.1930429159 May 09 01:57:37 PM PDT 24 May 09 01:58:42 PM PDT 24 3443568793 ps
T239 /workspace/coverage/default/38.sram_ctrl_executable.3480833711 May 09 02:00:20 PM PDT 24 May 09 02:01:06 PM PDT 24 1167219094 ps
T240 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.307761540 May 09 01:49:53 PM PDT 24 May 09 02:03:26 PM PDT 24 10914633732 ps
T241 /workspace/coverage/default/17.sram_ctrl_lc_escalation.3471895068 May 09 01:53:57 PM PDT 24 May 09 01:55:18 PM PDT 24 45214258083 ps
T242 /workspace/coverage/default/31.sram_ctrl_regwen.1956133138 May 09 01:58:19 PM PDT 24 May 09 02:02:12 PM PDT 24 5887146125 ps
T243 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.966246261 May 09 01:53:25 PM PDT 24 May 09 01:58:31 PM PDT 24 6105386364 ps
T244 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1690023803 May 09 01:54:27 PM PDT 24 May 09 01:56:03 PM PDT 24 3226427919 ps
T105 /workspace/coverage/default/31.sram_ctrl_stress_all.4162518645 May 09 01:58:20 PM PDT 24 May 09 03:30:39 PM PDT 24 893190708473 ps
T245 /workspace/coverage/default/10.sram_ctrl_multiple_keys.72886996 May 09 01:51:59 PM PDT 24 May 09 01:57:10 PM PDT 24 4194569028 ps
T246 /workspace/coverage/default/6.sram_ctrl_alert_test.1055685182 May 09 01:51:14 PM PDT 24 May 09 01:51:16 PM PDT 24 12878431 ps
T247 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.2225228526 May 09 01:53:38 PM PDT 24 May 09 02:01:20 PM PDT 24 35779047442 ps
T248 /workspace/coverage/default/40.sram_ctrl_partial_access.3184937975 May 09 02:00:41 PM PDT 24 May 09 02:01:02 PM PDT 24 2712541204 ps
T127 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.955105879 May 09 01:55:32 PM PDT 24 May 09 02:01:23 PM PDT 24 16314917080 ps
T249 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.4279359110 May 09 01:50:02 PM PDT 24 May 09 01:58:07 PM PDT 24 49475423165 ps
T250 /workspace/coverage/default/26.sram_ctrl_multiple_keys.264170786 May 09 01:56:25 PM PDT 24 May 09 02:13:26 PM PDT 24 91030243096 ps
T251 /workspace/coverage/default/27.sram_ctrl_alert_test.3632347934 May 09 01:56:58 PM PDT 24 May 09 01:56:59 PM PDT 24 154562053 ps
T252 /workspace/coverage/default/27.sram_ctrl_mem_walk.69270570 May 09 01:56:43 PM PDT 24 May 09 01:59:21 PM PDT 24 60824976889 ps
T253 /workspace/coverage/default/35.sram_ctrl_multiple_keys.2418741275 May 09 01:59:22 PM PDT 24 May 09 02:06:15 PM PDT 24 14393760968 ps
T254 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1204486715 May 09 02:02:40 PM PDT 24 May 09 02:06:15 PM PDT 24 4687930065 ps
T255 /workspace/coverage/default/34.sram_ctrl_partial_access.3942942819 May 09 01:59:00 PM PDT 24 May 09 02:00:21 PM PDT 24 805206552 ps
T256 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2167294785 May 09 01:59:26 PM PDT 24 May 09 02:11:49 PM PDT 24 7929825298 ps
T257 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1958657270 May 09 01:52:09 PM PDT 24 May 09 01:55:44 PM PDT 24 10670111292 ps
T258 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.616674236 May 09 02:03:29 PM PDT 24 May 09 02:08:57 PM PDT 24 9046329212 ps
T50 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3273307760 May 09 02:02:02 PM PDT 24 May 09 02:02:08 PM PDT 24 148164775 ps
T259 /workspace/coverage/default/3.sram_ctrl_max_throughput.3334898362 May 09 01:50:10 PM PDT 24 May 09 01:51:15 PM PDT 24 2942129035 ps
T260 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.4161607518 May 09 02:03:18 PM PDT 24 May 09 02:04:18 PM PDT 24 952152968 ps
T51 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.956948442 May 09 01:51:14 PM PDT 24 May 09 01:53:19 PM PDT 24 1271687109 ps
T261 /workspace/coverage/default/17.sram_ctrl_alert_test.3124022179 May 09 01:53:56 PM PDT 24 May 09 01:53:58 PM PDT 24 15244004 ps
T52 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.14671662 May 09 01:51:24 PM PDT 24 May 09 01:53:34 PM PDT 24 5260036754 ps
T262 /workspace/coverage/default/26.sram_ctrl_mem_walk.2658024894 May 09 01:56:33 PM PDT 24 May 09 02:01:05 PM PDT 24 14346750995 ps
T53 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.23553326 May 09 01:50:23 PM PDT 24 May 09 01:51:37 PM PDT 24 8569243270 ps
T128 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3397355557 May 09 02:02:54 PM PDT 24 May 09 02:10:34 PM PDT 24 115844434099 ps
T263 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.3699494886 May 09 02:00:11 PM PDT 24 May 09 02:01:20 PM PDT 24 3806707264 ps
T264 /workspace/coverage/default/28.sram_ctrl_ram_cfg.1924232512 May 09 01:57:16 PM PDT 24 May 09 01:57:21 PM PDT 24 363484954 ps
T265 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3053878820 May 09 01:50:10 PM PDT 24 May 09 01:50:23 PM PDT 24 221921025 ps
T266 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1649510836 May 09 01:51:35 PM PDT 24 May 09 01:55:10 PM PDT 24 10840948635 ps
T267 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3443277035 May 09 01:56:15 PM PDT 24 May 09 01:58:30 PM PDT 24 1703234404 ps
T268 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2972017911 May 09 02:00:50 PM PDT 24 May 09 02:01:10 PM PDT 24 835951839 ps
T106 /workspace/coverage/default/20.sram_ctrl_lc_escalation.2779839522 May 09 01:54:37 PM PDT 24 May 09 01:54:48 PM PDT 24 1392064938 ps
T269 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3503979844 May 09 01:59:00 PM PDT 24 May 09 01:59:44 PM PDT 24 1715923804 ps
T270 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2521712140 May 09 01:52:53 PM PDT 24 May 09 01:57:52 PM PDT 24 92157184587 ps
T271 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3076214706 May 09 02:01:46 PM PDT 24 May 09 02:19:57 PM PDT 24 10230169124 ps
T272 /workspace/coverage/default/43.sram_ctrl_max_throughput.2516174345 May 09 02:01:34 PM PDT 24 May 09 02:03:27 PM PDT 24 787153885 ps
T273 /workspace/coverage/default/13.sram_ctrl_bijection.2132970593 May 09 01:52:42 PM PDT 24 May 09 02:14:26 PM PDT 24 155194722834 ps
T274 /workspace/coverage/default/3.sram_ctrl_stress_all.2944359403 May 09 01:50:20 PM PDT 24 May 09 03:20:56 PM PDT 24 308697264649 ps
T275 /workspace/coverage/default/23.sram_ctrl_mem_walk.800906827 May 09 01:55:42 PM PDT 24 May 09 01:57:43 PM PDT 24 4291055936 ps
T276 /workspace/coverage/default/45.sram_ctrl_smoke.1734108863 May 09 02:02:13 PM PDT 24 May 09 02:02:28 PM PDT 24 8024068747 ps
T277 /workspace/coverage/default/22.sram_ctrl_max_throughput.2792142627 May 09 01:55:21 PM PDT 24 May 09 01:55:42 PM PDT 24 1536129426 ps
T278 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3513370606 May 09 01:50:59 PM PDT 24 May 09 01:51:28 PM PDT 24 2900482829 ps
T279 /workspace/coverage/default/46.sram_ctrl_mem_walk.4216566951 May 09 02:02:43 PM PDT 24 May 09 02:05:16 PM PDT 24 24029852695 ps
T280 /workspace/coverage/default/2.sram_ctrl_mem_walk.1786719324 May 09 01:50:01 PM PDT 24 May 09 01:55:06 PM PDT 24 17924788667 ps
T281 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.2882919382 May 09 01:50:21 PM PDT 24 May 09 02:06:20 PM PDT 24 22126654801 ps
T282 /workspace/coverage/default/24.sram_ctrl_executable.1490029103 May 09 01:55:52 PM PDT 24 May 09 02:16:21 PM PDT 24 69380714909 ps
T283 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1334517250 May 09 01:50:51 PM PDT 24 May 09 01:51:53 PM PDT 24 970153383 ps
T284 /workspace/coverage/default/40.sram_ctrl_alert_test.3465008147 May 09 02:00:52 PM PDT 24 May 09 02:00:54 PM PDT 24 12902278 ps
T285 /workspace/coverage/default/47.sram_ctrl_ram_cfg.3331585260 May 09 02:03:17 PM PDT 24 May 09 02:03:22 PM PDT 24 1357129874 ps
T286 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1747294375 May 09 01:59:21 PM PDT 24 May 09 02:00:20 PM PDT 24 3053488843 ps
T287 /workspace/coverage/default/44.sram_ctrl_lc_escalation.4221458920 May 09 02:02:03 PM PDT 24 May 09 02:03:24 PM PDT 24 13534623505 ps
T288 /workspace/coverage/default/44.sram_ctrl_alert_test.1370807208 May 09 02:02:13 PM PDT 24 May 09 02:02:14 PM PDT 24 12362837 ps
T289 /workspace/coverage/default/26.sram_ctrl_executable.901711773 May 09 01:56:35 PM PDT 24 May 09 02:04:36 PM PDT 24 7267169479 ps
T290 /workspace/coverage/default/12.sram_ctrl_ram_cfg.49708607 May 09 01:52:32 PM PDT 24 May 09 01:52:38 PM PDT 24 1340996967 ps
T291 /workspace/coverage/default/24.sram_ctrl_regwen.2511979483 May 09 01:56:01 PM PDT 24 May 09 02:00:30 PM PDT 24 24242546313 ps
T292 /workspace/coverage/default/41.sram_ctrl_alert_test.92087542 May 09 02:01:11 PM PDT 24 May 09 02:01:12 PM PDT 24 46835853 ps
T293 /workspace/coverage/default/19.sram_ctrl_regwen.734278331 May 09 01:54:27 PM PDT 24 May 09 01:58:39 PM PDT 24 836683304 ps
T294 /workspace/coverage/default/39.sram_ctrl_bijection.3357220727 May 09 02:00:31 PM PDT 24 May 09 02:41:25 PM PDT 24 158196715463 ps
T295 /workspace/coverage/default/2.sram_ctrl_multiple_keys.2634473786 May 09 01:50:01 PM PDT 24 May 09 02:06:44 PM PDT 24 96812980185 ps
T296 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3417856945 May 09 01:56:25 PM PDT 24 May 09 02:03:42 PM PDT 24 35493960658 ps
T297 /workspace/coverage/default/6.sram_ctrl_regwen.3850425852 May 09 01:51:01 PM PDT 24 May 09 02:15:00 PM PDT 24 27331062359 ps
T298 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.1469041086 May 09 01:54:48 PM PDT 24 May 09 01:55:52 PM PDT 24 951098749 ps
T299 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.4293942215 May 09 01:58:11 PM PDT 24 May 09 02:11:09 PM PDT 24 142024962094 ps
T300 /workspace/coverage/default/34.sram_ctrl_lc_escalation.285150106 May 09 01:59:12 PM PDT 24 May 09 01:59:41 PM PDT 24 16915677941 ps
T301 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.788485113 May 09 01:53:11 PM PDT 24 May 09 01:56:54 PM PDT 24 59878710493 ps
T302 /workspace/coverage/default/11.sram_ctrl_smoke.3847032687 May 09 01:52:14 PM PDT 24 May 09 01:52:31 PM PDT 24 3345810214 ps
T303 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.3105190006 May 09 01:52:17 PM PDT 24 May 09 02:12:15 PM PDT 24 62650478735 ps
T304 /workspace/coverage/default/20.sram_ctrl_partial_access.2330579443 May 09 01:54:36 PM PDT 24 May 09 01:55:01 PM PDT 24 7819938815 ps
T305 /workspace/coverage/default/15.sram_ctrl_ram_cfg.1085120204 May 09 01:53:28 PM PDT 24 May 09 01:53:32 PM PDT 24 620641491 ps
T306 /workspace/coverage/default/5.sram_ctrl_mem_walk.656753416 May 09 01:50:52 PM PDT 24 May 09 01:54:56 PM PDT 24 8042002739 ps
T307 /workspace/coverage/default/21.sram_ctrl_partial_access.794493383 May 09 01:54:49 PM PDT 24 May 09 01:57:55 PM PDT 24 5791465089 ps
T308 /workspace/coverage/default/29.sram_ctrl_max_throughput.3180601269 May 09 01:57:40 PM PDT 24 May 09 01:59:53 PM PDT 24 1561768048 ps
T309 /workspace/coverage/default/42.sram_ctrl_lc_escalation.3853115104 May 09 02:01:17 PM PDT 24 May 09 02:02:03 PM PDT 24 7001986389 ps
T310 /workspace/coverage/default/10.sram_ctrl_lc_escalation.3766539979 May 09 01:52:12 PM PDT 24 May 09 01:52:23 PM PDT 24 2711063777 ps
T311 /workspace/coverage/default/44.sram_ctrl_stress_all.605832234 May 09 02:02:13 PM PDT 24 May 09 03:11:39 PM PDT 24 203423720888 ps
T312 /workspace/coverage/default/6.sram_ctrl_ram_cfg.1621183402 May 09 01:51:01 PM PDT 24 May 09 01:51:06 PM PDT 24 353788637 ps
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