Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	145460977	1			T1	1543		T2	56248		T3	6663
triple_byte_access	2830469	1			T1	3593		T2	1134		T3	149
halfword_access	4346355	1			T1	6880		T2	1683		T3	196
byte_access	6085747	1			T1	13046		T2	2193		T3	255
zero_access	1851028	1			T1	7498		T2	550		T3	73

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80081338

1

T1

16177

T2

33667

T3

3664

auto[1]

80493238

1

T1

16383

T2

28141

T3

3672

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	72383711	1			T1	146		T2	30689		T3	3301
auto[0]	triple_byte_access	1345910	1			T1	679		T2	611		T3	80
auto[0]	halfword_access	2122985	1			T1	2357		T2	909		T3	109
auto[0]	byte_access	3120100	1			T1	6970		T2	1164		T3	127
auto[0]	zero_access	1108632	1			T1	6025		T2	294		T3	47
auto[1]	word_access	73077266	1			T1	1397		T2	25559		T3	3362
auto[1]	triple_byte_access	1484559	1			T1	2914		T2	523		T3	69
auto[1]	halfword_access	2223370	1			T1	4523		T2	774		T3	87
auto[1]	byte_access	2965647	1			T1	6076		T2	1029		T3	128
auto[1]	zero_access	742396	1			T1	1473		T2	256		T3	26